CN111864833A - Low-power-consumption starting circuit awakened through USB interface and power supply device - Google Patents
Low-power-consumption starting circuit awakened through USB interface and power supply device Download PDFInfo
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- CN111864833A CN111864833A CN202010641174.1A CN202010641174A CN111864833A CN 111864833 A CN111864833 A CN 111864833A CN 202010641174 A CN202010641174 A CN 202010641174A CN 111864833 A CN111864833 A CN 111864833A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/10—Control circuit supply, e.g. means for supplying power to the control circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/20—Charging or discharging characterised by the power electronics converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/30—Charge provided using DC bus or data bus of a computer
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Abstract
The invention relates to a low-power-consumption starting circuit awakened through a USB interface and a power supply device, comprising: the USB interface comprises an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control circuit and a USB interface; the USB interface comprises an insertion end, an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control end, a voltage stabilizing circuit and a USB interface, wherein the insertion end of the USB interface is used for being connected with a load, the input end of the energy storage circuit and the input end of the first switch circuit are connected with an input voltage, the output end of the first switch circuit is connected with the input end of the voltage stabilizing circuit, the control end of the first switch circuit is connected with the control circuit, the output; when the plug end of the USB interface is connected with a load, the first switch circuit is switched on, the input voltage is transmitted to the voltage stabilizing circuit through the first switch circuit, the voltage stabilizing circuit processes the input voltage and outputs working voltage to the control circuit, and the control circuit wakes up to start according to the working voltage. When the USB interface is in standby, the internal circuit stops working completely, the USB interface is started when being connected to a load, the standby power consumption is low, and the standby current can reach below 5 uA.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a low-power-consumption startup circuit awakened through a USB interface and a power supply device.
Background
With the development of electronic technology, the existing battery products generally require low power consumption design, and the current common mode is to realize wake-up detection through a USB interface load, however, when the existing products are in standby, some devices inside the battery, such as an MCU, are always in a working state, and there is still a power consumption problem in standby, so that the power consumption is high in standby, and cannot be below 5 uA.
Disclosure of Invention
The present invention provides a low power consumption power-on circuit and a power supply apparatus awakened through a USB interface, aiming at the above-mentioned defects in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a low-power-consumption starting circuit awakened through a USB interface is constructed, and the circuit comprises: the USB interface comprises an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control circuit and a USB interface;
the plug end of the USB interface is used for connecting a load, the input end of the energy storage circuit and the input end of the first switch circuit are connected with an input voltage, the output end of the first switch circuit is connected with the input end of the voltage stabilizing circuit, the control end of the first switch circuit is connected with the control circuit, the output end of the voltage stabilizing circuit is connected, and the connecting end of the USB interface is connected with the first switch circuit;
When the plug end of the USB interface is connected with a load, the first switch circuit is conducted, the input voltage is transmitted to the voltage stabilizing circuit through the first switch circuit, the voltage stabilizing circuit processes the input voltage and outputs working voltage to the control circuit, and the control circuit wakes up to start according to the working voltage.
Preferably, the method further comprises the following steps: a DC-DC circuit connected to the first switching circuit;
the DC-DC circuit is used for processing the input voltage to output direct current voltage to the USB interface after the control circuit is started.
Preferably, the method further comprises the following steps: a second switching circuit provided between the DC-DC circuit and the control circuit;
and the second switch circuit receives a conduction signal output by the control circuit after the control circuit is started, and is conducted according to the conduction signal, and the DC-DC circuit outputs direct-current voltage to the USB interface through the second switch circuit.
Preferably, the tank circuit comprises: a fourth capacitor and a fifth capacitor;
a first end of the fourth capacitor is connected with the input voltage, a second end of the fourth capacitor is connected with a first end of the fifth capacitor, and a second end of the fifth capacitor is grounded;
The connection end of the second end of the fourth capacitor and the first end of the fifth capacitor is also connected to the first switch circuit.
Preferably, the first switching circuit includes: the resistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a third PMOS tube, a second resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor;
the source electrode of the first PMOS tube is connected with the input voltage, the drain electrode of the first PMOS tube is connected with the input end of the voltage stabilizing circuit, the grid electrode of the first PMOS tube is connected with the drain electrode of the second NPMOS tube through the fourth resistor, and the second resistor is connected between the source electrode and the grid electrode of the first PMOS tube;
the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected to the control circuit and the drain electrode of the third PMOS tube through the fifth resistor; the sixth resistor is connected between the grid electrode and the source electrode of the second NMOS tube; a source electrode of the third PMOS tube is connected with the second end of the fourth capacitor and the connecting end of the first end of the fifth capacitor, a grid electrode of the third PMOS tube is connected with the connecting end of the USB interface through a fourth diode, and the seventh resistor is connected between the grid electrode and the source electrode of the third PMOS tube;
The drain electrode of the first PMOS tube is the output end of the first switch circuit, and the grid electrode of the second NMOS tube is the control end of the first switch circuit.
Preferably, the voltage stabilizing circuit comprises: the circuit comprises a first resistor, a voltage stabilizing chip, a first capacitor, a second capacitor and a third capacitor;
the first end of the first resistor serves as the input end of the voltage stabilizing circuit and is connected with the drain electrode of the first PMOS tube, the second end of the first resistor is connected with the first end of the third capacitor and the second pin of the voltage stabilizing chip, the first pin of the voltage stabilizing chip and the second end of the third capacitor are grounded, the third pin of the voltage stabilizing chip is grounded through the first capacitor, the first end of the second capacitor is connected with the third pin of the voltage stabilizing chip, the second end of the second capacitor is grounded, and the third pin of the voltage stabilizing chip outputs the working voltage.
Preferably, the DC-DC circuit includes: the circuit comprises a conversion chip, a first inductor, a sixth capacitor, an eighth resistor, a twelfth resistor, a ninth resistor, a thirteenth resistor, a seventh capacitor and a third diode;
the first end of the sixth capacitor and the first end of the eighth resistor are connected with the output end of the first switch circuit, the second end of the sixth capacitor is grounded, the second end of the eighth resistor is grounded through the twelfth resistor, the second end of the eighth resistor is also connected with the enable end of the conversion chip, the power supply end of the conversion chip is connected with the output end of the first switch circuit, the conversion end of the conversion chip is connected with the first end of the first inductor, the second end of the first inductor is grounded through the ninth resistor and the thirteenth resistor in sequence, and the second end of the first inductor is also connected with the second switch circuit;
A first end of the seventh capacitor is connected with the second end of the first inductor, and a second end of the seventh capacitor is grounded; the connection end of the ninth resistor and the thirteenth resistor is connected to the feedback end of the conversion chip, the anode of the third diode is grounded, and the cathode of the third diode is connected to the conversion end of the conversion chip.
Preferably, the second switching circuit includes: a fourth PMOS tube, a fifth NMOS tube, a tenth resistor, an eleventh resistor, a fourteenth resistor and a fifteenth resistor;
the drain electrode of the fourth PMOS tube is connected with the second end of the first inductor, the source electrode of the fourth PMOS tube is connected to the connecting end of the USB interface, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube through the eleventh resistor, and the tenth resistor is connected between the grid electrode and the source electrode of the fourth PMOS tube;
the grid electrode of the fifth NMOS tube is connected to the control circuit through the fourteenth resistor, the source electrode of the fifth NMOS tube is grounded, and the fifteenth resistor is connected between the source electrode and the grid electrode of the fifth NMOS tube.
Preferably, the control circuit comprises a control chip;
the first pin of the control chip is connected with the grid electrode of the fifth NMOS tube through the fourteenth resistor, the second pin of the control chip is connected with the control end of the first switch circuit through a second diode, the third pin of the control chip is connected with the output end of the voltage stabilizing circuit, and the control end of the control chip is grounded.
The invention also provides a power supply device which comprises the low-power-consumption starting circuit awakened through the USB interface.
The low-power-consumption starting circuit awakened through the USB interface has the following beneficial effects: the method comprises the following steps: the USB interface comprises an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control circuit and a USB interface; the USB interface comprises an insertion end, an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control end, a voltage stabilizing circuit and a USB interface, wherein the insertion end of the USB interface is used for being connected with a load, the input end of the energy storage circuit and the input end of the first switch circuit are connected with an input voltage, the output end of the first switch circuit is connected with the input end of the voltage stabilizing circuit, the control end of the first switch circuit is connected with the control circuit, the output; when the plug end of the USB interface is connected with a load, the first switch circuit is switched on, the input voltage is transmitted to the voltage stabilizing circuit through the first switch circuit, the voltage stabilizing circuit processes the input voltage and outputs working voltage to the control circuit, and the control circuit wakes up to start according to the working voltage. When the USB interface is in standby, the internal circuit stops working completely, and the USB interface is started when the USB interface is connected to a load, so that the standby power consumption is low and can reach below 5 uA.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
Fig. 1 is a schematic block diagram of a low-power-consumption boot circuit awakened through a USB interface according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a low-power-consumption boot circuit awakened through a USB interface according to an embodiment of the present invention.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, the descriptions of up, down, left, right, front, rear, etc. used in the present invention are only relative to the positional relationship of the respective components of the present invention with respect to each other in the drawings. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
Referring to fig. 1, fig. 1 is a schematic block diagram of an alternative embodiment of the embodiments of the present invention.
As shown in fig. 1, the low power booting circuit awakened by the USB interface 16 may include: a tank circuit 11, a first switch circuit 12, a voltage regulator circuit 14, a control circuit 15 and a USB interface 16.
The plug end of the USB interface 16 is used for connecting a load, the input end of the energy storage circuit 11 and the input end of the first switch circuit 12 are connected with an input voltage, the output end of the first switch circuit 12 is connected with the input end of the voltage stabilizing circuit 14, the control end of the first switch circuit 12 is connected with the control circuit 15, the output end of the voltage stabilizing circuit 14 is connected, and the connecting end of the USB interface 16 is connected with the first switch circuit 12. When the plug end of the USB interface 16 is connected to a load, the first switch circuit 12 is turned on, the input voltage is transmitted to the voltage stabilizing circuit 14 through the first switch circuit 12, the voltage stabilizing circuit 14 processes the input voltage and outputs a working voltage to the control circuit 15, and the control circuit 15 wakes up to start according to the working voltage. In some embodiments, when the plug end of the USB interface 16 is not connected to a load, the energy storage circuit 11 is charged by the input voltage, the energy storage circuit 11 stores energy, at this time, the first switch circuit 12 is in an off state, and since the first switch circuit 12 is not turned on, the control circuit 15 and the voltage regulator circuit 14 are both in an off state, so that the standby current may be less than 5 uA.
In some embodiments, the tank circuit 11 may be implemented by a plurality of capacitors connected in series to divide the voltage. The first switching circuit 12 may be implemented by a MOS transistor or a triode. When the plug end of the USB interface 16 is not connected to a load, the capacitor performs serial voltage division on the input voltage due to the effect of the capacitor, and at this time, the first switch circuit 12 is not turned on, and due to the effect of the first switch circuit 12, the control circuit 15 and the voltage stabilizing circuit 14 do not have electricity and do not work, so that the standby power consumption is very low, and the standby current can reach below 5 uA.
In some embodiments, the input voltage may be provided by a battery or may be provided by an external power source.
Further, the voltage regulator circuit 14 is used for processing the input voltage when the first switch circuit 12 is turned on to obtain an operating voltage suitable for the operation of the control circuit 15.
In some embodiments, further comprising: and a DC-DC circuit 13 connected to the first switching circuit 12. The DC-DC circuit 13 is configured to process the input voltage to output a DC voltage to the USB interface 16 after the control circuit 15 is started.
Further, in some embodiments, the method further comprises: and a second switching circuit 17 provided between the DC-DC circuit 13 and the control circuit 15.
The second switch circuit 17 receives the on signal output by the control circuit 15 after the control circuit 15 is started, and is turned on according to the on signal, and the DC-DC circuit 13 outputs a DC voltage to the USB interface 16 through the second switch circuit 17. The second switching circuit 17 is controlled by the control circuit 15. Specifically, after the control circuit 15 is started, the control circuit 15 outputs a conducting signal to the second switch circuit 17, the second switch circuit 17 is conducted according to the conducting signal, and at this time, the DC voltage converted and output by the DC-DC circuit 13 is transmitted to the USB interface 16 through the second switch circuit 17 to supply power to the load. In some embodiments, the second switch circuit 17 may also function as an anti-reverse, i.e., prevent voltage from flowing back to the DC-DC circuit 13 after the USB interface 16 is connected to the load. In some embodiments, the second switch circuit 17 may be implemented by a MOS transistor or a triode.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of an alternative embodiment of the embodiments of the present invention.
As shown in fig. 2, R16 represents a load. It should be noted that R16 is merely an example, and does not limit the load type of the present invention, and the present invention is applicable to a capacitive load, a resistive load, and the like.
In some embodiments, the tank circuit 11 includes: a fourth capacitor C4 and a fifth capacitor C5.
A first terminal of the fourth capacitor C4 is connected to the input Voltage (VIN), a second terminal of the fourth capacitor C4 is connected to a first terminal of the fifth capacitor C5, and a second terminal of the fifth capacitor C5 is grounded.
The connection of the second terminal of the fourth capacitor C4 and the first terminal of the fifth capacitor C5 is also connected to the first switch circuit 12.
In some embodiments, the first switching circuit 12 includes: the circuit comprises a first PMOS tube Q1, a second NMOS tube Q2, a third PMOS tube Q3, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7.
The source electrode of the first PMOS tube Q1 is connected with an input voltage, the drain electrode of the first PMOS tube Q1 is connected with the input end of the voltage stabilizing circuit 14, the gate electrode of the first PMOS tube Q1 is connected with the drain electrode of the second NPMOS tube through a fourth resistor R4, and the second resistor R2 is connected between the source electrode and the gate electrode of the first PMOS tube Q1; the source electrode of the second NMOS transistor Q2 is grounded, and the gate electrode of the second NMOS transistor Q2 is connected to the control circuit 15 and the drain electrode of the third PMOS transistor Q3 through a fifth resistor R5; the sixth resistor R6 is connected between the gate and the source of the second NMOS transistor Q2; the source of the third PMOS transistor Q3 is connected to the connection end of the second end of the fourth capacitor C4 and the first end of the fifth capacitor C5, the gate of the third PMOS transistor Q3 is connected to the connection end of the USB interface 16 through a fourth diode, and the seventh resistor R7 is connected between the gate and the source of the third PMOS transistor Q3. The drain of the first PMOS transistor Q1 is the output terminal of the first switch circuit 12, and the gate of the second NMOS transistor Q2 is the control terminal of the first switch circuit 12.
In some embodiments, the stabilizing circuit 14 includes: the circuit comprises a first resistor, a voltage stabilizing chip U1, a first capacitor C1, a second capacitor C2 and a third capacitor C3.
The first end of the first resistor R1 is used as the input end of the voltage stabilizing circuit 14 and is connected with the drain of the first PMOS tube Q1, the second end of the first resistor R1 is connected with the first end of the third capacitor C3 and the second pin of the voltage stabilizing chip U1, the first pin of the voltage stabilizing chip U1 and the second end of the third capacitor C3 are grounded, the third pin of the voltage stabilizing chip U1 is grounded through the first capacitor C1, the first end of the second capacitor C2 is connected with the third pin of the voltage stabilizing chip U1, the second end of the second capacitor C2 is grounded, and the third pin of the voltage stabilizing chip U1 outputs the working Voltage (VCC).
In some embodiments, the DC-DC circuit 13 includes: the circuit comprises a conversion chip U3, a first inductor L1, a sixth capacitor C6, an eighth resistor R8, a twelfth resistor R12, a ninth resistor R9, a thirteenth resistor R13, a seventh capacitor C7 and a third diode D3.
The first end of the sixth capacitor C6 and the first end of the eighth resistor R8 are connected to the output end of the first switch circuit 12, the second end of the sixth capacitor C6 is grounded, the second end of the eighth resistor R8 is grounded through the twelfth resistor R12, the second end of the eighth resistor R8 is further connected to the enable end of the conversion chip U3, the power supply end of the conversion chip U3 is connected to the output end of the first switch circuit 12, the conversion end of the conversion chip U3 is connected to the first end of the first inductor L1, the second end of the first inductor L1 is grounded through the ninth resistor R9 and the thirteenth resistor R13 in sequence, and the second end of the first inductor L1 is further connected to the second switch circuit 17.
A first end of the seventh capacitor C7 is connected to the second end of the first inductor L1, and a second end of the seventh capacitor C7 is grounded; the connection end of the ninth resistor R9 and the thirteenth resistor R13 is connected to the feedback end of the conversion chip U3, the anode of the third diode D3 is grounded, and the cathode of the third diode D3 is connected to the conversion end of the conversion chip U3.
In some embodiments, the second switching circuit 17 includes: a fourth PMOS transistor Q4, a fifth NMOS transistor Q5, a tenth resistor R10, an eleventh resistor R11, a fourteenth resistor R14 and a fifteenth resistor R15.
The drain of the fourth PMOS transistor Q4 is connected to the second end of the first inductor L1, the source of the fourth PMOS transistor Q4 is connected to the connection end of the USB interface 16, the gate of the fourth PMOS transistor Q4 is connected to the drain of the fifth NMOS transistor Q5 through an eleventh resistor R11, and the tenth resistor R10 is connected between the gate and the source of the fourth PMOS transistor Q4; the gate of the fifth NMOS transistor Q5 is connected to the control circuit 15 through a fourteenth resistor R14, the source of the fifth NMOS transistor Q5 is grounded, and the fifteenth resistor R15 is connected between the source and the gate of the fifth NMOS transistor Q5.
In some embodiments, control circuit 15 includes a control chip U2.
A first pin of the control chip U2 is connected to a gate of the fifth NMOS transistor Q5 through a fourteenth resistor R14, a second pin of the control chip U2 is connected to the control terminal of the first switch circuit 12 through a second diode D2, a third pin of the control chip U2 is connected to the output terminal of the voltage regulator circuit 14, and the control terminal of the control chip U2 is grounded.
Further, in some embodiments, the method further comprises: a third resistor R3 and a first diode D1, wherein a second terminal of the third resistor R3 is connected to the output terminal of the voltage stabilizing circuit 14, a second terminal of the third resistor R3 is connected to the anode of the first diode D1, and a cathode of the first diode D1 is connected to a first terminal of the fifth capacitor C5.
As shown in fig. 2, during standby, the fourth capacitor C4 and the fifth capacitor C5 divide the input voltage VIN in series, at this time, since no USB interface is connected to a load, the gate of the third PMOS transistor in the first switch circuit 12 is at a high level, the third PMOS transistor is turned off, at this time, the first PMOS transistor and the second NMOS transistor are in an off state, and at this time, the conversion chip U3, the voltage regulation chip U1, and the control chip U2 all have no voltage and are in an off state, so that the standby current of the circuit is less than 5 uA.
When the USB interface is connected to a load, the gate voltage of the third PMOS transistor Q3 is pulled low, the third PMOS transistor Q3 is turned on, so as to provide a start voltage for the gate of the second NMOS transistor Q2, the second NMOS transistor Q2 is turned on, the gate voltage of the first PMOS transistor Q1 is pulled low after the second NMOS transistor Q2 is turned on, the first PMOS transistor Q1 is turned on to supply power to the subsequent circuit, the voltage regulation chip U1 outputs a working voltage VCC to the control chip U2, the control chip U2 is powered on to work, and immediately outputs a high level through the first pin and the second pin thereof, so that the second NMOS transistor Q2 and the fifth NMOS transistor Q5 are turned on, after the USB interface is connected to the load, the electric energy of the fifth capacitor C5 is consumed, and at this time, the VCC charges the fifth capacitor C5 through the third resistor R3 and the first diode D1, so as to ensure that the USB can normally work when the USB is plugged for the second time.
Further, after the system operates, VCC charges the fifth capacitor C5 through the third resistor R3 and the first diode D1, and the second diode D2 prevents the voltage of the fifth capacitor C5 from flowing backward to the control chip U2, thereby reducing the voltage consumption of the fifth capacitor C5.
Further, in some embodiments, the DC-DC circuit may be a boost circuit or a buck circuit, which is determined by the actual design requirement of the circuit.
Furthermore, the invention also provides a power supply device, which comprises the low-power-consumption startup circuit awakened through the USB interface disclosed by the embodiment of the invention. Optionally, the power supply device may include a battery product, or may be a power supply system. By setting the low-power-consumption startup circuit awakened through the USB interface, the internal circuit can be completely stopped working when in standby, and the startup circuit is started when the USB interface is connected to a load, so that the standby power consumption is low and can reach below 5 uA.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (10)
1. A low power consumption boot circuit that wakes up through a USB interface, comprising: the USB interface comprises an energy storage circuit, a first switch circuit, a voltage stabilizing circuit, a control circuit and a USB interface;
the plug end of the USB interface is used for connecting a load, the input end of the energy storage circuit and the input end of the first switch circuit are connected with an input voltage, the output end of the first switch circuit is connected with the input end of the voltage stabilizing circuit, the control end of the first switch circuit is connected with the control circuit, the output end of the voltage stabilizing circuit is connected, and the connecting end of the USB interface is connected with the first switch circuit;
when the plug end of the USB interface is connected with a load, the first switch circuit is conducted, the input voltage is transmitted to the voltage stabilizing circuit through the first switch circuit, the voltage stabilizing circuit processes the input voltage and outputs working voltage to the control circuit, and the control circuit wakes up to start according to the working voltage.
2. The low power consumption boot circuit that wakes up via a USB interface of claim 1, further comprising: a DC-DC circuit connected to the first switching circuit;
the DC-DC circuit is used for processing the input voltage to output direct current voltage to the USB interface after the control circuit is started.
3. The low power consumption boot circuit that wakes up via a USB interface of claim 2, further comprising: a second switching circuit provided between the DC-DC circuit and the control circuit;
and the second switch circuit receives a conduction signal output by the control circuit after the control circuit is started, and is conducted according to the conduction signal, and the DC-DC circuit outputs direct-current voltage to the USB interface through the second switch circuit.
4. A low power consumption power-on circuit to wake up through a USB interface as claimed in claim 1, wherein the energy storage circuit comprises: a fourth capacitor and a fifth capacitor;
a first end of the fourth capacitor is connected with the input voltage, a second end of the fourth capacitor is connected with a first end of the fifth capacitor, and a second end of the fifth capacitor is grounded;
the connection end of the second end of the fourth capacitor and the first end of the fifth capacitor is also connected to the first switch circuit.
5. The low power consumption power-on circuit woken up through the USB interface of claim 4, wherein the first switch circuit comprises: the resistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a third PMOS tube, a second resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor;
The source electrode of the first PMOS tube is connected with the input voltage, the drain electrode of the first PMOS tube is connected with the input end of the voltage stabilizing circuit, the grid electrode of the first PMOS tube is connected with the drain electrode of the second NPMOS tube through the fourth resistor, and the second resistor is connected between the source electrode and the grid electrode of the first PMOS tube;
the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected to the control circuit and the drain electrode of the third PMOS tube through the fifth resistor; the sixth resistor is connected between the grid electrode and the source electrode of the second NMOS tube; a source electrode of the third PMOS tube is connected with the second end of the fourth capacitor and the connecting end of the first end of the fifth capacitor, a grid electrode of the third PMOS tube is connected with the connecting end of the USB interface through a fourth diode, and the seventh resistor is connected between the grid electrode and the source electrode of the third PMOS tube;
the drain electrode of the first PMOS tube is the output end of the first switch circuit, and the grid electrode of the second NMOS tube is the control end of the first switch circuit.
6. The low power consumption power-on circuit awakened through the USB interface of claim 5, wherein the voltage stabilizing circuit comprises: the circuit comprises a first resistor, a voltage stabilizing chip, a first capacitor, a second capacitor and a third capacitor;
The first end of the first resistor serves as the input end of the voltage stabilizing circuit and is connected with the drain electrode of the first PMOS tube, the second end of the first resistor is connected with the first end of the third capacitor and the second pin of the voltage stabilizing chip, the first pin of the voltage stabilizing chip and the second end of the third capacitor are grounded, the third pin of the voltage stabilizing chip is grounded through the first capacitor, the first end of the second capacitor is connected with the third pin of the voltage stabilizing chip, the second end of the second capacitor is grounded, and the third pin of the voltage stabilizing chip outputs the working voltage.
7. A low power consumption power-on circuit to wake up over a USB interface as claimed in claim 3, wherein the DC-DC circuit comprises: the circuit comprises a conversion chip, a first inductor, a sixth capacitor, an eighth resistor, a twelfth resistor, a ninth resistor, a thirteenth resistor, a seventh capacitor and a third diode;
the first end of the sixth capacitor and the first end of the eighth resistor are connected with the output end of the first switch circuit, the second end of the sixth capacitor is grounded, the second end of the eighth resistor is grounded through the twelfth resistor, the second end of the eighth resistor is also connected with the enable end of the conversion chip, the power supply end of the conversion chip is connected with the output end of the first switch circuit, the conversion end of the conversion chip is connected with the first end of the first inductor, the second end of the first inductor is grounded through the ninth resistor and the thirteenth resistor in sequence, and the second end of the first inductor is also connected with the second switch circuit;
A first end of the seventh capacitor is connected with the second end of the first inductor, and a second end of the seventh capacitor is grounded; the connection end of the ninth resistor and the thirteenth resistor is connected to the feedback end of the conversion chip, the anode of the third diode is grounded, and the cathode of the third diode is connected to the conversion end of the conversion chip.
8. A low power consumption power-on circuit woken up through a USB interface as claimed in claim 7, wherein the second switching circuit comprises: a fourth PMOS tube, a fifth NMOS tube, a tenth resistor, an eleventh resistor, a fourteenth resistor and a fifteenth resistor;
the drain electrode of the fourth PMOS tube is connected with the second end of the first inductor, the source electrode of the fourth PMOS tube is connected to the connecting end of the USB interface, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube through the eleventh resistor, and the tenth resistor is connected between the grid electrode and the source electrode of the fourth PMOS tube;
the grid electrode of the fifth NMOS tube is connected to the control circuit through the fourteenth resistor, the source electrode of the fifth NMOS tube is grounded, and the fifteenth resistor is connected between the source electrode and the grid electrode of the fifth NMOS tube.
9. The low power consumption power-on circuit woken up through the USB interface of claim 8, wherein the control circuit comprises a control chip;
the first pin of the control chip is connected with the grid electrode of the fifth NMOS tube through the fourteenth resistor, the second pin of the control chip is connected with the control end of the first switch circuit through a second diode, the third pin of the control chip is connected with the output end of the voltage stabilizing circuit, and the control end of the control chip is grounded.
10. A power supply device comprising the low power boot circuit awakened through the USB interface according to any one of claims 1 to 9.
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| CN202010641174.1A CN111864833A (en) | 2020-07-06 | 2020-07-06 | Low-power-consumption starting circuit awakened through USB interface and power supply device |
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| CN202010641174.1A CN111864833A (en) | 2020-07-06 | 2020-07-06 | Low-power-consumption starting circuit awakened through USB interface and power supply device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582999A (en) * | 2020-11-16 | 2021-03-30 | 惠州市德赛西威汽车电子股份有限公司 | Protection circuit for preventing chip pin overvoltage in standby process and after starting |
| CN113064364A (en) * | 2021-02-27 | 2021-07-02 | 徐州可云智能科技有限公司 | High-reliability low-power-consumption timed dormancy awakening device |
| CN113359542A (en) * | 2021-05-21 | 2021-09-07 | 深圳拓邦股份有限公司 | Low-power consumption control circuit and electrical apparatus |
| CN117148908A (en) * | 2023-10-25 | 2023-12-01 | 绿进新能源科技(常熟)有限公司 | BMS-based high-low side charging awakening and complete machine low-power-consumption circuit |
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2020
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582999A (en) * | 2020-11-16 | 2021-03-30 | 惠州市德赛西威汽车电子股份有限公司 | Protection circuit for preventing chip pin overvoltage in standby process and after starting |
| CN112582999B (en) * | 2020-11-16 | 2023-02-14 | 惠州市德赛西威汽车电子股份有限公司 | Protection circuit for preventing chip pin overvoltage in standby process and after starting |
| CN113064364A (en) * | 2021-02-27 | 2021-07-02 | 徐州可云智能科技有限公司 | High-reliability low-power-consumption timed dormancy awakening device |
| CN113359542A (en) * | 2021-05-21 | 2021-09-07 | 深圳拓邦股份有限公司 | Low-power consumption control circuit and electrical apparatus |
| CN113359542B (en) * | 2021-05-21 | 2024-02-09 | 深圳拓邦股份有限公司 | Low-power consumption control circuit and electric appliance |
| CN117148908A (en) * | 2023-10-25 | 2023-12-01 | 绿进新能源科技(常熟)有限公司 | BMS-based high-low side charging awakening and complete machine low-power-consumption circuit |
| CN117148908B (en) * | 2023-10-25 | 2024-01-26 | 绿进新能源科技(常熟)有限公司 | BMS-based high-low side charging awakening and complete machine low-power-consumption circuit |
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