CN111864065A - Pillar type deep trench capacitor and preparation method thereof - Google Patents

Abstract

The invention discloses a deep trench capacitor for improving capacitance based on a silicon substrate pillar structure and a preparation method thereof, and relates to the technical field of semiconductors. According to the invention, a plurality of pillar-type structures are formed on the existing silicon-based substrate, deep grooves are formed between the outer surfaces of the pillar-type structures and between the outer surface of the pillar-type structure and the side wall of the substrate, so that the surface area of the capacitor is greatly increased, and the capacitance is greatly improved.

Description

Pillar type deep trench capacitor and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a pillar type deep trench capacitor and a preparation method thereof.

Background

With the continuous reduction of the size and the continuous improvement of the integration of semiconductor devices, the performance of capacitors is also required to be improved, i.e., the charge storage capacity of the capacitors is required to be increased under the condition that the volumes of the capacitors are not changed or reduced. The charge storage capacity can be increased by increasing the surface area of the capacitor or by using a higher dielectric constant material as the dielectric.

In the prior art, the capacitance of a semiconductor device is increased by changing the structure of a capacitor to increase the capacitive energy by adopting the inner surface of a groove-shaped or round hole deep groove as an electrode. Although the deep trench structure increases the surface area of the capacitor to a certain extent, thereby enlarging the capacitance, the requirements of the existing semiconductor device on the size and the performance cannot be met.

Disclosure of Invention

The invention aims to provide a pillar type deep trench capacitor and a preparation method thereof, which can greatly increase the surface area of the capacitor, thereby improving the capacitance and being effectively compatible with the preparation process of the existing capacitor.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

the invention provides a pillar type deep trench capacitor, which is characterized in that a plurality of pillar structures are formed in the central region of a capacitor substrate structure, and deep trenches are formed among the pillar structures and between the pillar structures and the side wall of the substrate. And a bottom electrode layer, a dielectric layer and a top electrode layer are sequentially arranged on the surface of the deep groove of the capacitor and the upper surface of the pillar structure.

Further, the cross section of the capacitor substrate pillar structure is sequentially increased from top to bottom.

Further, the capacitor substrate sidewall is connected to a portion of the pillar structure.

Furthermore, the bottom electrode layer of the capacitor is a doped conductive layer, and the top electrode layer is a polysilicon layer.

Furthermore, the capacitor is also provided with a silicification layer, an isolation layer and an insulation layer.

Further, the insulating layer comprises at least one material selected from TEOS, BPSG and PSG.

Furthermore, the insulating layer is provided with a plurality of contact through holes filled with a conductive material, and the conductive material is preferably tungsten.

Further, the silicification layer comprises a first silicification layer located above the support column structure and a second silicification layer located on the periphery side of the substrate, and the first silicification layer and the second silicification layer are insulated through an isolation layer.

Further, the isolation layer is nitride.

In another aspect, a method for fabricating a pillar-type deep trench capacitor substrate structure is provided, which includes the following steps:

arranging an auxiliary layer, sequentially arranging a hard mask layer, an anti-reflection layer and a photoresist layer on a silicon substrate from bottom to top, and forming a first groove for etching the deep groove on the photoresist layer;

etching for the first time, and forming a second groove communicated with the first groove on the anti-reflection layer and the hard mask layer;

and etching for the second time to remove the photoresist layer and the anti-reflection layer, and etching the silicon substrate by taking a second groove formed by the hard mask layer as a template to form a pillar-type deep trench substrate structure.

In another aspect, a method for fabricating a pillar-type deep trench capacitor is provided, which includes the following steps:

s1, sequentially forming a hard mask layer, an anti-reflection layer and a photoresist layer on the silicon-based substrate;

s2, forming a plurality of first grooves on the photoresist layer to expose the anti-reflection layer, forming second grooves on the anti-reflection layer and the hard mask layer through photoetching or other processes, and exposing the silicon-based substrate through the second grooves;

s3, removing the photoresist layer and the anti-reflection layer, reserving the hard mask layer, and forming a pillar-type deep trench on the silicon-based substrate through etching or other processes;

and S4, depositing a doped conducting layer, a dielectric layer and a polysilicon layer on the surface of the deep groove and the upper surface of the pillar structure in sequence. The polysilicon layer is used as a top electrode and is filled in the pillar-type deep groove; doping the conductive layer as a bottom electrode;

s5, depositing a silicon nitride layer on the surface of the polycrystalline silicon layer and the substrate to form a covered isolation layer;

s6, removing the isolation layer on the upper surface of the polycrystalline silicon to expose the upper surface of the polycrystalline silicon bare layer and reserving the isolation layer on the side edge of the polycrystalline silicon;

s7, removing the isolation layer and the dielectric layer on the surface of the substrate to expose the bottom electrode layer;

s8, carrying out silicification treatment on the exposed polysilicon layer and the bottom electrode layer to form a silicification layer;

s9, depositing an insulating layer on the surface of the silicide layer, wherein the insulating layer at least comprises one of the following materials: TEOS, BPSG, PSG;

and S10, forming a plurality of contact through holes in the insulating layer, wherein the contact through holes are positioned above the polycrystalline silicon layer and the bottom electrode layer.

And S11, filling a conductive material such as metal in the contact through hole, and carrying out chemical mechanical polishing on the metal layer to obtain the deep trench capacitor with the capacitance improved based on the silicon substrate pillar structure.

Compared with the prior art, the technical scheme provided by the invention has the following advantages and beneficial effects:

a plurality of pillar type structures are formed on the existing silicon substrate, deep grooves are formed between the outer surfaces of the pillar structures and the side walls of the substrate, bottom electrodes, dielectrics, top electrodes and the like are laid on the surfaces of the deep grooves to form capacitors, and the capacitance of the capacitors is greatly increased by increasing the surface area of the capacitors.

Drawings

FIG. 1 is a schematic diagram of a pillar-type deep trench capacitor substrate structure;

FIG. 2 is a schematic structural diagram of a pillar-type deep trench capacitor substrate structure with a sidewall structure removed;

FIG. 3 is a schematic cross-sectional structure of a silicon-based substrate;

FIG. 4 is a schematic structural diagram of FIG. 3 after sequentially disposing a hard mask layer, an anti-reflection layer and a photoresist layer;

FIG. 5 is a schematic structural diagram of forming a deep trench mask pattern on a reticle;

FIG. 6 is a schematic structural diagram illustrating the pillar-type deep trench substrate structure formed by etching the substrate of FIG. 5;

FIG. 7 is a schematic structural diagram of the structure of FIG. 6 after sequentially depositing a bottom electrode, a dielectric layer and a polysilicon layer;

FIG. 8 is a schematic diagram of the structure of FIG. 7 after deposition of an isolation layer on the polysilicon layer and the substrate surface

FIG. 9 is a schematic structural diagram of FIG. 8 after the isolation layer on the polysilicon layer surface, the dielectric layer on the substrate surface and the isolation layer are removed;

FIG. 10 is a schematic diagram of the exposed top and bottom electrodes of FIG. 9 after silicidation;

FIG. 11 is a schematic illustration of the structure of FIG. 10 after deposition of an insulating layer and application of a photoresist layer over the silicide layer;

FIG. 12 is a schematic view of the structure of FIG. 11 after forming a contact via in the insulating layer by photolithography and removing the photoresist layer;

FIG. 13 is a schematic diagram of the contact via of FIG. 12 after being filled with a conductive material;

FIG. 14 is a schematic view of the structure of FIG. 13 after chemical mechanical processing.

Reference numerals: 1-a pillar structure; 2-deep groove; 3-a post structure connected to the substrate sidewall; 4-a hard mask layer; 5-an anti-reflection layer; 51-a second groove; 6-photoresist layer; 61-a first groove; 11-a silicon-based substrate; 12-a bottom electrode layer; 13-a dielectric layer; 14-a top electrode layer; 151-first silicide layer; 152-a second silicide layer; 16-an insulating layer; 17-contact vias; 18-an isolation layer; 19-metal layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of the present invention and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Examples

As shown in fig. 1 and fig. 2, the present embodiment provides a pillar-type deep trench capacitor, in which a plurality of pillar structures 1 are formed in a central region of a substrate structure of the capacitor, and deep trenches 2 are formed between the pillar structures 1 and sidewalls of the substrate.

The substrate structure of the pillar-type deep trench employed in this embodiment increases the capacitance of the deep trench capacitor by increasing the surface area of the capacitor. Compared with the traditional groove-shaped or round-hole-shaped deep trench capacitor, under the condition of adopting the same silicon substrate structure, the substrate structure of the pillar-shaped deep trench has the capacitance increased by 40-50% compared with the capacitance of the groove-shaped or round-hole-shaped substrate structure. Specific examples are as follows:

assuming a deep trench 2 substrate structure with a 5 × 3 surface area, the effective area is 5+3+5+3= 16; if the substrate structure is a substrate structure with a groove-shaped or round hole-shaped structure, the effective area is 8 pi = 25.12; if the substrate structure is a pillar type substrate structure, the effective area is 16+7 pi = 37.98; the increase value of the effective area is (37.98-25.12)/25.12 multiplied by 100% = 51.2%.

In one embodiment, the cross-section of the strut structure 1 increases from top to bottom.

In one embodiment, the substrate side wall is provided with the pillar structure 3 connected with the substrate side wall, and the pillar structure 3 connected with the substrate side wall can effectively enhance the mechanical strength of the capacitor and also can effectively prevent the capacitor from overloading.

In one embodiment, the bottom electrode layer 12 is a doped conductive layer and the top electrode layer 14 is a polysilicon layer.

In one embodiment, the insulating layer 16 comprises at least one of TEOS, BPSG, and PSG.

In one embodiment, the silicide layer includes a first silicide layer 151 located above the pillar structure 1 and a second silicide layer 152 located on the periphery side of the silicon-based substrate 11, and the isolation layer 18 is disposed between the first silicide layer 151 and the second silicide layer 152.

In one embodiment, the spacer layer 18 is a nitride.

On the other hand, referring to fig. 3 to 14, the present embodiment further provides a method for manufacturing a deep trench capacitor with improved capacitance based on a silicon substrate pillar structure, comprising the following steps:

s1, sequentially forming a hard mask layer 4, an anti-reflection layer 5 and a photoresist layer 6 on the silicon-based substrate 11;

s2, forming a plurality of first grooves 61 on the photoresist layer 6 to expose the anti-reflection layer 5, forming second grooves 51 on the anti-reflection layer 5 and the hard mask layer 4 by photolithography or other processes, wherein the second grooves 51 expose the silicon-based substrate 11;

s3, removing the photoresist layer 6 and the antireflection layer 5, reserving the hard mask layer 4, and forming the deep trench 2 on the silicon-based substrate 11 through etching or other processes to obtain a substrate structure for the pillar-type deep trench capacitor;

and S4, depositing a doped conducting layer (bottom electrode layer 12), a dielectric layer 13 and a polysilicon layer (top electrode layer 14) on the surface of the deep trench 2 and the upper surface of the pillar structure 3 connected with the side wall of the substrate in sequence. The polysilicon layer is used as a top electrode and is filled in the pillar-type deep groove; doping the conductive layer as a bottom electrode;

s5, depositing a silicon nitride layer on the surfaces of the polysilicon layer and the silicon-based substrate 11 to form a covered isolation layer 18;

s6, removing the isolation layer 18 on the surface of the polycrystalline silicon layer to expose the upper surface of the bare polycrystalline silicon layer and reserving the isolation layer 18 on the side edge of the polycrystalline silicon;

s7, removing the isolation layer 18 and the dielectric layer 13 on the surface of the substrate to expose the bottom electrode layer 12;

s8, carrying out silicification treatment on the exposed surface of the polycrystalline silicon layer and the surface of the bottom electrode layer to form a silicification layer 15;

s9, depositing an insulating layer 16 on the surface of the silicide layer 15, wherein the insulating layer 16 comprises at least one of the following materials: TEOS, BPSG or PSG;

s10, forming a plurality of contact through holes 17 in the insulating layer 16, and the contact through holes are positioned above the polycrystalline silicon layer and the bottom electrode layer 12;

s11, filling a conductive material (tungsten) in the contact through hole 17 to form a metal layer 19, carrying out chemical mechanical polishing on the metal layer 19, and removing the redundant metal layer 19 to obtain the deep trench capacitor.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (11)

1. A pillar type deep trench capacitor is characterized in that a plurality of pillar structures are formed in the central region of a capacitor substrate structure, deep trenches are formed among the pillar structures and between the pillar structures and the side wall of the substrate, and a bottom electrode layer, a dielectric layer and a top electrode layer are sequentially arranged on the surface of the capacitor deep trench and the upper surface of the pillar structures.

2. The pillar-type deep trench capacitor of claim 1 wherein the cross-section of the capacitor substrate pillar structure increases sequentially from top to bottom.

3. The pillar type deep trench capacitor of claim 1 wherein the substrate sidewall is connected to a portion of the pillar structure.

4. The pillar-type deep trench capacitor of claim 1, wherein said bottom electrode layer is a doped conductive layer and said top electrode layer is a polysilicon layer.

5. The pillar-type deep trench capacitor of claim 1, further comprising a silicide layer, an isolation layer, and an insulation layer.

6. The pillar-type deep trench capacitor of claim 5, wherein the insulating layer comprises at least one of TEOS, BPSG, and PSG.

7. The pillar-type deep trench capacitor of claim 6, wherein the insulating layer defines a plurality of contact vias filled with a conductive material, the conductive material being tungsten.

8. The deep trench capacitor of claim 5, wherein the silicide layers comprise a first silicide layer over the pillar and deep trench structures and a second silicide layer on a periphery side of the substrate, the first silicide layer and the second silicide layer being insulated from each other by an isolation layer.

9. The deep trench capacitor of claim 8, wherein the isolation layer is a nitride.

10. A method for preparing a pillar type deep trench capacitor substrate structure is characterized by comprising the following steps:

arranging an auxiliary layer, sequentially arranging a hard mask layer, an anti-reflection layer and a photoresist layer on a silicon substrate from bottom to top, and forming a first groove for etching the deep groove on the photoresist layer;

etching for the first time, and forming a second groove communicated with the groove on the anti-reflection layer and the hard mask layer;

and etching for the second time to remove the photoresist layer and the anti-reflection layer, and etching the silicon substrate by taking a second groove formed by the hard mask layer as a template to form a pillar-type deep trench substrate structure.

11. The method of manufacturing the pillar-type deep trench capacitor of claim 1, comprising the steps of:

s1, sequentially forming a hard mask layer, an anti-reflection layer and a photoresist layer on the silicon-based substrate;

s2, forming a plurality of first grooves on the photoresist layer to expose the anti-reflection layer, forming second grooves on the anti-reflection layer and the hard mask layer through photoetching or other processes, wherein the second grooves expose the silicon-based substrate;

s3, removing the photoresist layer and the anti-reflection layer, reserving the hard mask layer, and forming a pillar-type deep trench on the silicon-based substrate through etching or other processes;

s4, depositing a doped conducting layer, a dielectric layer and a polysilicon layer on the surface of the deep groove and the upper surface of the pillar structure in sequence; the polysilicon layer is used as a top electrode and is filled in the pillar-type deep groove; doping the conductive layer as a bottom electrode;

s5, depositing a silicon nitride layer on the surface of the polycrystalline silicon layer and the substrate to form a covered isolation layer;

s6, removing the isolation layer on the upper surface of the polycrystalline silicon to expose the upper surface of the polycrystalline silicon bare layer and reserving the isolation layer on the side edge of the polycrystalline silicon;

s7, removing the isolation layer and the dielectric layer on the surface of the substrate to expose the bottom electrode layer;

s8, carrying out silicification treatment on the exposed polysilicon layer and the bottom electrode layer to form a silicification layer;

s9, depositing an insulating layer on the surface of the silicified layer, wherein the insulating layer is composed of at least one of the following materials: TEOS, BPSG, PSG;

s10, forming a plurality of contact through holes in the insulating layer, wherein the contact through holes are positioned above the polycrystalline silicon layer and the bottom electrode layer;

and S11, filling a conductive material such as metal in the contact through hole, and carrying out chemical mechanical polishing on the metal layer to obtain the deep trench capacitor with the capacitance improved based on the silicon substrate pillar structure.

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