CN111863827A - Memory structure and manufacturing method thereof - Google Patents

Memory structure and manufacturing method thereof Download PDF

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Publication number
CN111863827A
CN111863827A CN201910338092.7A CN201910338092A CN111863827A CN 111863827 A CN111863827 A CN 111863827A CN 201910338092 A CN201910338092 A CN 201910338092A CN 111863827 A CN111863827 A CN 111863827A
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China
Prior art keywords
memory structure
igzo
thin metal
insulating layer
layer
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CN201910338092.7A
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Chinese (zh)
Inventor
冉晓雯
蔡娟娟
林敬富
李宗玹
陈蔚宗
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Yuan Tai Technology Industry Co ltd
E Ink Holdings Inc
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Yuan Tai Technology Industry Co ltd
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Priority to CN201910338092.7A priority Critical patent/CN111863827A/en
Publication of CN111863827A publication Critical patent/CN111863827A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

The invention discloses a memory structure and a manufacturing method thereof. The grid is positioned on the substrate. The first insulating layer is positioned on the grid electrode. The thin metal layer is located on the first insulating layer and has a plurality of metal particles. The IGZO particles are located on the metal particles. The second insulating layer is located on the IGZO pellets. The IGZO channel layer is located on the second insulating layer. The source/drain electrodes are positioned on the IGZO channel layer. The IGZO particles can be used as a medium for storing carriers (electrons) entering from a tunneling effect, so that the lateral electric leakage of the memory structure can be reduced, the memory structure can be ensured to normally operate for a long time, and the omission of data is avoided.

Description

Memory structure and manufacturing method thereof
Technical Field
The invention relates to a memory structure and a manufacturing method thereof.
Background
Nowadays, electronic products such as mobile phones, notebook computers, tablet computers, portable disks, digital cameras and the like are indispensable in life. Among them, the memory in the electronic product plays a very important role. The memory can be divided into Volatile (vollatile) memory and Non-Volatile (Non-vollatile) memory.
Volatile memory means that the data stored in the memory disappears with the removal of external power, such as static random access memory (sram) and dynamic random access memory (dram). Non-volatile memory means that the stored data in the memory will not disappear with the removal of the external power supply, and can be stored for a long time, such as rom, prom, eprom, eeprom, and flash memory.
In order to store information of carriers for a long time, reducing Lateral leakage (Lateral leakage) of a device is an important issue in a non-volatile memory, so that the device can be ensured to operate normally for a long time and information leakage is avoided.
Disclosure of Invention
An objective of the present invention is to provide a memory structure, which can reduce the lateral leakage of the memory structure, ensure the long-term normal operation of the memory structure, and avoid the data omission.
According to an embodiment of the present invention, a memory structure includes a substrate, a gate electrode, a first insulating layer, a thin metal layer, a plurality of Indium Gallium Zinc Oxide (IGZO) particles, a second insulating layer, an IGZO channel layer, and source/drain electrodes. The grid is positioned on the substrate. The first insulating layer is positioned on the grid electrode. The thin metal layer is located on the first insulating layer and has a plurality of metal particles. The IGZO particles are located on the metal particles. The second insulating layer is located on the IGZO pellets. The IGZO channel layer is located on the second insulating layer. The source/drain electrodes are positioned on the IGZO channel layer.
In an embodiment of the present invention, the thickness of the thin metal layer is in a range of 1nm to 20 nm.
In an embodiment of the present invention, the thickness of each of the IGZO particles described above is in a range of 2nm to 20 nm.
In an embodiment of the present invention, the material of the thin metal layer includes silver.
In one embodiment of the present invention, the IGZO particles are in contact with a thin metal layer.
In one embodiment of the present invention, the thin metal layer contacts the first insulating layer.
In an embodiment of the present invention, the IGZO grains are located between the thin metal layer and the second insulating layer.
Another objective of the present invention is to provide a method for manufacturing a memory structure.
According to one embodiment of the present invention, a method of fabricating a memory structure includes forming a thin metal layer on a first insulating layer on a gate electrode; subjecting the thin metal layer to a thermal annealing process to make the thin metal layer have a plurality of metal particles; forming an Indium Gallium Zinc Oxide (IGZO) material on the metal particles, such that the IGZO material forms a plurality of IGZO particles; forming a second insulating layer on the IGZO pellets; forming an IGZO channel layer on the second insulating layer; and forming a source/drain electrode on the IGZO channel layer.
In an embodiment of the present invention, the forming of the thin metal layer on the first insulating layer is performed by thermal evaporation.
In an embodiment of the present invention, the temperature of the thermal annealing treatment applied to the thin metal layer is in a range of 50 ℃ to 300 ℃.
In an embodiment of the present invention, the forming of the IGZO material on the metal particles is performed by sputtering.
In an embodiment of the present invention, the thickness of the thin metal layer is in a range of 1nm to 20 nm.
In an embodiment of the present invention, the thickness of each of the IGZO particles described above is in a range of 2nm to 20 nm.
In an embodiment of the present invention, the material of the thin metal layer includes silver.
In the above embodiments of the present invention, since the memory structure has the thin metal layer on the first insulating layer, and the thin metal layer has the metal grains, when the Indium Gallium Zinc Oxide (IGZO) material is formed on the metal grains, the IGZO material may form the IGZO grains. The IGZO particles can be used as a medium for storing carriers (electrons) entering from the tunneling effect, so that the Lateral leakage (lareral leakage) of the memory structure can be reduced, the memory structure can be ensured to operate normally for a long time, and information omission is avoided.
Drawings
FIG. 1 is a cross-sectional view of a memory structure according to an embodiment of the invention.
FIG. 2 is a flow chart of a method of fabricating the memory structure of FIG. 1.
FIG. 3 is a schematic current diagram of the memory structure of FIG. 1.
FIG. 4 is a diagram illustrating the movement of electrons during a write operation performed by the memory structure of FIG. 1.
FIG. 5 is a schematic diagram of electron movement during erasing of the memory structure of FIG. 1.
FIG. 6 is a graph of current-gate voltage relationship for the memory structure of FIG. 1.
Detailed Description
In the following description, numerous implementation details are set forth in order to provide a thorough understanding of various embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.
FIG. 1 shows a cross-sectional view of a memory structure 100 according to an embodiment of the invention. As shown, the memory structure 100 includes a substrate 110, a gate electrode 120, a first insulating layer 130, a thin metal layer 140, a plurality of Indium Gallium Zinc Oxide (IGZO) particles 150, a second insulating layer 160, an IGZO channel layer 170, and source/drain electrodes 180. Wherein the gate electrode 120 is located on the substrate 110. The first insulating layer 130 is on the gate electrode 120. The thin metal layer 140 is located on the first insulating layer 130, and the thin metal layer 140 has a plurality of metal particles 142. The IGZO pellets 150 are located on the metal pellets 142. The sizes and arrangement of the metal particles 142 and the IGZO particles 150 shown in fig. 1 are only schematic and will be described in the first place. The second insulating layer 160 is located on the IGZO pellets 150. That is, the IGZO particles 150 are located between the thin metal layer 140 and the second insulating layer 160. The IGZO channel layer 170 is located on the second insulating layer 160. The source/drain 180 is located on the IGZO channel layer 170. The source/drain 180 includes a source region 182a and a drain region 182 b.
In this embodiment, the memory structure 100 may be a Non-volatile memory (NVM), and may be a Floating gate (Floating gate) memory. The material of the thin metal layer 140 includes silver, and may be a silver metal layer. The thickness H1 of the thin metal layer 140 may be in the range of 1nm to 20nm, for example 10 nm. The thin metal layer 140 may be considered as a nano-silver particle structure. The IGZO pellets 150 are substantially spherical (Sphere). The thickness H2 of the IGZO particles may be in the range of 2nm to 20 nm. The materials of the first insulating layer 130 and the second insulating layer 160 may be the same, for example, both comprise silicon dioxide (SiO)2) But are not intended to limit the invention.
Since the memory structure 100 has the thin metal layer 140 on the first insulating layer 130, and the thin metal layer 140 has the metal grains 142, when an Indium Gallium Zinc Oxide (IGZO) material is formed on the metal grains 142, the IGZO material may form the IGZO grains 150. The IGZO particles 150 may be used as a medium for storing carriers (electrons) entering from the tunneling effect, so as to reduce a Lateral leakage (lareral leakage) of the memory structure 100, ensure a long-term normal operation of the memory structure 100, and avoid information leakage.
FIG. 2 is a flow chart of a method of fabricating the memory structure 100 of FIG. 1. The method of fabricating the memory structure 100 includes the following steps. First, in step S1, a gate electrode is formed on a substrate. Next, in step S2, a first insulating layer is formed on the gate electrode. Next, in step S3, a thin metal layer is formed on the first insulating layer on the gate electrode. Next, in step S4, a thermal annealing process is performed on the thin metal layer to make the thin metal layer have a plurality of metal particles. Thereafter, in step S5, an Indium Gallium Zinc Oxide (IGZO) material is formed on the metal particles, so that the IGZO material is formed into a plurality of IGZO particles. Next, in step S6, a second insulating layer is formed on the IGZO pellets. Thereafter, in step S7, an IGZO channel layer is formed on the second insulating layer. Next, in step S8, source/drain electrodes are formed on the IGZO channel layer.
In the following description, the above steps will be explained.
Referring to fig. 1 and 2, a gate electrode 120 and a first insulating layer 130 are sequentially formed on a substrate 110 such that the first insulating layer 130 is located on the gate electrode 120. The gate electrode 120 and the first insulating layer 130 may be formed by a deposition method (e.g., PVD, CVD), and the gate electrode 120 may be formed by an electroplating method (Plating), which is not intended to limit the invention. The thin metal layer 140 may be formed on the first insulating layer 130 by Thermal evaporation (Thermal evaporation). Accordingly, the thin metal layer 140 may contact the first insulating layer 130. In the present embodiment, the material of the thin metal layer 140 may include silver, and the thickness H1 thereof may be in a range of 1nm to 20nm (e.g., 10 nm). After the thin metal layer 140 is formed, a thermal annealing (thermal annealing) process may be applied to the thin metal layer 140 to make the thin metal layer 140 have metal particles 142 (e.g., nano-silver particles). In the present embodiment, the temperature at which the thin metal layer 140 is subjected to the thermal annealing treatment may be in the range of 50 ℃ to 300 ℃, for example, 200 ℃ for 1 hour.
After the metal particles 142 are formed, Indium Gallium Zinc Oxide (IGZO) material may be formed on the metal particles 142. The IGZO material formed on the metal grains 142 may form IGZO grains 150 due to the metal grains 142 of the thin metal layer 140. The IGZO material may be formed on the metal particles 142 by Sputtering (Sputtering). Thus, the IGZO material may form IGZO grains 150 and directly contact metal grains 142 of thin metal layer 140. The thickness H2 of the IGZO pellets 150 is related to the thickness H1 of the thin metal layer 140. In the present embodiment, since the thin metal layer 140 may have a thickness H1 in the range of 1nm to 20nm, the IGZO particles 150 may have a thickness H2 in the range of 2nm to 20 nm.
In this way, the IGZO grains 150 are prevented from being too compact, so as to reduce the contact area between the IGZO grains 150, thereby effectively reducing the lateral leakage, improving the operation stability of the memory structure 100, and being beneficial to the characteristics of the nonvolatile memory, such as the long-term normal operation of the memory structure 100, and avoiding the missing of information.
After the IGZO pellets 150 are formed, a second insulating layer 160 may be formed on the IGZO pellets 150. In subsequent steps, the IGZO channel layer 170 may be sequentially formed on the second insulating layer 160, and the source/drain electrodes 180 may be formed on the IGZO channel layer 170.
Through the above steps, the memory structure 100 of fig. 1 can be obtained. It is to be understood that the connection, fabrication, materials and functions of the elements described above will not be repeated. In the following description, the states in which the memory structure 100 operates will be described.
FIG. 3 illustrates a current I diagram of the memory structure 100 of FIG. 1. As shown, the IGZO particles 150 are used to store the writing charges in the second insulating layer 160 without affecting the channel current I of the transistor, so the current I still flows from the source region 182a of the source/drain 180 to the drain region 182b of the source/drain 180 through the IGZO channel layer 170.
FIG. 4 is a diagram illustrating an electrical movement of the memory structure 100 of FIG. 1 during a write operation. The memory structure 100 is a Thin Film Transistor (TFT) having an IGZO channel layer 170, and electrons can be tunneled between the IGZO channel layer 170 and the IGZO grains 150 by enhancing a gate electric field based on quantum tunneling. For example, when information is to be written into the memory structure 100, electrons are tunneled from the IGZO channel layer 170 into the IGZO grains 150 by enhancing the gate forward bias, as shown in fig. 4. In the present embodiment, the Conduction band (Conduction band) and valence band (valence band) energies of the IGZO material are-4 eV and-7 eV, respectively.
FIG. 5 is a schematic diagram of electron movement during erasing of the memory structure 100 of FIG. 1. When the memory structure 100 is to remove information, electrons tunnel from the IGZO grains 150 back into the IGZO channel layer 170 by using the gate-enhanced reverse bias, as shown in fig. 5.
Referring to fig. 4 and 5, that is, when the memory structure 100 is operated, a strong forward gate bias is applied, and carriers (electrons) can tunnel from the IGZO channel layer 170 into the IGZO grains 150 for storage; when a reset of the information is required, a strong reverse bias can be applied to tunnel electrons from the IGZO grains 150 back into the IGZO channel 170.
FIG. 6 is a graph of current-gate voltage relationship for the memory structure 100 of FIG. 1. Referring to fig. 1 and fig. 6, fig. 6 is a graph showing the absolute value of the drain current ID and the absolute value of the gate current IG of the memory structure 100 under the condition that the length of the IGZO channel layer 170 is 300 μm and the voltage of the drain region 182b is 20V.
As can be seen from fig. 6, the absolute value data points of the drain current ID constitute one broken line, the absolute value data points of the gate current IG constitute the other broken line, and the trends of the two broken lines are substantially the same and no significant Gap (Gap) exists. Thus, it can be proved that the IGZO particles 150 of the memory structure 100 not only can be used as a medium for storing carriers (electrons) entering from the tunneling effect, but also can effectively reduce the Lateral leakage (lareral leakage) of the memory structure 100, thereby ensuring the long-term normal operation of the memory structure 100 and avoiding the omission of information.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (14)

1. A memory structure, comprising:
a substrate;
a gate on the substrate;
a first insulating layer on the gate electrode;
a thin metal layer on the first insulating layer, having a plurality of metal particles;
a plurality of indium gallium zinc oxide particles located on the plurality of metal particles;
the second insulating layer is positioned on the indium gallium zinc oxide particles;
the indium gallium zinc oxide channel layer is positioned on the second insulating layer; and
and the source/drain is positioned on the indium gallium zinc oxide channel layer.
2. The memory structure of claim 1, in which a thickness of the thin metal layer is in a range of 1nm to 20 nm.
3. The memory structure of claim 1, wherein each of the indium gallium zinc oxide particles has a thickness in a range from 2nm to 20 nm.
4. The memory structure of claim 1, in which a material of the thin metal layer comprises silver.
5. The memory structure of claim 1, in which the plurality of indium gallium zinc oxide particles contact the thin metal layer.
6. The memory structure of claim 1, wherein the thin metal layer contacts the first insulating layer.
7. The memory structure of claim 1, in which the plurality of indium gallium zinc oxide particles are located between the thin metal layer and the second insulating layer.
8. A method of fabricating a memory structure, comprising:
forming a thin metal layer on the first insulating layer on the gate electrode;
subjecting the thin metal layer to a thermal annealing process to make the thin metal layer have a plurality of metal particles;
forming an indium gallium zinc oxide material on the plurality of metal particles, so that the indium gallium zinc oxide material forms a plurality of indium gallium zinc oxide particles;
forming a second insulating layer on the plurality of indium gallium zinc oxide particles;
forming an indium gallium zinc oxide channel layer on the second insulating layer; and
and forming a source/drain on the indium gallium zinc oxide channel layer.
9. The method of claim 8, wherein forming the thin metal layer on the first insulating layer is performed by thermal evaporation.
10. The method of manufacturing a memory structure of claim 8, wherein a temperature at which the thermal annealing process is applied to the thin metal layer is in a range of 50 ℃ to 300 ℃.
11. The method of claim 8, wherein forming the indium gallium zinc oxide material on the plurality of metal particles is performed by sputtering.
12. The method of fabricating a memory structure according to claim 8, wherein the thin metal layer has a thickness in a range of 1nm to 20 nm.
13. The method of fabricating a memory structure according to claim 8, wherein each of the indium gallium zinc oxide particles has a thickness in a range of 2nm to 20 nm.
14. The method of claim 9, wherein the material of the thin metal layer comprises silver.
CN201910338092.7A 2019-04-25 2019-04-25 Memory structure and manufacturing method thereof Pending CN111863827A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022005A (en) * 1998-06-26 2000-01-21 Toshiba Corp Semiconductor device
US20050045943A1 (en) * 2003-08-25 2005-03-03 Hsiang-Lan Lung [non-volatile memory cell and fabrication thereof]
US20090085094A1 (en) * 2007-09-27 2009-04-02 Jang-Sik Lee Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof
KR101355813B1 (en) * 2012-10-24 2014-01-28 한국과학기술원 Nonvolatile memory device including self-assembled monolayer
CN107482014A (en) * 2017-07-04 2017-12-15 复旦大学 A kind of multi-level unit thin-film transistor memory and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022005A (en) * 1998-06-26 2000-01-21 Toshiba Corp Semiconductor device
US20050045943A1 (en) * 2003-08-25 2005-03-03 Hsiang-Lan Lung [non-volatile memory cell and fabrication thereof]
US20090085094A1 (en) * 2007-09-27 2009-04-02 Jang-Sik Lee Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof
KR101355813B1 (en) * 2012-10-24 2014-01-28 한국과학기술원 Nonvolatile memory device including self-assembled monolayer
CN107482014A (en) * 2017-07-04 2017-12-15 复旦大学 A kind of multi-level unit thin-film transistor memory and preparation method thereof

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