CN111863592B - Post-polish cleaning method and method for forming semiconductor structure - Google Patents
Post-polish cleaning method and method for forming semiconductor structure Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A post-polish cleaning method suitable for cleaning a polished wafer to remove contaminant particles on the wafer surface, and a method of forming a semiconductor structure, the post-polish cleaning method comprising: performing a first cleaning process on the wafer, wherein the first cleaning process comprises a first sub-cleaning process, and the step of the first sub-cleaning process comprises the following steps: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; wherein the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer; and after the first cleaning process is executed, drying the wafer. The embodiment of the invention is beneficial to improving the cleaning effect on the wafer and effectively reducing the residual quantity of pollutant particles on the wafer.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a post-grinding cleaning method and a semiconductor structure forming method.
Background
In the fabrication of Integrated Circuit (IC) chips, a wafer cleaning process is often required for semiconductor wafers (wafer) used to manufacture ICs. The purpose of wafer cleaning is to remove contaminants (Contamination) such as organic residues (residues), metallic impurities or particles (particles) adhering to the wafer surface. The pollution of metal impurities can cause phenomena of electric leakage of PN junction interface, breakdown voltage reduction of grid oxide layer and the like; the adhesion of particles can affect the authenticity of the pattern transfer of the lithographic process and can even cause shorting of the circuit structure. Therefore, wafer cleaning directly affects the yield of integrated circuit fabrication, and the industry has sought the most effective cleaning method for removing contaminants such as organic residues, metallic impurities or particulates.
In the fabrication of integrated circuits, a planarization process is typically performed using a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process. However, during the cmp process, the polishing particles and polishing byproducts are easily adsorbed on the wafer surface to form contaminant particles, which are easily defective (Defect) in the subsequent process. Therefore, after performing the cmp process, a cleaning process is also required to be performed on the wafer to remove contaminant particles on the wafer surface so as to reduce defects.
Disclosure of Invention
The problem solved by the embodiment of the invention is to provide a post-grinding cleaning method and a method for forming a semiconductor structure, so that the cleaning effect on a wafer is improved.
In order to solve the above problems, an embodiment of the present invention provides a post-polishing cleaning method, which is suitable for cleaning a polished wafer, and removing contaminant particles on the surface of the wafer, and includes: performing a first cleaning process on the wafer, wherein the first cleaning process comprises a first sub-cleaning process, and the step of the first sub-cleaning process comprises the following steps: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; wherein the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer; and after the first cleaning process is executed, drying the wafer.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, a metal gate structure is formed on the substrate, an interlayer dielectric layer is formed on the substrate exposed by the metal gate structure, the top of the interlayer dielectric layer is higher than the top of the metal gate structure, a groove is formed by the top of the metal gate structure and the interlayer dielectric layer in a surrounding mode, a hard mask material layer is formed in the groove, and the top of the interlayer dielectric layer is covered by the hard mask material layer; grinding the hard mask material layer, wherein the residual hard mask material layer after the grinding is used as a hard mask layer; and after the grinding treatment, cleaning the wafer by adopting the cleaning method.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention executes a first cleaning process on the wafer, wherein the first cleaning process comprises a first sub-cleaning process, and the steps of the first sub-cleaning process comprise: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer. The megasonic deionized water can realize high-frequency vibration, correspondingly increase the vibration frequency of pollutant particles, reduce the physical contact and adsorption of the pollutant particles and the surface of the wafer, and therefore, the megasonic deionized water can be matched with a first chemical cleaning agent, so that the pollutant particles are easy to separate from the surface of the wafer, the residual quantity of the pollutant particles on the wafer is effectively reduced, the cleaning effect of the wafer is further improved, and the performance and the yield of the formed semiconductor structure are correspondingly improved.
In an alternative, the first cleaning process further includes a second sub-cleaning process after the first sub-cleaning process, and the step of the second sub-cleaning process includes: adopting deionized water and a second chemical cleaning agent to carry out second flushing treatment; the second chemical cleaning agent and the first chemical cleaning agent have the same components, and the mass percentage concentration of the second chemical cleaning agent is smaller than that of the first chemical cleaning agent; the first chemical cleaning agent with higher mass percent concentration is adopted to carry out first flushing treatment, so that the first chemical cleaning agent can obviously improve the hydrophilicity of the surfaces of pollutant particles and increase the electric repulsive force between the pollutant particles and the surfaces of the wafers, and the second chemical cleaning agent with lower mass percent concentration is adopted to carry out second flushing treatment, so that the problem that the chemical cleaning agent is difficult to remove due to the too high concentration is solved, the flushing requirement is met, the problem of chemical component residues of the chemical cleaning agent is solved, and the cleaning effect on the wafers is further improved.
Drawings
FIG. 1 is a flowchart corresponding to each step in an embodiment of a post-polish cleaning method according to the present invention;
FIG. 2 is a flow chart corresponding to each step in the first cleaning process in FIG. 1;
FIG. 3 is a flowchart corresponding to each step in the first sub-cleaning process of FIG. 2;
FIG. 4 is a flowchart corresponding to each step in the second sub-cleaning process of FIG. 2;
FIG. 5 is a flowchart corresponding to each step in the second cleaning process of FIG. 1;
fig. 6 to 7 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
In the semiconductor field, a step of polishing a wafer is generally included. After the polishing process, contaminant particles such as polishing particles and organic contaminants typically remain on the wafer surface.
Therefore, after the polishing process, the wafer is generally cleaned to remove the contaminant particles generated during the polishing process, so as to prevent defects in the subsequent process.
Current post-polish cleaning methods typically include performing at least one cleaning process, which typically includes the steps of: and brushing the wafer by adopting a chemical cleaning agent, wherein the chemical cleaning agent is suitable for increasing the hydrophilia of pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer.
However, in the polishing step, the wafer surface usually has a Zeta potential of positive or negative, and the wafer surface is easy to adsorb contaminant particles with opposite Zeta potential, and the contaminant particles have a strong electric adsorption force with the wafer surface, so that the contaminant particles are difficult to remove by adopting the post-polishing cleaning method. The Zeta potential refers to a potential generated on the surface of a particle when the particle exists in a liquid.
For example: in the semiconductor field, after forming a metal gate (gate) structure, it also generally includes: and forming a hard mask layer on the top of the metal gate structure, wherein the hard mask layer is used for protecting the top of the metal gate structure in the subsequent etching process step of forming the source-drain contact hole, thereby realizing the self-alignment of the etching process. Specifically, forming the hard mask layer generally includes a step of performing a grinding process to planarize a surface of the hard mask layer and to make a thickness of the hard mask layer meet process requirements.
The material of the hard mask layer is usually silicon nitride, the Zeta potential of the silicon nitride material is usually positive in the step of grinding treatment, pollutant particles with negative Zeta potential are easily adsorbed on the surface of the hard mask layer, the pollutant particles and the surface of the hard mask layer have stronger adsorption force, and the pollutant particles are difficult to remove by adopting the method for cleaning after grinding.
With further reduction of process nodes, further requirements are put on the size and the number of pollutant particles on the surface of the wafer, the pollutant particles on the surface of the wafer are difficult to effectively remove by adopting the method for cleaning after grinding, and the cleaning effect is difficult to meet the process requirements.
In order to solve the technical problem, an embodiment of the present invention provides a post-polishing cleaning method, which is suitable for cleaning a polished wafer, and removing contaminant particles on the surface of the wafer, and includes: performing a first cleaning process on the wafer, wherein the first cleaning process comprises a first sub-cleaning process, and the step of the first sub-cleaning process comprises the following steps: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; wherein the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer; and after the first cleaning process is executed, drying the wafer.
The steps of the first sub-cleaning process in the embodiment of the invention include: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer. The megasonic deionized water can realize high-frequency vibration, correspondingly increase the vibration frequency of pollutant particles, reduce the physical contact and adsorption of the pollutant particles and the surface of the wafer, and therefore, the megasonic deionized water can be matched with a first chemical cleaning agent, so that the pollutant particles are easy to separate from the surface of the wafer, the residual quantity of the pollutant particles on the wafer is effectively reduced, the cleaning effect of the wafer is further improved, and the performance and the yield of the formed semiconductor structure are correspondingly improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
FIG. 1 is a flow chart showing the steps corresponding to one embodiment of the post-polish cleaning method of the present invention.
The cleaning method is suitable for cleaning the polished wafer, and cleaning pollutant particles on the surface of the wafer, so that the cleaning effect meets the process requirement.
Referring to fig. 1 and 2 in combination, fig. 2 is a flowchart corresponding to each step in the first cleaning process in fig. 1, and step S1 is performed to perform a first cleaning process on the wafer, where the steps of the first cleaning process include: step S11 is executed to perform a first sub-cleaning process on the wafer.
The first cleaning process is used to substantially remove larger sized contaminant particles (e.g., abrasives and polishing byproducts) generated after polishing.
Specifically, referring to fig. 3 in combination, fig. 3 is a flowchart corresponding to each step in the first sub-cleaning process in fig. 2, where the steps in the first sub-cleaning process include: step S111 is performed, wherein a first rinsing process is performed using Megasonic (Megasonic) Deionized water (DIW) and a first chemical cleaning agent; the first chemical cleaning agent is suitable for increasing the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the surface of the wafer.
Megasonic is sound wave with frequency higher than 1000000Hz, the megasonic deionized water can realize high-frequency vibration, correspondingly increase the vibration frequency of pollutant particles, reduce the physical contact and adsorption of the pollutant particles and the surface of a wafer, and therefore, the megasonic deionized water can be matched with a first chemical cleaning agent to realize the effect of removing a large amount of pollutant particles, so that the pollutant particles are easy to separate from the surface of the wafer, the residual quantity of the pollutant particles on the wafer is effectively reduced, the cleaning effect of the wafer is further improved, and the performance and the yield of the formed semiconductor structure are correspondingly improved.
The megasonic wave is a high-frequency oscillation signal sent by a megasonic generator, and is converted into high-frequency mechanical oscillation by a transducer to be propagated to a medium, the megasonic wave is radiated forwards in a solution in a dense and alternate way, so that liquid flows to generate tens of thousands of tiny bubbles, the tiny bubbles (cavitation nuclei) existing in the liquid vibrate under the action of a sound field, when the sound pressure reaches a certain value, the bubbles are rapidly grown and then suddenly closed, shock waves are generated when the bubbles are closed, thousands of atmospheric pressures are generated around the bubbles, and therefore the accelerated movement and vibration of pollutant particles are forced, and the physical contact and adsorption of the pollutant particles and the wafer surface are reduced, so that the pollutant particles are separated from the wafer surface.
The chemical cleaning agent for post-polishing cleaning generally includes a surfactant, a corrosion inhibitor, a PH adjuster, and the like. Wherein the surfactant is capable of altering the hydrophilicity or hydrophobicity, and electronegativity, of the surface of the contaminant particles; the corrosion inhibitor is used for reducing the corrosion of the chemical cleaning agent to the surface of the wafer; the surface electrical properties of the pollutant particles under solutions with different pH values are different, and the pH value regulator is used for being matched with the surfactant, so that the electrical properties of the pollutant particles meet the process requirements.
In this embodiment, the surfactant in the first chemical cleaning agent can improve the hydrophilicity of the surface of the contaminant particles, so that the contaminant particles are easy to be removed under the scouring action of hydraulic force; the surfactant can also reduce the potential difference between the contaminant particles and the wafer surface, even making the contaminant particles have the same electrical properties as the wafer surface, thereby increasing the electrical repulsive force of the contaminant particles to the wafer surface. In summary, the first chemical cleaning agent is beneficial to reducing the adhesion of contaminant particles on the surface of the wafer, so that the contaminant particles are easy to wash away.
The megasonic power of the megasonic deionized water should not be too low. If the megasonic power is too low, the energy density of the megasonic and the vibration frequency of the megasonic deionized water are correspondingly too low, and the megasonic deionized water has poor effect of reducing physical contact and adsorption of contaminant particles with the wafer surface, thereby resulting in a reduction in cleaning effect, and for this reason, the megasonic power of the megasonic deionized water is at least 40 watts.
The greater the megasonic power, the better the cleaning effect. However, if the megasonic power is too high, it tends to decrease the uniformity of the energy density of the megasonic waves and damage the pattern on the wafer surface. For this reason, in this embodiment, the megasonic deionized water has megasonic power of 40 watts to 200 watts.
The higher the mass percentage concentration of the first chemical cleaning agent, the higher the content of the surfactant in the first chemical cleaning agent, so the mass percentage concentration of the first chemical cleaning agent is not too low, otherwise, the effect of increasing the hydrophilicity of the surfaces of the pollutant particles and the electric repulsive force between the pollutant particles and the surfaces of the wafers is difficult to achieve. For this purpose, in this embodiment, the concentration of the first chemical cleaning agent is at least 5% by mass.
It should be noted that, compared with a chemical cleaning agent adopted in a conventional post-grinding cleaning process, the mass percentage concentration of the first chemical cleaning agent is higher in this embodiment, so that the hydrophilicity of the surface of the contaminant particles and the electrical repulsive force between the contaminant particles and the surface of the wafer can be significantly increased, and the first chemical cleaning agent and megasonic deionized water are further matched, so that the contaminant particles are more easily separated from the surface of the wafer, and a cleaning effect of removing a large number of contaminant particles is achieved.
However, the concentration of the first chemical cleaning agent in mass percentage cannot be too high, otherwise, the first chemical cleaning agent is difficult to remove later, organic residues are easy to generate, and the process stability of the first washing treatment is easy to be reduced. For this purpose, in this embodiment, the concentration of the first chemical cleaning agent is 5% to 30% by mass.
The treatment time of the first flushing treatment is not too short nor too long. If the treatment time of the first rinse treatment is too short, it is likely to result in a first rinse treatment that is less effective for removing a large amount of contaminant particles; if the treatment time of the first flushing treatment is too long, the waste of the process time is easily caused, and the production capacity is reduced. For this reason, in the present embodiment, the treatment time of the first flushing treatment is 5 seconds to 20 seconds.
In this embodiment, in the step of the first flushing treatment, each parameter is reasonably set and matched with each other, so that the manufacturing efficiency is improved and a better process effect is achieved.
With continued reference to fig. 3, in this embodiment, the step of the first sub-cleaning process further includes: after the first rinsing process, step S112 is performed, and a first brushing process is performed using deionized water and the first chemical cleaning agent.
The first brushing treatment is used for further removing pollutant particles remained on the surface of the wafer.
Specifically, the first chemical cleaning agent is still adopted in the first brushing treatment, so that the pollutant particles still keep a larger repulsive force with the surface of the wafer, and further the pollutant particles are easy to brush off from the surface of the wafer.
In this embodiment, the flow and the concentration of the first chemical cleaning agent in the first brushing treatment and the first rinsing treatment are the same, which is beneficial to maintaining the flow stability of the first chemical cleaning agent and reducing the complexity of the operation of the cleaning machine.
Specifically, in the first brushing treatment step, a soft brush (brush) is used to act on the surface of the wafer at a certain extrusion force and rotation speed, so that the surface of the wafer is brushed, and pollutant particles remained on the surface of the wafer are further removed through the physical action of the soft brush and the surface of the wafer and the hydraulic flushing action of deionized water.
With continued reference to fig. 3, in this embodiment, the step of the first sub-cleaning process further includes: after the first brushing treatment, step S113 is executed, and a second brushing treatment is performed by using deionized water.
In the step of the second brushing treatment, the washing of the first chemical cleaning agent is stopped, the washing of deionized water is kept, and therefore the first chemical cleaning agent on the surface of the wafer is removed, the problem that chemical components of the first chemical cleaning agent remain on the wafer and the brush to form organic residues is solved, meanwhile, the extrusion force and rotating working state of the soft brush on the surface of the wafer are kept, and therefore residual pollutant particles and the first chemical cleaning agent components are brushed away from the surface of the wafer.
With continued reference to fig. 3, in this embodiment, the step of the first sub-cleaning process further includes: after the second brushing treatment, step S114 is executed, and deionized water is used to perform the first washing treatment.
Specifically, deionized water is used to rinse the wafer surface.
During the second brushing process, contaminant particles may adhere to the soft brush, and therefore, during the first water washing process, the soft brush is stopped to prevent contaminant particles adhering to the soft brush from sticking back to the wafer surface, and at the same time, the wafer surface is rinsed with deionized water to further rinse away residual contaminant particles and residual first chemical cleaner composition.
With continued reference to fig. 2, in this embodiment, the step of the first cleaning process further includes: after the first sub-cleaning process is performed, step S12 is performed to perform a second sub-cleaning process on the wafer.
The second sub-cleaning process is used for further removing pollutant particles on the surface of the wafer after the first sub-cleaning process, so that the cleaning effect on the wafer is further improved.
Specifically, referring to fig. 4 in combination, fig. 4 is a flowchart corresponding to each step in the second sub-cleaning process in fig. 2, where the steps in the second sub-cleaning process include: step S121 is executed, in which a second rinsing process is performed using deionized water and a second chemical cleaning agent. The second chemical cleaning agent and the first chemical cleaning agent have the same components, and the mass percentage concentration of the second chemical cleaning agent is smaller than that of the first chemical cleaning agent.
The first chemical cleaning agent with higher mass percent concentration is adopted to carry out first flushing treatment, so that the first chemical cleaning agent can obviously improve the hydrophilicity of the surfaces of pollutant particles and increase the electric repulsive force between the pollutant particles and the surfaces of the wafers, and the second chemical cleaning agent with lower mass percent concentration is adopted to carry out second flushing treatment, so that the problem that the chemical cleaning agent is difficult to remove due to the fact that the concentration of the chemical cleaning agent is too high is solved, the problem of chemical component residues of the chemical cleaning agent is solved while the flushing requirement is met, and the cleaning effect on the wafers is further improved.
In addition, the subsequent step further includes a step of performing a third brushing treatment, and the second rinsing treatment is also used as a pretreatment step to maintain the hydrophilicity of the contaminant particles and the electrical repulsive force of the contaminant particles with the wafer surface, thereby preparing for the subsequent third brushing treatment.
Therefore, the concentration of the second chemical cleaning agent in mass percent is not too low nor too high. If the mass percentage concentration of the second chemical cleaning agent is too low, in the step of the second flushing treatment, the effect of the second chemical cleaning agent on changing the hydrophilicity and electronegativity of the surfaces of the pollutant particles is not obvious, and the adhesion force of the pollutant particles on the surfaces of the wafers is difficult to reduce, so that the effect of enabling the pollutant particles to be easily removed under the flushing effect of water power is difficult to be achieved; if the mass percentage concentration of the second chemical cleaning agent is too high, even if the mass percentage concentration of the second chemical cleaning agent is smaller than the mass percentage concentration of the first chemical cleaning agent, it may cause a problem that the second chemical cleaning agent is difficult to be completely removed later, thereby easily generating organic residues. Therefore, in this embodiment, the mass percentage concentration of the second chemical cleaning agent is 5% to 20% of the mass percentage concentration of the first chemical cleaning agent.
The second rinse treatment should not be too short or too long. If the treatment time of the second rinsing treatment is too short, the second rinsing treatment is difficult to increase the hydrophilicity of the surfaces of the contaminant particles and the electrical repulsive force between the contaminant particles and the surfaces of the wafers, so that the effect of removing the contaminant particles by the second rinsing treatment is poor, and when the third brushing treatment is performed subsequently, the repulsive force between the contaminant particles and the surfaces of the wafers is insufficient, so that the effect of the third brushing treatment is poor; if the second rinsing treatment is too long, the waste of the process time is easily caused, and the production capacity is reduced. For this reason, in the present embodiment, the treatment time of the second flushing treatment is 5 seconds to 20 seconds.
With continued reference to fig. 4, in this embodiment, the step of the second sub-cleaning process further includes: after the second rinsing process, step S122 is performed, and a third brushing process is performed using deionized water and the second chemical cleaning agent.
The third brushing treatment is used for further removing the residual pollutant particles on the surface of the wafer.
Specifically, the second chemical cleaning agent is still adopted in the third brushing treatment, so that the hydrophilicity of the pollutant particles is maintained, and the pollutant particles still keep a larger repulsive force with the surface of the wafer, so that the pollutant particles are easy to brush off from the surface of the wafer.
In this embodiment, the flow and the concentration of the second chemical cleaning agent in the third brushing treatment and the second rinsing treatment are the same, which is beneficial to improving the flow stability of the second chemical cleaning agent and reducing the complexity of the machine operation.
Meanwhile, the soft brush is used for acting on the surface of the wafer at a certain extrusion force and rotation speed to brush the surface of the wafer, so that pollutant particles remained on the surface of the wafer are further removed through the physical action of the soft brush and the surface of the wafer.
With continued reference to fig. 4, in this embodiment, the step of the second sub-cleaning process further includes: after the third brushing treatment, step S123 is executed, and the deionized water is used for the fourth brushing treatment.
In the fourth brushing treatment step, the second chemical cleaning agent is stopped, deionized water is adopted for washing, so that the second chemical cleaning agent on the surface of the wafer is removed, the problem that organic residues are formed due to the fact that components of the second chemical cleaning agent remain on the wafer and the soft brush is solved, meanwhile, the extrusion force and the rotating working state of the soft brush on the surface of the wafer are maintained, and residual pollutant particles and the components of the second chemical cleaning agent are brushed away from the surface of the wafer under the physical action of the soft brush and the surface of the wafer.
With continued reference to fig. 4, in this embodiment, the step of the second sub-cleaning process further includes: after the fourth brushing treatment, step S124 is performed, and the third water washing treatment is performed using deionized water.
In the fourth brushing treatment step, contaminant particles may adhere to the soft brush, and thus, in the third water washing treatment step, the soft brush is stopped to prevent the contaminant particles adhering to the soft brush from being adhered back to the wafer surface, and at the same time, deionized water is used to wash the wafer surface to further remove residual contaminant particles and residual chemical cleaning agent components under the scouring action of water flow.
With continued reference to fig. 1, after the first cleaning process is performed, step S3 is performed to dry the wafer.
The drying treatment is used for removing the moisture on the surface of the wafer, so that the surface of the wafer is dried, and preparation is made for the subsequent process.
In this embodiment, the step of drying includes: the wafer was dried using IPA (iso-Propyl alcohol) solution and inert gas.
The IPA solution can improve the hydrophobicity of the surface of the wafer, so that the water on the surface of the wafer is changed into a water film, and the water film can be blown away from the surface of the wafer through inert gas, so that the surface of the wafer is dried.
In this embodiment, the inert gas may be nitrogen. The nitrogen is the inert gas commonly used in the semiconductor process, is easy to obtain, and is beneficial to saving the cost and improving the process compatibility.
In other embodiments, according to actual process requirements, other suitable drying processes may be used to dry the wafer surface.
It should be noted that, referring to fig. 1 in this embodiment, after the first cleaning process is performed, before the drying process is performed, the method further includes: step S2 is executed to execute a second cleaning process on the wafer.
Referring to fig. 5 in combination, fig. 5 is a flowchart corresponding to each step in the second cleaning process in fig. 1, where the steps in the second cleaning process include: step S21 is executed, wherein the wafer surface is subjected to pre-washing treatment by adopting a third chemical cleaning agent, the components of the third chemical cleaning agent are the same as those of the first chemical cleaning agent, and the mass percentage concentration of the third chemical cleaning agent is smaller than that of the first chemical cleaning agent; after the pre-rinsing treatment, step S22 is executed, and the third chemical cleaning agent is adopted to perform a scraping treatment on the surface of the wafer.
The pre-rinse treatment is used for maintaining the hydrophilicity and surface electrical property of the pollutant particles, so that the pollutant particles are easy to remove under the flushing action of water power, the electrical repulsive force between the pollutant particles and the surface of the wafer is increased, the residual pollutant particles after the second sub-cleaning process are prevented from being stuck back to the surface of the wafer, and meanwhile, the preparation is also provided for the subsequent scraping and cleaning treatment.
And the mass percentage concentration of the third chemical cleaning agent is smaller than that of the first chemical cleaning agent, so that the problem that the chemical cleaning agent is difficult to remove due to the fact that the concentration of the chemical cleaning agent is too high is solved, the problem of chemical component residues of the chemical cleaning agent is solved, and the cleaning effect on wafers is further improved.
Specifically, the concentration of the third chemical cleaning agent may be the same as the concentration of the second chemical cleaning agent.
The scraping and washing treatment is used for further removing tiny pollutant particles remained on the surface of the wafer after the second sub-washing process is executed.
The scraping and washing treatment comprises the following steps: the method comprises the steps of scraping and washing the wafer from the center to the edge of the wafer at a preset moving speed by adopting a pencil sponge brush (pencil sponge), and gradually reducing the preset moving speed of the pencil sponge brush along the direction of the center of the wafer to the edge of the wafer.
The pencil sponge brush is a pencil-shaped sponge brush, and compared with the soft brush, the pencil sponge brush is softer in material, and in the step of scraping and washing treatment, the pencil sponge brush has a certain extrusion force on the surface of the wafer, so that the pencil sponge brush is favorable for removing pollutant particles which are adsorbed tightly on the surface of the wafer, and meanwhile, the influence on the structure and the graph of the surface of the wafer is small.
In the foregoing step and the step of the scraping and washing process, the wafer always maintains a rotating state, so that the linear velocity at the center of the wafer is minimum, contaminant particles located at the center of the wafer are correspondingly difficult to remove, and the linear velocity of the wafer gradually increases along the direction of the center of the wafer toward the edge of the wafer, and the adhesion force of the contaminant particles on the wafer gradually decreases, that is, the removal difficulty of the contaminant particles is also gradually reduced, and the number of the contaminant particles is correspondingly reduced.
Therefore, in this embodiment, along the direction of the wafer center pointing to the wafer edge, the preset moving speed of the pencil sponge brush decreases, so that the contaminant particles can be scraped from the wafer center to the wafer edge in cooperation with the wafer linear speeds at different positions on the wafer, and finally removed under the scouring action of water flow and thrown out of the wafer surface under the rotation of the wafer.
In this embodiment, in the step of the scraping and washing process, the pencil sponge brush has a preset rotation speed.
The rotating pencil sponge brush can bring pollutant particles which are adsorbed tightly with the wafer away from the surface of the wafer, so that the residual pollutant particles are removed under the flushing action of water power; meanwhile, the pencil sponge brush is scraped from the center of the wafer to the edge of the wafer, so that pollutant particles are taken away from the center of the wafer to the edge of the wafer and removed under the flushing action of water power and the rotating and swinging action of the wafer.
The rotation speed of the pencil sponge brush is not too small or too large. If the rotation speed of the pencil sponge brush is too small, the pencil sponge brush is difficult to bring pollutant particles out of the surface of the wafer; if the rotation speed of the pencil sponge brush is too high, scratches (scratch) are easily caused to the surface of the wafer. For this reason, in this embodiment, the pencil sponge brush has a rotation speed of 200RPM (Revolutions Per Minute ) to 300RPM.
It should be noted that, in order to maintain a large electrical repulsive force between the contaminant particles and the wafer surface and make the contaminant particles easy to be washed away by the water flow, the third chemical cleaning agent needs to be continuously washed away during the step of the scraping and washing treatment. Wherein the scraping treatment and the pre-flushing treatment adopt the same components, concentration and flow rate of a third chemical cleaning agent.
With continued reference to fig. 5, in this embodiment, the step of the second cleaning process further includes: after the scraping and washing process, step S23 is performed to perform a gas cleaning process on the wafer.
By the gas cleaning treatment, fine contaminant particles remaining in the depressions of the wafer surface can be further removed.
The density and the quality of the gas are smaller, and the gas can be sprayed to the surface of the wafer at a larger speed by adopting a gas cleaning treatment mode, so that tiny pollutant particles which are difficult to remove and remain in the concave position of the surface of the wafer are further removed, the cleaning effect is improved, and meanwhile, the damage to the structure and the graph of the surface of the wafer is smaller.
In this embodiment, after the scraping and washing process, the gas cleaning process is performed, so that the situation that tiny contaminant particles remain in the concave position of the surface of the wafer after the scraping and washing process is prevented, and the cleaning effect on the wafer is improved.
Specifically, the gas cleaning treatment is performed using a mixed gas of an inert gas and carbon dioxide.
The carbon dioxide is easy to generate bubbles, so that the carbon dioxide is easy to be atomized, and can be carried by inert gas to spray on the surface of the wafer. Moreover, the carbon dioxide gas is easy to obtain, which is beneficial to saving the cost and improving the compatibility.
In this embodiment, the inert gas is nitrogen. Nitrogen is the inert gas commonly used in the semiconductor process, which is beneficial to saving the cost and improving the process compatibility.
The step of performing the gas cleaning process includes: and (3) adopting mixed gas of nitrogen and carbon dioxide in a certain proportion, and after atomization (mist) treatment, flushing the surface of the wafer at a high speed along the direction of the center of the wafer pointing to the edge of the wafer.
Thus, the mixed gas used in the gas cleaning process also includes water vapor. The water vapor is favorable for keeping the pollutant particles on the surface of the wafer in a wet state, so that the residual pollutant particles are easy to remove under the flushing action of water power in the subsequent steps.
The total flow rate of the gas used for the gas cleaning treatment is not too small nor too large. If the total flow is too small, the cleaning effect of the gas cleaning treatment is easily reduced; if the total flow is too large, damage may also be caused to the wafer surface. For this reason, in this embodiment, the total flow rate of the gas used for the gas cleaning process is 200 standard liters per minute to 300 standard liters per minute.
In this embodiment, a single scraping treatment and a gas cleaning treatment will be described as an example.
In other embodiments, the scraping and cleaning process and the gas cleaning process may be alternately performed multiple times according to actual process requirements, so as to improve the cleaning effect on the wafer. In this embodiment, the last step is a gas cleaning process, so as to prevent the tiny contaminant particles remaining in the concave portion of the wafer surface after the scraping process from being removed completely.
With continued reference to fig. 5, in this embodiment, the step of the second cleaning process further includes: after the gas cleaning treatment, executing a step S24, and performing a third flushing treatment by adopting deionized water and the third chemical cleaning agent; after the third rinsing process, step S25 is performed, and a second rinsing process is performed using deionized water.
And through the third flushing treatment, the hydrophilicity of the pollutant particles and the electric repulsive force between the pollutant particles and the wafer surfaces of the pollutant particles are maintained, and the residual tiny pollutant particles after being cleaned by the gas cleaning treatment are prevented from being stuck back to the wafer surfaces.
In this embodiment, the mass percentage concentration and the flow rate of the third chemical cleaning agent used in the third washing are the same as those of the third chemical cleaning agent used in the scraping treatment, which is favorable for maintaining the flow stability of the third chemical cleaning agent and reducing the complexity of the machine operation.
For a specific description of the third rinsing process, reference may be made to the foregoing description of the second rinsing process, which is not repeated herein.
The second water washing treatment is used for removing the third chemical cleaning agent in the third washing treatment step.
For a specific description of the second water washing process, reference may be made to the foregoing detailed description of the first water washing process, which is not repeated herein.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Referring to fig. 6 to 7, schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention are shown.
Referring to fig. 6, a wafer (not shown) is provided, the wafer includes a substrate (not shown), a metal gate structure 123 is formed on the substrate, an interlayer dielectric layer 122 is formed on the substrate where the metal gate structure 123 is exposed, the top of the interlayer dielectric layer 122 is higher than the top of the metal gate structure 123, a recess (not shown) is defined by the top of the metal gate structure 123 and the interlayer dielectric layer 122, a hard mask material layer 124 is formed in the recess, and the hard mask material layer 124 also covers the top of the interlayer dielectric layer 122.
In this embodiment, taking a formed semiconductor structure as a fin field effect transistor (FinFET), the base includes a substrate 100 and a fin portion 110 protruding from the substrate 100. In other embodiments, when the semiconductor structure formed is a planar field effect transistor, the base includes only the substrate, respectively.
The substrate 100 is used to provide a process platform for a process recipe.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, an isolation layer 111 is formed on the substrate 100 exposed by the fin 110, and the isolation layer 111 covers a portion of the sidewall of the fin 110. The isolation layer 111 is used to electrically isolate adjacent devices from each other.
In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation structure may be an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
The metal gate structure 123 is used to control the on or off of the conductive channel when the semiconductor structure is in operation. Specifically, the metal gate structure 123 spans a portion of the top and a portion of the sidewalls of the fin 110.
The metal gate structure 123 includes a high-k dielectric layer (not shown) and a gate electrode layer (not shown) on the high-k dielectric layer.
The material of the high-k gate dielectric layer is a high-k gate dielectric material, wherein the high-k gate dielectric material refers toThe gate dielectric material with a relative dielectric constant greater than that of silicon oxide can be HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO 2 Or Al 2 O 3 . In this embodiment, the material of the high-k gate dielectric layer is HfO 2 。
The gate electrode layer is Al, cu, ag, au, pt, ni, ti or W. In this embodiment, the material of the gate electrode layer is correspondingly W.
In this embodiment, the sidewall of the metal gate structure 123 is further formed with a sidewall 115. The sidewall 115 is used to protect the sidewall of the metal gate structure 123, and the sidewall 115 is also used to define a formation region of the source-drain doped layer.
In this embodiment, the side wall 115 is a stacked structure, and the side wall 115 includes a first side wall (not shown) located on a side wall of the metal gate structure 123, a second side wall (not shown) located on a side wall of the first side wall, and a third side wall (not shown) located on a side wall of the second side wall. In other embodiments, the side wall may also have a single-layer structure.
In this embodiment, the material of the first side wall and the third side wall is silicon oxide, and the material of the second side wall is silicon nitride.
In this embodiment, the metal gate structure 123 is formed by a process of forming a metal gate (high k last metal gate last) by forming a high-k gate dielectric layer, and the dummy gate structure is a stacked structure before forming the metal gate structure 123, so that a dummy gate oxide layer 112 is further formed between the sidewall 115 and the fin 110. In the process of removing the dummy gate structure to form the metal gate structure 123, the dummy gate oxide 112 between the sidewall 115 and the fin 110 is maintained under the protection of the sidewall 115.
In this embodiment, the material of the dummy gate oxide layer 112 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
In this embodiment, the source-drain doped layer 120 is further formed in the fin portion 110 at two sides of the metal gate structure 123.
When forming an NMOS transistor, the source-drain doped layer 120 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 120 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
The interlayer dielectric layer 122 is used for isolating adjacent devices, and the interlayer dielectric layer 122 is also used for providing a process platform for forming the metal gate structure 123.
Thus, the material of the interlayer dielectric layer 122 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 122 has a single-layer structure, and the material of the interlayer dielectric layer 122 is silicon oxide.
The hard mask material layer 124 is used for forming a hard mask layer later, so as to realize self-alignment of an etching process for forming a source-drain contact hole later.
In this embodiment, the material of the hard mask material layer 124 is silicon nitride.
Referring to fig. 7, the hard mask material layer 124 is subjected to a polishing process, and the remaining hard mask material layer 124 after the polishing process serves as a hard mask layer 125.
The hard mask layer 125 is used to protect the top of the metal gate structure 124, and in the subsequent etching process for forming the source-drain contact hole, the hard mask layer 125 is also used to realize the self-alignment of the etching process, so as to prevent the bridging (bridge) problem between the subsequent contact hole plug and the metal gate structure 124.
Specifically, the polishing treatment is performed using a chemical mechanical polishing process.
In this embodiment, the material of the hard mask material layer 124 is silicon nitride, and in the process of performing the polishing treatment on the hard mask material layer 124, the surface of the hard mask material layer 124 is positively charged in the polishing solution environment, so that negatively charged contaminant particles are easily adsorbed.
Therefore, in this embodiment, after the polishing process, the wafer is cleaned by the cleaning method in the foregoing embodiment.
According to the embodiment, the cleaning method has good cleaning effect, and can effectively reduce the residual quantity of pollutant particles on the wafer, so that the cleaning effect meets the process requirement.
In the subsequent process, other functional layers covering the hard mask layer 125 are further formed, so that the probability of generating defects such as bumps (bumps) is low by reducing the residual number of contaminant particles on the wafer, thereby improving the performance and yield of the semiconductor structure.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A post-lapping cleaning method adapted to clean a lapped wafer to remove contaminant particles from the wafer surface, comprising:
performing a first cleaning process on the wafer, wherein the first cleaning process comprises a first sub-cleaning process, and the step of the first sub-cleaning process comprises the following steps: carrying out first flushing treatment by adopting megasonic deionized water and a first chemical cleaning agent; the first chemical cleaning agent comprises a surfactant and a corrosion inhibitor, wherein the surfactant is suitable for increasing the hydrophilicity of pollutant particles and the electric repulsive force between the pollutant particles and the surface of a wafer, and the corrosion inhibitor is used for reducing the corrosion of the first chemical cleaning agent to the surface of the wafer;
after the first cleaning process is executed, the wafer is dried; the first cleaning process further includes a second sub-cleaning process after the first sub-cleaning process, the step of the second sub-cleaning process including: adopting deionized water and a second chemical cleaning agent to carry out second flushing treatment;
The second chemical cleaning agent and the first chemical cleaning agent have the same components, and the mass percentage concentration of the second chemical cleaning agent is smaller than that of the first chemical cleaning agent.
2. The post-grind cleaning method according to claim 1, wherein the concentration of the first chemical cleaning agent is at least 5% by mass.
3. The post-grinding cleaning method according to claim 1, wherein the concentration of the first chemical cleaning agent is 5% to 30% by mass.
4. The post-grinding cleaning method according to claim 1, wherein the concentration of the second chemical cleaning agent is 5% to 20% of the concentration of the first chemical cleaning agent by mass.
5. The post-polish cleaning method according to claim 1, wherein in the step of the first sub-polish cleaning process, the treatment time of the first rinse treatment is 5 seconds to 20 seconds.
6. The post-polish cleaning method according to claim 1, wherein in the step of the second sub-polish cleaning process, the second rinse process has a process time of 5 seconds to 20 seconds.
7. The post-polish cleaning method of claim 1, wherein in said first sub-cleaning process step, said megasonic deionized water has a megasonic power of at least 40 watts.
8. The post-polish cleaning method of claim 1, wherein in the step of the first sub-polish process, the megasonic deionized water has a megasonic power of 40 watts to 200 watts.
9. The post-polish cleaning method of claim 1, wherein the step of the first sub-polish cleaning process further comprises: and after the first flushing treatment, adopting deionized water and the first chemical cleaning agent to carry out first brushing treatment.
10. The post-polish cleaning method of claim 9, wherein the step of the first sub-cleaning process further comprises: and after the first brushing treatment, adopting deionized water to carry out a second brushing treatment.
11. The post-polish cleaning method of claim 10, wherein the step of the first sub-cleaning process further comprises: and after the second scrubbing treatment, adopting deionized water to carry out first water scrubbing treatment.
12. The post-polish cleaning method of claim 1, wherein the step of the second sub-polish cleaning process further comprises: and after the second flushing treatment, adopting deionized water and the second chemical cleaning agent to carry out third brushing treatment.
13. The post-polish cleaning method according to claim 1, further comprising, after performing the first cleaning process, before performing the drying process: performing a second cleaning process on the wafer, the second cleaning process comprising: carrying out pre-washing treatment on the surface of the wafer by adopting a third chemical cleaning agent, wherein the third chemical cleaning agent and the first chemical cleaning agent have the same components, and the mass percentage concentration of the third chemical cleaning agent is smaller than that of the first chemical cleaning agent;
and after the pre-flushing treatment, scraping and washing the surface of the wafer by adopting the third chemical cleaning agent.
14. The post-grind cleaning method according to claim 13, wherein the step of wiping treatment includes: the pencil sponge brush is adopted to carry out scraping treatment from the center of the wafer to the edge of the wafer at a preset moving speed, and the preset moving speed of the pencil sponge brush is decreased gradually along the direction of the center of the wafer pointing to the edge of the wafer.
15. The post-grind cleaning method according to claim 14, wherein in the step of the scraping treatment, the pencil sponge brush has a preset rotational speed of 200RPM to 300RPM.
16. The post-polish cleaning method of claim 13, wherein the step of the second cleaning process further comprises: and after the scraping and washing treatment, carrying out gas cleaning treatment on the wafer.
17. The post-polish cleaning method according to claim 16, wherein the total flow rate of the gas used for the gas cleaning treatment is 200 standard liters per minute to 300 standard liters per minute.
18. A method of forming a semiconductor structure, comprising:
providing a wafer, wherein the wafer comprises a substrate, a metal gate structure is formed on the substrate, an interlayer dielectric layer is formed on the substrate exposed by the metal gate structure, the top of the interlayer dielectric layer is higher than the top of the metal gate structure, a groove is formed by the top of the metal gate structure and the interlayer dielectric layer in a surrounding mode, a hard mask material layer is formed in the groove, and the top of the interlayer dielectric layer is covered by the hard mask material layer;
grinding the hard mask material layer, wherein the residual hard mask material layer after the grinding is used as a hard mask layer;
after the polishing treatment, the wafer is cleaned using the cleaning method according to claims 1 to 17.
19. The method of claim 18, wherein the material of the hard mask layer is silicon nitride.
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