CN111863095B - Method and device for erasing NOR flash memory - Google Patents
Method and device for erasing NOR flash memory Download PDFInfo
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- CN111863095B CN111863095B CN201910357593.XA CN201910357593A CN111863095B CN 111863095 B CN111863095 B CN 111863095B CN 201910357593 A CN201910357593 A CN 201910357593A CN 111863095 B CN111863095 B CN 111863095B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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Abstract
The invention provides a method and a device for erasing a NOR flash memory. The method comprises the following steps: receiving a program pause instruction, temporarily stopping the progress of the program operation according to the program pause instruction, recording the address of the memory unit corresponding to the program operation through a control unit, receiving an erase operation instruction, judging whether the address of the memory unit needing to execute the erase operation contains the address of the memory unit corresponding to the program operation, and executing the erase operation on the memory unit needing to execute the erase operation if the address of the memory unit needing to execute the erase operation does not contain the address of the memory unit corresponding to the program operation. The method and the device realize that the NOR flash memory supports the temporary stop of the programming operation in the programming operation process to carry out the erasing operation, enrich the functions of the NOR flash memory, improve the use flexibility of the NOR flash memory, facilitate the technical development and popularization of the NOR flash memory, and improve the use feeling of users.
Description
Technical Field
The invention relates to the field of storage, in particular to a method and a device for erasing a NOR flash memory.
Background
At present, the application field of the NOR flash memory is more and more extensive, and the NOR is characterized in that the application program is executed in a chip, so that the application program can be directly operated in the NOR flash memory, codes do not need to be read into a system RAM, the transmission efficiency of the NOR flash memory is very high, and the NOR flash memory has very high cost benefit when the capacity is small, namely 1-4 MB.
Currently, for the NOR flash memory, some simple applications such as programming, erasing, reading have not been able to meet the requirements of the development of the NOR flash memory technology, and more complex applications are needed to be provided for the NOR flash memory, so that the NOR flash memory can be applied to a wider range.
At present, the NOR flash memory supports the temporary stop of programming operation in the process of programming operation to carry out reading operation. However, the erase operation cannot be performed during the program operation, that is, the NOR flash memory does not support the program operation to be temporarily stopped during the program operation to perform the erase operation, which limits the function of the NOR flash memory, is not favorable for the technical development and popularization of the NOR flash memory, and is not good for the user to use.
Disclosure of Invention
The method and the device for erasing the NOR flash memory solve the problem that the NOR flash memory does not support the temporary stop of the programming operation in the process of the programming operation so as to perform the erasing operation.
In order to solve the above technical problem, an embodiment of the present invention provides a NOR flash memory erasing method, where the method is applied to a NOR flash memory, and the NOR flash memory includes: a storage unit and a control unit, the method comprising:
receiving a pause programming instruction;
temporarily stopping the process of the programming operation according to the programming pause instruction;
recording the address of a storage unit corresponding to the programming operation through the control unit;
receiving an erasing operation instruction, wherein the erasing operation instruction comprises the following steps: the address of the memory cell required to perform the erase operation;
judging whether the address of the memory unit needing to execute the erasing operation contains the address of the memory unit corresponding to the programming operation;
and if the address of the memory unit needing to be subjected to the erasing operation does not contain the address of the memory unit corresponding to the programming operation, performing the erasing operation on the memory unit needing to be subjected to the erasing operation.
Optionally, after temporarily stopping the progress of the programming operation according to the program pause instruction, the method further includes:
recording, by the control unit, a programming field, which is a state in which programming is performed while the NOR flash memory programming operation is suspended, the programming field including:
the address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
Optionally, after determining whether the address of the memory cell that needs to perform the erase operation includes the address of the memory cell corresponding to the program operation, the method further includes:
and if the address of the memory unit needing to be subjected to the erasing operation comprises the address of the memory unit corresponding to the programming operation, not performing the erasing operation corresponding to the erasing operation instruction.
Optionally, after the erasing operation corresponding to the erasing operation instruction is not executed, the method further includes:
if a program resuming instruction is received, the program resuming instruction is an instruction for resuming the programming operation with respect to the program suspending instruction;
and according to the program resuming instruction and the programming site, resuming the programming operation corresponding to the programming operation instruction, wherein the programming site is a state in which the programming is performed when the programming operation of the NOR flash memory is suspended.
Optionally, after the erasing operation corresponding to the erasing operation instruction is not executed, the method further includes:
and if the program resuming instruction is not received, continuing to execute the program suspending instruction, and waiting for a next operation instruction, wherein the program resuming instruction is an instruction for resuming the program operation aiming at the program suspending instruction.
An embodiment of the present invention further provides a device for erasing a NOR flash memory, which is applied to the NOR flash memory, and the NOR flash memory includes: a storage unit and a control unit, the apparatus comprising:
the first receiving module is used for receiving a pause programming instruction;
the pause module is used for temporarily stopping the progress of the programming operation according to the pause programming instruction;
the recording module is used for recording the address of the storage unit corresponding to the programming operation through the control unit;
a second receiving module, configured to receive an erase operation instruction, where the erase operation instruction includes: the address of the memory cell required to perform the erase operation;
the judging module is used for judging whether the address of the memory unit which needs to execute the erasing operation comprises the address of the memory unit corresponding to the programming operation;
And the execution erasing module is used for executing the erasing operation on the memory unit which needs to execute the erasing operation if the address of the memory unit which needs to execute the erasing operation does not contain the address of the memory unit corresponding to the programming operation.
Optionally, the apparatus further comprises:
a recording field module for recording a programming field, which is a state of programming performed when the programming operation of the NOR flash memory is suspended, by the control unit, the programming field including:
the address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
Optionally, the executing and erasing module is further configured to:
and if the address of the memory unit needing to be subjected to the erasing operation comprises the address of the memory unit corresponding to the programming operation, not performing the erasing operation corresponding to the erasing operation instruction.
Optionally, the apparatus further comprises:
a third receiving module, configured to, if a program resuming instruction is received, resume the programming operation for the program pausing instruction;
and the recovery module is used for recovering the programming operation corresponding to the programming operation instruction according to the program recovery instruction and a programming site, wherein the programming site is a state of programming when the programming operation of the NOR flash memory is suspended.
Optionally, the apparatus further comprises:
and the continuous waiting module is used for continuously executing the program suspending instruction and waiting for the next operation instruction if the program resuming instruction is not received, wherein the program resuming instruction is an instruction for resuming the program operation aiming at the program suspending instruction.
Compared with the prior art, the method and the device for erasing the NOR flash memory provided by the invention have the advantages that in the programming operation process, the pause programming instruction is received, the programming operation process is temporarily stopped, the address of the memory unit corresponding to the programming operation is recorded, then the erasing operation instruction is received, whether the address of the memory unit needing to execute the erasing operation comprises the address of the memory unit corresponding to the programming operation or not is judged, and if the address of the memory unit needing to execute the erasing operation does not comprise the address of the memory unit corresponding to the programming operation, the erasing operation is executed on the memory unit needing to execute the erasing operation. The method and the device realize that the NOR flash memory supports the temporary stop of the programming operation in the programming operation process to carry out the erasing operation, enrich the functions of the NOR flash memory, improve the use flexibility of the NOR flash memory, facilitate the technical development and popularization of the NOR flash memory and improve the use feeling of users.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a flow chart of a NOR flash memory erase method according to an embodiment of the present invention;
FIG. 2 is another flow chart of the erase method after step 106 according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of an apparatus of an embodiment of the invention;
FIG. 4 is a block diagram of an apparatus for NOR flash memory erase in accordance with an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, during the use process of a NOR flash memory, the NOR flash memory is required to realize the functions of operations including but not limited to pure programming, reading, erasing and the like, for example, when a user programs the NOR flash memory, other operations may need to be executed urgently due to various factors, but due to the characteristics of the NOR flash memory, the NOR flash memory can only perform one operation, so that the next operation can be executed after the whole programming operation is finished, the time required for completing the programming operation is determined according to the size of the required writing quantity, if the data quantity required to be written in one programming operation is large, the time for completing the programming operation is long, and other operations need to be executed urgently, and only the programming operation can be executed after the programming operation is finished, so that many things can be delayed. If the NOR flash memory needs to suspend the programming operation to perform the erasing operation in the programming operation process, the erasing operation can only be performed after the whole programming operation is completed, the waiting time is long, and the use feeling of the NOR flash memory is not good. In order to solve the above problems, the present application proposes a NOR flash memory erase method, which is explained and illustrated below.
Fig. 1 is a flowchart illustrating a NOR flash memory erase method according to an embodiment of the present invention. The method is applied to a NOR flash memory, and the NOR flash memory comprises the following steps: the erasing method comprises the following steps:
step 101: a pause programming instruction is received.
In an embodiment of the present invention, a NOR flash memory includes: the device comprises a storage unit and a control unit, wherein the control unit is used for recording the state of programming in the NOR flash memory when the programming is suspended. When the program operation needs to be temporarily stopped, the upper computer is first required to send a program pause instruction, and the NOR flash memory receives the program pause instruction.
Step 102: according to the program pause instruction, the process of the programming operation is temporarily stopped.
In the embodiment of the invention, after the NOR flash memory receives the instruction for suspending programming, the instruction is executed, and the process of programming operation is temporarily stopped. It should be noted that, it is assumed that only the instruction for suspending programming may temporarily stop the programming operation during the programming operation of the NOR flash memory, and if the NOR flash memory receives any other instruction, such as an erase operation instruction, a read operation instruction, etc., during the programming operation, the NOR flash memory does not temporarily stop or directly stop the programming operation, but continues the programming operation.
Optionally, after step 102, the erasing method further includes:
recording a programming field by a control unit, wherein the programming field is a state of programming when the programming operation of the NOR flash memory is suspended, and the programming field comprises:
the address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
In the embodiment of the invention, after the NOR flash memory temporarily stops the process of the programming operation, the state of the programming process when the NOR flash memory stops the programming operation is recorded by the control unit, and the programming field comprises: the address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles, where the address of the memory cell corresponding to the programming operation is recorded according to a rule of the NOR flash memory itself, for example, when the NOR flash memory temporarily stops the programming operation, a start address and a final address of all memory cells in which data is required to be written in the programming operation may be recorded, or only a start address or a final address of all memory cells in which data is required to be written in the programming operation may be recorded separately, or an address of a memory cell in which data is finally written in the programming operation when the programming operation temporarily stops is recorded separately. The data to be programmed is data which needs to be written into the memory cell in the programming operation, and when the NOR flash memory temporarily stops the programming operation, the data which is not written into the memory cell is recorded, so that when the subsequent programming operation is recovered again, the data which is not written into the memory cell is continuously written into the corresponding memory cell. The program loop number is the number of loops required for the NOR flash memory to perform the program verify operation and the program stress operation in order to complete the entire program operation.
Step 103: and recording the address of the memory cell corresponding to the programming operation through the control unit.
In the embodiment of the invention, when the NOR flash memory temporarily stops the programming operation, the address of the storage unit corresponding to the programming operation is recorded by the control unit. How to record the address of the memory cell corresponding to the programming operation is explained above, and is not described herein again. The recording of the address of the memory cell corresponding to the programming operation is to determine whether the erasing operation can be performed by combining the address of the memory cell corresponding to the subsequent erasing operation.
Step 104: receiving an erasing operation instruction, wherein the erasing operation instruction comprises the following steps: the address of the memory cell required to perform the erase operation.
In the embodiment of the invention, after the control unit records a programming field, the NOR flash memory receives an erasing operation instruction, and the erasing operation instruction comprises the following steps: the address of the memory cell required to perform the erase operation. In the NOR flash memory, the erase operation is performed in units of blocks, and the program operation is performed in units of pages, where a block includes a plurality of pages, and the address of a memory cell required to perform the erase operation is the address of a block, including the start address to the end address of the block.
Step 105: and judging whether the address of the memory cell needing to execute the erasing operation comprises the address of the memory cell corresponding to the programming operation.
In the embodiment of the present invention, after the NOR flash memory receives the instruction of the erase operation, it is necessary to determine whether the address of the memory cell that needs to perform the erase operation includes the address of the memory cell corresponding to the program operation. Because the address range of the memory cell corresponding to the erase operation is larger than the address of the memory cell corresponding to the program operation, the address of the memory cell corresponding to the program operation may fall within the address range of the memory cell required to perform the erase operation, or the address of the memory cell corresponding to the program operation may not fall within the address range of the memory cell required to perform the erase operation. It should be noted that if the NOR flash memory does not receive the erase command during the program suspension process, the NOR flash memory continues the program operation and does not respond to the erase command.
Step 106: and if the address of the memory unit needing to be subjected to the erasing operation does not contain the address of the memory unit corresponding to the programming operation, performing the erasing operation on the memory unit needing to be subjected to the erasing operation.
In the embodiment of the invention, if the judgment result is: the address of the memory cell required to perform the erase operation does not include the address of the memory cell corresponding to the program operation, such as: the addresses of the memory cells required to perform an erase operation are: 0000H to 0FFFH, and if the address of the memory cell corresponding to the program operation is not within the address range of 0000H to 0FFFH, the erase operation is performed on the memory cell that needs to perform the erase operation, i.e. the memory cell of 0000H to 0 FFFH. If the judgment result is: the address of the memory cell required to perform the erase operation includes the address of the memory cell corresponding to the program operation, for example: the addresses of the memory cells required to perform an erase operation are: 0000H to 0FFFH, and the address of the memory cell corresponding to the program operation is within the address range of 0000H to 0FFFH, the erase operation corresponding to the command of the erase operation is not performed, i.e. the erase operation is not performed on the memory cells of addresses 0000H to 0 FFFH.
Optionally, referring to fig. 2, after the address of the memory cell required to perform the erase operation includes the address of the memory cell corresponding to the program operation and the erase operation corresponding to the instruction not performing the erase operation, the erase method further includes:
Step 107: if the program resuming instruction is received, the program resuming instruction is an instruction for resuming the programming operation with respect to the program suspending instruction.
In the embodiment of the invention, after the NOR flash memory does not execute the erasing operation corresponding to the erasing operation instruction, if the program resuming instruction is received, the programming operation corresponding to the programming operation instruction needs to be resumed.
Step 108: and according to the program resuming instruction and the programming site, resuming the programming operation corresponding to the programming operation instruction, wherein the programming site is a state in which the programming is performed when the programming operation of the NOR flash memory is suspended.
In the embodiment of the invention, the programming operation corresponding to the instruction for resuming the programming operation needs to be resumed according to the instruction for resuming the programming operation and the programming field, because the programming field records the address of the memory unit corresponding to the programming operation, the data to be programmed and the programming cycle number when the programming operation of the NOR flash memory is suspended, and when the programming operation is resumed again, the incomplete programming operation can be correctly continued according to the records.
Step 109: and if the program resuming instruction is not received, continuing to execute the program suspending instruction, waiting for the next operation instruction, and resuming the program as the instruction for resuming the program operation aiming at the program suspending instruction.
In the embodiment of the invention, after the NOR flash memory does not execute the erasing operation corresponding to the instruction of the erasing operation, if the program resuming instruction is not received, the program suspending instruction is continuously executed, namely, the state of the program suspending operation is continuously maintained, the next operation instruction is waited, if the next operation instruction is still the erasing operation instruction, the steps 105 and 106 are repeated; and if the next operation instruction is a read operation instruction, executing the read operation corresponding to the read operation instruction. Of course, when the NOR flash memory continues to maintain the state of suspending the programming operation, the resume program instruction is received and executed according to steps 107 and 108.
Referring to fig. 3, which shows a device schematic diagram of an embodiment of the present invention, a NOR flash memory includes: a storage unit and a control unit. The upper computer is connected with the NOR flash memory and used for sending various instructions to the NOR flash memory.
In the process of programming the NOR flash memory, if the erasing operation is needed, firstly, an instruction for pausing the programming is sent to the NOR flash memory through the upper computer, and after the instruction for pausing the programming is received by the NOR flash memory, the instruction is executed, and the progress of the programming operation is temporarily stopped. Recording the programming site by the control unit, comprising: address of memory cell to which data is finally written when the program operation is suspended: 1128H; the data to be programmed not written to the memory cell and the number of programming cycles 10.
Sending an instruction of an erasing operation to the NOR flash memory through the upper computer, wherein the instruction of the erasing operation comprises: address of memory cell required to perform erase operation: 0000H to 0FFFH, after the NOR flash memory receives the instruction of the erase operation, determining that the addresses 0000H to 0FFFH of the memory cells required to execute the erase operation do not include the addresses of the memory cells corresponding to the program operation: 1128H, an erase operation is performed on the memory cells at addresses 0000H-0 FFFH.
If the process of the programming operation is temporarily stopped, the programming site is recorded by the control unit, and the address of the memory unit which is written with data finally when the programming operation is suspended: 0128H, sending an instruction of erasing operation to the NOR flash memory through the upper computer, the instruction of erasing operation includes: address of memory cell required to perform erase operation: 0000H to 0FFFH, after the NOR flash memory receives the instruction of the erase operation, judging that the addresses 0000H to 0FFFH of the memory cells needing to execute the erase operation contain the addresses of the memory cells corresponding to the program operation: 0128H, no erase operation is performed to the memory cells at addresses 0000H 0 FFFH. At this time, the NOR flash memory maintains the state of the program operation being suspended, and then if the NOR flash memory receives the resume program instruction, according to the address of the memory cell to which data is last written when the program operation is suspended: 0128H, data to be programmed not written in the memory cell and the number of program cycles 10, and continuing to execute the incomplete program operation. If the NOR flash memory receives another erase operation command while the NOR flash memory maintains a state of suspending a program operation, the erase operation command includes: address of memory cell required to perform erase operation: 1000H to 1FFFH, determining that the addresses of the memory cells requiring the erase operation 1000H to 1FFFH do not include the address of the memory cell corresponding to the program operation: 0128H, and performing erasing operation on the memory cells with addresses 1000H-1 FFFH.
Referring to fig. 4, an embodiment of the present invention further provides an apparatus for erasing a NOR flash memory, where the apparatus is applied to the NOR flash memory, and the NOR flash memory includes: a memory unit and a control unit, the erasing device comprises:
a first receiving module 310, configured to receive a pause programming instruction;
a pause module 320, configured to temporarily stop the process of the programming operation according to the pause programming instruction;
a recording module 330, configured to record, by the control unit, an address of a memory cell corresponding to the programming operation;
the second receiving module 340 is configured to receive an erase operation instruction, where the erase operation instruction includes: the address of the memory cell required to perform the erase operation;
a determining module 350, configured to determine whether an address of a memory cell that needs to perform an erase operation includes an address of a memory cell corresponding to a program operation;
the erase execution module 360 is configured to, if the address of the memory cell that needs to be erased does not include the address of the memory cell corresponding to the program operation, perform an erase operation on the memory cell that needs to be erased.
Optionally, the erasing device further comprises:
a recording field module 370 for recording a programming field, which is a state of programming performed when the NOR flash memory programming operation is suspended, by the control unit, the programming field including:
The address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
Optionally, the erasing module 360 is further configured to:
and if the address of the memory unit needing to be subjected to the erasing operation comprises the address of the memory unit corresponding to the programming operation, not performing the erasing operation corresponding to the erasing operation instruction.
Optionally, the erasing device further comprises:
a third receiving module 380, configured to, if a program resuming instruction is received, resume the programming instruction as an instruction for resuming the programming operation with respect to the suspended programming instruction;
the resuming module 390 is configured to resume the programming operation corresponding to the programming operation instruction according to the resuming programming instruction and the programming site, where the programming site is a state where the programming is performed when the programming operation of the NOR flash memory is suspended.
The wait continuing module 400 is configured to continue to execute the program suspending instruction if the program resuming instruction is not received, and wait for a next operation instruction, where the program resuming instruction is an instruction for resuming the program operation with respect to the program suspending instruction.
Through the embodiment, in the process of the programming operation, the invention receives the program pause instruction, temporarily stops the process of the programming operation, records the address of the memory unit corresponding to the programming operation, the data to be programmed and the programming cycle number, then receives the erase operation instruction, judges whether the address of the memory unit needing to execute the erase operation contains the address of the memory unit corresponding to the programming operation, executes the erase operation on the memory unit needing to execute the erase operation if the address of the memory unit needing to execute the erase operation does not contain the address of the memory unit corresponding to the programming operation, and does not execute the erase operation corresponding to the instruction of the erase operation if the address of the memory unit needing to execute the erase operation contains the address of the memory unit corresponding to the programming operation. And after the erasing operation corresponding to the instruction without executing the erasing operation, according to the program resuming instruction and the programming field, resuming the programming operation corresponding to the program operating instruction, or continuing to execute the program suspending instruction and waiting for the next operating instruction. The method and the device realize that the NOR flash memory supports the temporary stop of the programming operation in the programming operation process to carry out the erasing operation, enrich the functions of the NOR flash memory, improve the use flexibility of the NOR flash memory, facilitate the technical development and popularization of the NOR flash memory, and improve the use feeling of users.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the particular illustrative embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and equivalents thereof, which may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for erasing a NOR flash memory, wherein the method is applied to the NOR flash memory, and the NOR flash memory comprises the following steps: a storage unit and a control unit, the method comprising:
receiving a pause programming instruction;
temporarily stopping the process of the programming operation according to the programming pause instruction;
recording the address of a storage unit corresponding to the programming operation through the control unit;
receiving an erasing operation instruction, wherein the erasing operation instruction comprises the following steps: the address of the memory cell required to perform the erase operation;
judging whether the address of the memory unit needing to execute the erasing operation contains the address of the memory unit corresponding to the programming operation;
and if the address of the memory unit needing to be subjected to the erasing operation does not contain the address of the memory unit corresponding to the programming operation, performing the erasing operation on the memory unit needing to be subjected to the erasing operation.
2. The method of claim 1, wherein after temporarily stopping the progress of the programming operation according to the suspend programming instruction, the method further comprises:
recording, by the control unit, a programming field, which is a state in which programming is performed while the NOR flash memory programming operation is suspended, the programming field including:
The address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
3. The method of claim 1, wherein after determining whether the address of the memory cell required to perform the erase operation includes the address of the memory cell corresponding to the program operation, the method further comprises:
and if the address of the memory cell needing to be subjected to the erasing operation comprises the address of the memory cell corresponding to the programming operation, not performing the erasing operation corresponding to the erasing operation instruction.
4. The method of claim 3, wherein after the erase operation corresponding to the erase operation instruction is not executed, the method further comprises:
if a program resuming instruction is received, the program resuming instruction is an instruction for resuming the programming operation aiming at the program suspending instruction;
and according to the program resuming instruction and the programming site, resuming the programming operation corresponding to the programming operation instruction, wherein the programming site is a state in which the programming is performed when the programming operation of the NOR flash memory is suspended.
5. The method of claim 3, wherein after the erase operation corresponding to the erase operation instruction is not executed, the method further comprises:
And if the program resuming instruction is not received, continuing to execute the program suspending instruction, and waiting for a next operation instruction, wherein the program resuming instruction is an instruction for resuming the program operation aiming at the program suspending instruction.
6. An apparatus for erasing a NOR flash memory, the apparatus being applied to a NOR flash memory, the NOR flash memory comprising: a storage unit and a control unit, the apparatus comprising:
the first receiving module is used for receiving a pause programming instruction;
the pause module is used for temporarily stopping the progress of the programming operation according to the pause programming instruction;
the recording module is used for recording the address of the storage unit corresponding to the programming operation through the control unit;
a second receiving module, configured to receive an erase operation instruction, where the erase operation instruction includes: the address of the memory cell required to perform the erase operation;
the judging module is used for judging whether the address of the memory unit which needs to execute the erasing operation comprises the address of the memory unit corresponding to the programming operation;
and the execution erasing module is used for executing the erasing operation on the memory unit which needs to execute the erasing operation if the address of the memory unit which needs to execute the erasing operation does not contain the address of the memory unit corresponding to the programming operation.
7. The apparatus of claim 6, further comprising:
a recording field module for recording a programming field, which is a state of programming performed when the programming operation of the NOR flash memory is suspended, by the control unit, the programming field including:
the address of the memory cell corresponding to the programming operation, the data to be programmed, and the number of programming cycles.
8. The apparatus of claim 6, wherein the execute erase module is further configured to:
and if the address of the memory cell needing to be subjected to the erasing operation comprises the address of the memory cell corresponding to the programming operation, not performing the erasing operation corresponding to the erasing operation instruction.
9. The apparatus of claim 8, further comprising:
a third receiving module, configured to, if a program resuming instruction is received, resume the programming operation for the program pausing instruction;
and the recovery module is used for recovering the programming operation corresponding to the programming operation instruction according to the program recovery instruction and a programming site, wherein the programming site is a state of programming when the programming operation of the NOR flash memory is suspended.
10. The apparatus of claim 8, further comprising:
and the continuous waiting module is used for continuously executing the program suspending instruction and waiting for the next operation instruction if the program resuming instruction is not received, wherein the program resuming instruction is an instruction for resuming the program operation aiming at the program suspending instruction.
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| JP2003123488A (en) * | 2001-10-11 | 2003-04-25 | Toshiba Corp | Semiconductor memory |
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| CN105161129A (en) * | 2011-07-14 | 2015-12-16 | 株式会社东芝 | Non-volatile semiconductor memory device and memory system |
| CN107112047A (en) * | 2015-01-23 | 2017-08-29 | 桑迪士克科技有限责任公司 | Partial Block for block program in the nonvolatile memory is wiped |
| CN108713184A (en) * | 2016-03-30 | 2018-10-26 | 英特尔公司 | The method and apparatus that erasing pausing operation is executed in memory device |
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