CN111860794A - Processing device, processing method and neural network classifier - Google Patents
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Abstract
The present disclosure provides a processing apparatus, a processing method, and a neural network classifier. The processing equipment comprises an input voltage compensation device and a resistance change intersection array. The input voltage compensation device is configured to compensate a plurality of input first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and apply the plurality of second voltage signals to the resistive switching cross point array. The resistance change cross point array includes a plurality of bit lines, a plurality of word lines, and a plurality of resistance change cells, and is configured to derive a plurality of first current signals based on a plurality of second voltage signals applied to the plurality of word lines and the plurality of resistance change cells. The processing equipment can avoid the distortion of matrix operation results under the influence of wire parasitic resistance and potential leakage path problems, and the distortion of neural network inference results caused by the distortion.
Description
Technical Field
The present disclosure relates to a processing apparatus, a processing method, and a neural network classifier.
Background
Deep neural network technology has made significant advances in various fields such as image recognition, speech recognition, and natural language processing. In the process of deducing and training the deep neural network, by means of mapping matrix elements into the conductance values of the resistance change cross point array, vector-matrix multiplication can be efficiently realized through the resistance change cross point array, and therefore the process of deducing and training the deep neural network can be greatly accelerated. Specifically, parallel input voltage is applied to the resistive switching cross point array, and output current is the result of corresponding vector-matrix multiplication operation by using ohm's law and kirchhoff's law.
However, in a brain-like computing system taking a resistive switching cross point array as a core, the scale of the resistive switching cross point array is related to the hardware overhead of the system. The smaller the scale of the resistive cross point array is, the larger the overhead of a digital-to-analog conversion circuit and an analog-to-digital conversion circuit required by the system is. Under the influence of wire parasitic resistance and sneak path problem (sneak path problem), the resistive cross point array is distorted when calculating vector-matrix multiplication. The larger the scale of the resistive switching cross point array is, the more obvious the distortion is.
Disclosure of Invention
At least one embodiment of the present disclosure provides a processing device. The processing equipment comprises an input voltage compensation device and a resistance change intersection array. The input voltage compensation device is configured to compensate a plurality of input first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and apply the plurality of second voltage signals to the resistive switching cross point array. The resistance change cross point array includes a plurality of bit lines, a plurality of word lines, and a plurality of resistance change cells, the plurality of resistance change cells form an array having a size of m × n, m and n are integers greater than 1, and the resistance change cross point array is configured to obtain a plurality of first current signals based on a plurality of second voltage signals applied to the plurality of word lines and the plurality of resistance change cells.
For example, according to an embodiment of the present disclosure, there is provided a processing apparatus, further including an output current compensation device. The output current compensation device is configured to compensate the plurality of first current signals by using a plurality of second compensation factors to obtain a plurality of second current signals.
For example, according to an embodiment of the present disclosure, there is provided a processing apparatus in which each of a plurality of first compensation factors is determined according to an equivalent circuit of a resistance change crossbar array without considering parasitic resistances on a plurality of word lines.
For example, in a processing apparatus provided according to an embodiment of the present disclosure, the processing apparatus further includes a first compensation factor determining device configured to determine a first compensation factor 1/a of the first voltage signal for the ith row among the plurality of first compensation factors according to the following equationi：
In the above formula, i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
For example, in a processing device provided according to an embodiment of the present disclosure, the processing device further includes a first compensation factor determination device configured to: applying the plurality of first voltage signals to the resistive switching cross point array, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after the plurality of first voltage signals are applied; obtaining a conductance value of each row of resistance change units in a first column of resistance change units from the resistance change cross point array; and taking the ratio of the conductance value of the resistive unit of the ith row in the resistive units of the first column to the value of the first column output current in the uncompensated output currents as a first compensation factor of the first voltage signal corresponding to the resistive unit of the ith row, wherein i is an integer greater than or equal to 1 and less than or equal to m.
For example, according to an embodiment of the present disclosure, there is provided a processing apparatus, wherein the input voltage compensation device is configured to adjust at least one of an amplitude, a pulse width, and a number of pulses of the plurality of first voltage signals according to a plurality of first compensation factors.
For example, according to an embodiment of the present disclosure, there is provided a processing apparatus in which each of a plurality of second compensation factors is determined according to an equivalent circuit of a resistance change crossbar array without considering parasitic resistances on a plurality of bit lines.
For example, in a processing apparatus provided according to an embodiment of the present disclosure, the processing apparatus further includes a second compensation factor determining device configured to determine a second compensation factor 1/b of the plurality of second compensation factors for the first current signal of the jth column according to the following equationj：
In the above formula, j is an integer of 1 to n, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
For example, according to an embodiment of the disclosure, a processing apparatus is provided, in which the processing apparatus further includes a second compensation factor determination device. The second compensation factor determination means is configured to: applying the plurality of first voltage signals to the resistive switching cross point array, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after the plurality of first voltage signals are applied; obtaining the conductance value of each row of resistance change units in the mth row of resistance change units from the resistance change cross point array; and taking the ratio of the conductance value of the resistive switching unit at the jth column in the resistive switching units at the mth row to the value of the output current at the jth column in the uncompensated output currents as a second compensation factor of the first current signal corresponding to the resistive switching unit at the jth column, wherein j is an integer which is greater than or equal to 1 and less than or equal to n.
For example, according to an embodiment of the present disclosure, there is provided a processing apparatus in which the output current compensation device includes at least one of an amplification circuit and an integration circuit.
At least one embodiment of the present disclosure also provides a neural network classifier. The neural network classifier comprises any one of the processing devices described previously.
At least one embodiment of the present disclosure further provides a processing method. The processing method comprises the following steps: the method comprises the steps of compensating a plurality of input first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and applying the plurality of second voltage signals to a resistance change cross point array, wherein the resistance change cross point array comprises a plurality of bit lines, a plurality of word lines and a plurality of resistance change units, the plurality of resistance change units form an array with the size of m multiplied by n, and m and n are integers more than 1; and obtaining a plurality of first current signals based on a plurality of second voltage signals applied to a plurality of word lines of the resistive switching cross point array and the plurality of resistive switching cells.
For example, a processing method according to an embodiment of the present disclosure further includes compensating the plurality of first current signals by using a plurality of second compensation factors to obtain a plurality of second current signals.
For example, according to an embodiment of the disclosure, a processing method is provided in which each of a plurality of first compensation factors is determined according to an equivalent circuit of a resistive switching crossbar array without considering parasitic resistances on a plurality of word lines, and the method further includes determining a first compensation factor 1/a of the plurality of first compensation factors for a first voltage signal of an ith row according to the following equationi：
In the above formula, i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
For example, the processing method provided according to an embodiment of the present disclosure further includes determining a plurality of first compensation factors, where determining the plurality of first compensation factors includes: applying the plurality of first voltage signals to the resistive switching cross point array, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after the plurality of first voltage signals are applied; obtaining a conductance value of each row of resistance change units in a first column of resistance change units from the resistance change cross point array; and taking the ratio of the conductance value of the resistive unit of the ith row in the resistive units of the first column to the value of the first column output current in the uncompensated output currents as a first compensation factor of the first voltage signal corresponding to the resistive unit of the ith row, wherein i is an integer greater than or equal to 1 and less than or equal to m.
For example, a processing method provided according to an embodiment of the present disclosure is one in which each of a plurality of second compensation factors is determined according to an equivalent circuit of the resistive switching crossbar array without considering parasitic resistances on a plurality of bit lines, and the method further includes determining a second compensation factor 1/b of the plurality of second compensation factors for the first current signal of the j-th column according to the following equationj：
In the above formula, j is an integer of 1 to n, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
For example, the processing method provided according to an embodiment of the present disclosure further includes determining a plurality of second compensation factors, where determining the plurality of second compensation factors includes: applying the plurality of first voltage signals to the resistive switching cross point array, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after the plurality of first voltage signals are applied; obtaining the conductance value of each row of resistance change units in the mth row of resistance change units from the resistance change cross point array; and taking the ratio of the conductance value of the resistive switching unit at the jth column in the resistive switching units at the mth row to the value of the output current at the jth column in the uncompensated output currents as a second compensation factor of the first current signal corresponding to the resistive switching unit at the jth column, wherein j is an integer which is greater than or equal to 1 and less than or equal to n.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is to be expressly understood that the drawings described below are directed to only some embodiments of the disclosure and are not intended as a definition of the limits of the disclosure.
Fig. 1 shows a schematic structural diagram of a processing device according to an exemplary embodiment of the present disclosure.
Fig. 2 shows a schematic structural diagram of a processing device according to an exemplary embodiment of the present disclosure.
Fig. 3 shows a schematic structural diagram of a processing device according to an exemplary embodiment of the present disclosure.
Fig. 4 shows a schematic structural diagram of a processing device according to an exemplary embodiment of the present disclosure.
Fig. 5A illustrates a schematic structural diagram of a resistive switching cross-point array with wire parasitic resistance according to an exemplary embodiment of the present disclosure.
Fig. 5B shows a schematic diagram of a resistive switching cross-point array without considering parasitic resistance on word lines, according to an example embodiment of the present disclosure.
Fig. 5C shows a schematic diagram of a resistive switching cross-point array without considering parasitic resistance on word lines, according to an example embodiment of the present disclosure.
Fig. 6 shows a schematic structural diagram of a neural network classifier according to an exemplary embodiment of the present disclosure.
Fig. 7 shows a flow chart of a processing method according to an exemplary embodiment of the present disclosure.
Fig. 8 shows a flow chart of a processing method according to an exemplary embodiment of the present disclosure.
Fig. 9A and 9B are schematic diagrams illustrating distortion of resistance change cross point arrays of different sizes when vector-matrix multiplication is implemented.
Fig. 10 illustrates an accuracy diagram of classification results obtained by applying a processing device and/or a processing method according to an exemplary implementation of the present disclosure to a neural network classifier or a neural network classification method.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
The terminology used herein to describe embodiments of the invention is not intended to limit and/or define the scope of the invention.
For example, unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention belongs.
It should be understood that the use of "first," "second," and similar terms in the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The singular forms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one, unless the context clearly dictates otherwise.
It will be further understood that the terms "comprises" or "comprising," and the like, mean that the element or item identified as preceding the term, includes the element or item identified as following the term, and equivalents thereof, without excluding other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The schemes for solving the operational distortion problem can be roughly divided into two kinds. One scheme is to adjust the conductance value of the resistive cross point array, for example, iteratively adjust the conductance value of the resistive cross point array with the parasitic wire resistance to make the output current approach the result of vector-matrix multiplication, or introduce the parasitic wire resistance effect in the forward inference process of training the deep neural network, so that the parasitic wire resistance effect becomes a part of the network characteristics. However, the implementation of this scheme requires a large number of iterative computations, when the array scale or the neural network scale reaches a certain degree, the computational resources that need to be consumed will be unacceptable, and the scheme only introduces the wire parasitic resistance effect in the forward inference process of training the deep neural network, and the convergence of the training cannot be guaranteed. Another approach is to apply a different compensation factor on each column output current. However, in this scheme, the calculation of the compensation factor requires artificial adjustment of the hyper-parameter according to the size of the array and the learning process of the deep neural network, and is difficult to realize by a simple circuit.
At least one embodiment of the present disclosure provides a processing apparatus including an input voltage compensation device, a resistive switching cross point array, and an output current compensation device, wherein the input voltage compensation device is configured to compensate the input plurality of first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and applying the plurality of second voltage signals to a resistive cross point array, the resistive cross point array including a plurality of bit lines, a plurality of word lines, and a plurality of resistive cells forming an array having a size of m × n, m and n each being an integer greater than 1, the resistive cross point array being configured to obtain a plurality of first current signals based on the plurality of second voltage signals applied to the plurality of word lines and the plurality of resistive cells, and the output current compensation device is configured to compensate the plurality of first current signals by using a plurality of second compensation factors to obtain a plurality of second current signals.
At least one embodiment of the present disclosure also provides a neural network classifier including the processing device as described above.
At least one embodiment of the present disclosure further provides a processing method, including: the method comprises the steps of compensating a plurality of input first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and applying the plurality of second voltage signals to a resistance change cross point array, wherein the resistance change cross point array comprises a plurality of bit lines, a plurality of word lines and a plurality of resistance change units, the plurality of resistance change units form an array with the size of m multiplied by n, and m and n are integers more than 1; obtaining a plurality of first current signals based on a plurality of second voltage signals applied to a plurality of word lines of the resistive switching cross point array and a plurality of resistive switching cells; and compensating the plurality of first current signals by using a plurality of second compensation factors to obtain a plurality of second current signals.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.
Fig. 1 shows a schematic view of a processing device according to an exemplary embodiment of the present disclosure.
Referring to fig. 1, a processing apparatus 1 according to an exemplary embodiment of the present disclosure may include an input voltage compensation device 11 and a resistive switching cross point array 12.
For example, in some embodiments, the input voltage compensation device 11 may be configured to compensate the input plurality of first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and apply the plurality of second voltage signals to the resistive switching cross point array. The voltage signal to be applied to the resistive switching cross point array 12 can be compensated by the input voltage compensation device 11 to obtain a compensated voltage signal.
For example, the input voltage compensation device 11 may be configured to adjust at least one of the amplitude, the pulse width and the number of pulses of the plurality of first voltage signals according to the plurality of first compensation factors to compensate the input plurality of first voltage signals. For example, when applying the embodiments of the present disclosure to a brain-like computing system, the implementation of the input voltage compensation device 11 may consider the specific design of the brain-like computing system. Thus, embodiments of the present disclosure may avoid distortion of the matrix operation results, and thus the neural network inference results, subject to wire parasitic resistance and sneak path problems.
For example, in some embodiments, the resistive switching cross point array 12 may include a plurality of bit lines, a plurality of word lines, and a plurality of resistive switching cells, where the plurality of resistive switching cells may form an array having a size of m × n, where m and n are integers greater than 1. The resistive switching cross point array 12 may be configured to derive a plurality of first current signals based on a plurality of second voltage signals applied to a plurality of word lines and a plurality of resistive switching cells. In some embodiments, the resistive switching cells in the resistive switching cross point array 12 may be a 1T1R structure including one Transistor (Transistor) and one resistive switching memory (RRAM). For example, the resistive random access memory may be composed of upper and lower electrodes and a resistive medium interposed therebetween, and may be gradually switched between a low resistance state (LRS or ON state) and a high resistance state (HRS or OFF state) by voltage or current excitation. In some embodiments, the upper and lower electrodes of the resistive random access memory are respectively connected to a word line and a bit line, and applying a forward voltage excitation to the word line can increase the conductance of the resistive random access memory, and applying a forward voltage excitation to the bit line can decrease the conductance of the resistive random access memory. However, the structure of the resistance change cell in the present disclosure is not limited thereto. In some embodiments, the resistive switching memory in the resistive switching cell may be a memristor, however, the type of resistance of the resistive switching cell in the present disclosure is not limited thereto.
For example, each of the plurality of first compensation factors may be determined according to the resistance of the resistive switching cell on the corresponding word line and the parasitic resistance distributed on one bit line of the resistive switching cross point array 12. For example, the compensation factor may be obtained by a model analysis or the like.
As shown in fig. 2, in a further example, the processing device 1 may further comprise first compensation factor determining means 13.
In some embodiments, for example, the first compensation factor determining means 13 may be configured to determine the first compensation factor 1/a of the plurality of first compensation factors for the first voltage signal of the ith row according to equation (1)i。
[ formula (1) ]
In the formula (1), i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
Can replaceAlternatively, in some embodiments, the first compensation factor determining means 13 may be configured to: a plurality of first voltage signals (V)1,V2,…,Vi,…,Vm) Is directly applied to the resistive switching cross point array 12, and obtains a plurality of first voltage signals (V) applied from the resistive switching cross point array 121,V2,…,Vi,…,Vm) The latter plurality of uncompensated output currents; obtaining a conductance value of each row of resistive random access units in the first column of resistive random access units from the resistive random access cross point array 12; and taking the ratio of the conductance value of the resistive unit of the ith row in the resistive units of the first column to the value of the first column output current in the uncompensated output currents as a first compensation factor of the first voltage signal corresponding to the resistive unit of the ith row, wherein i is an integer greater than or equal to 1 and less than or equal to m.
As shown in fig. 3, in a further example, the processing device 1 may further comprise an output current compensation means 14. For example, the output current compensation device 14 may be configured to compensate the plurality of first current signals output by the resistive switching cross point array 12 by using a plurality of second compensation factors to obtain a plurality of second current signals. The current signal output from the resistive cross point array 12 can be compensated by the input voltage compensation device 11. By compensating the plurality of input first voltage signals and compensating the plurality of first current signals output by the resistive switching cross point array 12, the plurality of second current signals may represent multiplication (i.e., vector-matrix multiplication) between a vector composed of the plurality of input first voltage signals and a matrix composed of conductance values of the plurality of resistive switching cells in the resistive switching cross point array 12.
For example, the output current compensation device 4 may include at least one of an amplification circuit and an integration circuit to compensate for the plurality of first current signals output by the resistive switching cross point array 12 using the plurality of second compensation factors. For example, when applying embodiments of the present disclosure to a brain-like computing system, the implementation of the output current compensation device 14 may take into account the specific design of the brain-like computing system.
As shown in fig. 4, in a further example, the processing device 1 may further comprise second compensation factor determining means 15.
In some embodiments, for example, the second compensation factor determining device 15 may be configured to determine the second compensation factor 1/b of the plurality of second compensation factors for the first current signal of the jth column according to equation (2)j。
[ formula (2) ]
In the formula (2), j is an integer of 1 to n, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
Alternatively, in some embodiments, the second compensation factor determining means 15 may be configured to: a plurality of first voltage signals (V)1,V2,…,Vi,…,Vm) Is applied to the resistive switching cross point array 12, and obtains a plurality of first voltage signals (V) applied from the resistive switching cross point array 121,V2,…,Vi,…,Vm) The latter plurality of uncompensated output currents; obtaining a conductance value of each row of resistance change units in the mth row of resistance change units from the resistance change cross point array 12; and taking the ratio of the conductance value of the resistive switching unit at the jth column in the resistive switching units at the mth row to the value of the output current at the jth column in the uncompensated output currents as a second compensation factor of the first current signal corresponding to the resistive switching unit at the jth column, wherein j is an integer which is greater than or equal to 1 and less than or equal to n.
In some embodiments, for example, the first compensation factor determining means 14 and the second compensation factor determining means 15 may be implemented by a programmable processor, a computer, a system on a chip, a special-purpose logic circuit such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or the like, or a plurality or combination of the foregoing. For example, the first compensation factor determining means 14 and the second compensation factor determining means 14 may be implemented by hardware, firmware or software, and any combination thereof.
It is to be noted that, although the above shows an example in which the processing apparatus 1 includes the voltage compensation device, and an example in which the processing apparatus includes both the voltage compensation device and the current compensation device. However, embodiments of the present disclosure are not limited thereto. For example, the processing device may comprise current compensation means and not voltage compensation means. In this case, the embodiments of the present disclosure can still avoid the distortion of the matrix operation result and the distortion of the neural network inference result caused by the distortion of the matrix operation result affected by the wire parasitic resistance and the sneak path problem.
The principle of the determination of the first compensation factor and the second compensation factor in some embodiments will be explained below with reference to fig. 5A-5C.
Fig. 5A illustrates a schematic structural diagram of a resistive switching cross-point array with wire parasitic resistance according to an exemplary embodiment of the present disclosure.
Referring to fig. 5A, the resistive switching cross point array 12 may include a plurality of bit lines, a plurality of word lines, and a plurality of resistive switching cells, where the plurality of resistive switching cells may form an array having a size of m × n, and m and n are integers greater than 1. In FIG. 5A, the voltage signal (V)1,V1,...,Vi...,Vm) Indicating a voltage signal, V, applied to the resistive cells of the resistive cross point array 12iRepresenting the input voltage of row i, GjiRepresents the conductance value, I, of the resistive unit in the ith row and the jth column of the resistive cross point array 12jAnd an output current of a j-th column of the resistive switching cross point array 12, wherein i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. gwlA conductance value representing a parasitic resistance between any two adjacent resistance change cells on the word line and a conductance value representing a parasitic resistance between the input terminal of the resistance change cross point array 12 and the adjacent resistance change cell, gblAnd a conductance value indicating the parasitic resistances of any two adjacent resistance change cells on the bit line and the conductance value of the parasitic resistance between the output terminal of the resistance change cross point array 12 and the adjacent resistance change cell. It should be noted that, in the embodiments of the present disclosure, parasitic electricity between any two adjacent resistive switching cells on each bit line may be assumed The conductance values of the resistances and the conductance values of the parasitic resistances between the input terminal of the resistive-switching cross point array 12 and the adjacent resistive-switching cells are equal, and it can be assumed that the conductance values of the parasitic resistances between any two adjacent resistive-switching cells on each word line and the conductance values of the parasitic resistances between the output terminal of the resistive-switching cross point array 12 and the adjacent resistive-switching cells are equal.
When the parasitic resistances on the word lines and bit lines are not considered, the voltage signal (V) can be represented by equation (3)1,V1,...,Vi...,Vm) Resistive unit G of resistive cross point array 12jiVector-matrix multiplication between the constructed matrices.
[ formula (3) ]
Ij＝∑iGji×Vi
If the effect of parasitic resistance on the word line is not taken into account (i.e., g)wl→ ∞), an equivalent circuit diagram of each column of the resistive switching cross-point array 12 can be obtained as shown in fig. 5B. In FIG. 5B, GiAn average conductance value or a maximum conductance value of the ith row of resistive switching cells may be represented. Solving the kirchhoff equation system of the equivalent circuit shown in fig. 5B can obtain equation (4).
[ formula (4) ]
In the formula (4), IresponseShows the output current of the equivalent circuit shown in FIG. 5B, aiRepresenting the input voltage V for each rowiThe inverse of the first compensation factor. Because of Gk/g bl1 is always true, therefore G k/gblThe multiple entries of (a) are negligible and the entries may be retained only once. Thus, aiCalculation can be performed according to the equation (1) as described above, whereby the input voltage V for each row of the equivalent circuit shown in fig. 5A can be obtainediFirst compensation factor of 1/ai。
[ formula (1) ]
In the formula (1), i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
Similarly, if the effect of parasitic resistance on the bit line is not considered (i.e., g)bl→ ∞), an equivalent circuit diagram of each row of the resistive switching cross-point array 12 can be obtained as shown in fig. 5C. In FIG. 5C, GjAnd the average conductance value or the maximum conductance value of the resistive switching unit in the j-th column. Solving the kirchhoff equation system of the equivalent circuit shown in fig. 5C can obtain equation (5).
[ formula (5) ]
Ijresponse＝bjGj·V
In the formula (5), Ij responseRepresents the output current of the j-th column of the equivalent circuit shown in FIG. 5C, bjRepresenting the output current I for each columnjThe inverse of the second compensation factor. Because of Gk/g wl1 is always true, therefore Gk/gwlThe multiple entries of (a) are negligible and the entries may be retained only once. Thus, b jCalculation can be made according to the equation (2) as described above, whereby the output current I for each column of the equivalent circuit shown in fig. 5A can be obtainedj Second compensation factor 1/bj。
[ formula (2) ]
In the formula (2), j is an integer of 1 to n, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
As described above, the plurality of input first voltage signals are compensated by the plurality of first compensation factors and the plurality of first current signals output by the resistive switching cross point array 12 are compensated by the plurality of second compensation factors, so that the plurality of compensated second current signals can represent multiplication (i.e., vector-matrix multiplication) between a vector made up of the plurality of input first voltage signals and a matrix made up of the conductance values of the plurality of resistive switching cells in the resistive switching cross point array 12. Thus, the processing apparatus in at least one exemplary embodiment of the present disclosure may avoid distortion of vector-matrix multiplication operations subject to wire parasitic resistance and sneak path problems. Further, in some embodiments of the present disclosure, the setting of the compensation parameter can be achieved by a simple circuit structure without manually setting the compensation parameter.
Fig. 6 shows a schematic structural diagram of a neural network classifier according to an exemplary embodiment of the present disclosure.
As shown in fig. 6, the neural network classifier 2 according to an exemplary embodiment of the present disclosure may include the processing device 1 as described above, however, embodiments of the present disclosure are not limited thereto. For example, the neural network classifier 2 may comprise only a part of the processing device 1. By including the processing device 1 or portions of the processing device 1, the neural network classifier 2 in exemplary embodiments of the present disclosure may avoid distortion of vector-matrix multiplication operations in the training process even under the influence of wire parasitic resistance and sneak path problems.
Fig. 7 shows a flow chart of a processing method according to an exemplary embodiment of the present disclosure.
Referring to fig. 7, the processing method may include step S11 and step S12.
Step S11: the method includes compensating input first voltage signals by using first compensation factors to obtain second voltage signals, and applying the second voltage signals to a resistive switching cross point array. The resistance change cross point array can comprise a plurality of bit lines, a plurality of word lines and a plurality of resistance change units, the plurality of resistance change units form an array with the size of m multiplied by n, and m and n are integers larger than 1.
In some embodiments, among the plurality of first compensation factorsEach may be determined based on a parasitic resistance on a corresponding bit line of the plurality of bit lines. For example, a first compensation factor 1/a of the plurality of first compensation factors for the first voltage signal of the ith row may be determined according to equation (1) as described abovei。
[ formula (1) ]
In the formula (1), i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
Alternatively, in some embodiments, the conductance values of the respective resistance change cells and the conductance values of the parasitic resistances on the conductive lines (word lines and bit lines) may not be given directly. In this case, the plurality of first compensation factors for the plurality of input first voltage signals may be obtained according to the following method: applying the plurality of first voltage signals to the resistive switching cross point array, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after the plurality of first voltage signals are applied; obtaining a conductance value of each row of resistance change units in a first column of resistance change units from the resistance change cross point array; and taking the ratio of the conductance value of the resistive unit of the ith row in the resistive units of the first column to the value of the first column output current in the uncompensated output currents as a first compensation factor of the first voltage signal corresponding to the resistive unit of the ith row, wherein i is an integer greater than or equal to 1 and less than or equal to m.
By compensating the input first voltage signals by using the first compensation factors, the embodiments of the present disclosure can avoid the distortion of the matrix operation result and the distortion of the neural network inference result caused by the distortion of the matrix operation result under the influence of the wire parasitic resistance and the sneak path problem.
Step S12: a plurality of first current signals are obtained based on a plurality of second voltage signals applied to a plurality of word lines of the resistive switching cross point array and a plurality of resistive switching cells.
In step S12, in the case where the plurality of second voltage signals are applied to the plurality of word lines of the resistance-change cross point array, the plurality of first current signals may be output through the resistance-change cross point array.
In some embodiments, the processing method may further include step S13: the plurality of first current signals are compensated by using the plurality of second compensation factors to obtain a plurality of second current signals, referring to fig. 8.
For example, in step S13, the current signal output by the resistive switching cross point array may be compensated. By compensating the plurality of input first voltage signals and compensating the plurality of first current signals output by the resistance change cross point array 12, multiplication (i.e., vector-matrix multiplication) between a vector made up of the plurality of input first voltage signals and a matrix made up of conductance values of the plurality of resistance change cells in the resistance change cross point array 12 can be represented by the plurality of second current signals.
In some embodiments, each of the plurality of second compensation factors may be determined according to a parasitic resistance on a respective word line of the plurality of word lines. For example, a second compensation factor 1/b for the first current signal of the jth column of the plurality of second compensation factors may be determined according to equation (2)j。
[ formula (2) ]
In the formula (2), j is an integer of 1 to n, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
Alternatively, in some embodiments, the conductance values of the respective resistance change cells and the conductance values of the parasitic resistances on the conductive lines (word lines and bit lines) may not be given directly. In this case, the plurality of second compensation factors for the plurality of input first current signals may be obtained according to the following method: applying a plurality of first voltage signals to the resistive switching cross point array 12, and obtaining a plurality of uncompensated output currents from the resistive switching cross point array 12 after the plurality of first voltage signals are applied; obtaining a conductance value of each row of resistance change units in the mth row of resistance change units from the resistance change cross point array 12; and taking the ratio of the conductance value of the resistive switching unit at the jth column in the resistive switching units at the mth row to the value of the output current at the jth column in the uncompensated output currents as a second compensation factor of the first current signal corresponding to the resistive switching unit at the jth column, wherein j is an integer which is greater than or equal to 1 and less than or equal to n.
As described above, the plurality of input first voltage signals are compensated by the plurality of first compensation factors and the plurality of first current signals output by the resistive switching cross point array are compensated by the plurality of second compensation factors, so that the plurality of compensated second current signals can represent multiplication (i.e., vector-matrix multiplication) between a vector made up of the plurality of input first voltage signals and a matrix made up of conductance values of the plurality of resistive switching cells in the resistive switching cross point array. Thus, the processing method in exemplary embodiments of the present disclosure may avoid distortion of vector-matrix multiplication operations, subject to wire parasitic resistance and sneak path problems.
It is to be noted that, although the example in which the processing method includes step S11 and the example in which the processing method includes step S11 and step S13 are shown above. However, embodiments of the present disclosure are not limited thereto. For example, the processing method may include step S13 without including step S11. That is, the processing method according to various embodiments of the present disclosure may include compensating for a current signal output by the resistive switching cross point array without compensating for the plurality of first voltage signals input. In this case, the embodiments of the present disclosure can still avoid the distortion of the matrix operation result and the distortion of the neural network inference result caused by the distortion of the matrix operation result affected by the wire parasitic resistance and the sneak path problem.
At least some of the benefits of the treatment apparatus and treatment method provided by the exemplary embodiments of the present disclosure are described below in conjunction with the figures.
Under the influence of wire parasitic resistance and sneak path problems, the resistive cross point array is distorted when vector-matrix multiplication is calculated. The larger the scale of the resistive switching cross point array is, the more obvious the distortion is. Fig. 9A and 9B show the case where the resistive switching cross point arrays of different sizes are implementing vector-matrix multiplication. In an example corresponding to the graphs shown in fig. 9A and 9B, parasitic resistances on word lines and bit lines in the resistive switching cross point array are 1 Ω (ohm), respectively, and resistance values of the resistive switching cells in the high resistance state and the low resistance state are 500k Ω (kilo-ohms) and 50k Ω, respectively. In fig. 9A and 9B, the ordinate is the normalized current of the resistance change cross point array output, and represents the relative current magnitude with respect to the ideal output. The abscissa represents the corresponding column of the resistive switching cross-point array. The dotted line (base) represents the ideal output that should be achieved in the absence of wire parasitic resistance.
More specifically, the solid line and the broken line in fig. 9A respectively represent output current curves of the resistive switching cross point arrays of sizes 128 × 64, 128 × 256 (i.e., arrays with different numbers of columns), and the square broken line and the triangular broken line represent inverse numbers a of the plurality of first compensation factors obtained by the method or apparatus in the embodiment of the present disclosure for the resistive switching cross point arrays of sizes 128 × 64, 128 × 256 iAnd the inverse b of the plurality of second compensation factorsjFitted output curves obtained according to the formula output ≈ input × a × G × B, where input ═ V (V)1,V2,…,Vi,…,Vm) Representing the input voltage signal, A ═ diag (a)1,a2,…,ai,…,am) A matrix formed by inverses of a plurality of first compensation factors, G a conductance matrix corresponding to the resistive switching cross point array, and B ═ diag (B)1,b2,…,bj,…,bn) A matrix formed by the inverses of a plurality of second compensation factors, output ═ I1,I2,…,Ij,…,In) Representing the output current of a resistive cross-point array of size m x n with an input voltage signal applied directly to the resistive cross-point array (i.e., without compensation for the input voltage signal and the output current signal). Similarly, the solid and dashed lines in fig. 9B represent sizes of 64 × 128, 256 × 128 (i.e., rows), respectivelyArrays with different numbers), the square dotted line and the triangular dotted line represent a fitted output curve obtained by using the inverses of the plurality of first compensation factors and the inverses of the plurality of second compensation factors obtained by the method or the apparatus in the embodiment of the present disclosure according to the formula output ≈ input × a × G × B for the resistive cross point array with the size of 64 × 128 and 256 × 128, and the definitions of the parameters input, a, G, and B are similar to those in fig. 9A, and thus are not repeated.
As can be seen from fig. 9A and 9B, the output current curve of the resistive switching cross point array coincides with the uncompensated output current, so that the uncompensated output current can be approximated by using output ≈ input × a × G × B, and the input voltage signal is compensated separately (for example, the input voltage signal is multiplied by a-1) And compensating the output current signal (e.g., multiplying the output current signal by B)-1) The result of the multiplication of the input voltage signal input with the conductance matrix G can then be obtained: output ≈ output (((input. A)-1)·A·G·B)·B-1The curve corresponding to this result substantially coincides with the dotted line indicated by base in the figure. That is, by compensating the input voltage signal and compensating the output current signal, an ideal output representing the multiplication of the voltage signal input by the conductance matrix G can be obtained substantially.
It should be noted that although exemplary technical effects of compensating the input voltage signal and compensating the output current signal are described in conjunction with fig. 9A and 9B, the same or similar technical effects may be obtained in other embodiments. For example, in the case of only compensating the input signal or only compensating the output current signal, the embodiments of the present disclosure may still avoid distortion of the matrix operation result and the neural network inference result caused thereby to some extent under the influence of the wire parasitic resistance and the sneak path problem.
Fig. 10 illustrates an accuracy diagram of classification results obtained by applying a processing device and/or a processing method according to an exemplary implementation of the present disclosure to a neural network classifier or a neural network classification method. In the example corresponding to fig. 10, the size of the resistive switching cross point array is 400 × 300, the resistance values corresponding to the low resistance state and the high resistance state of the resistive switching unit may be 50k Ω and 500k Ω, respectively, and the neural network classifier or the neural network classification method is used to classify a handwritten digital data set mnist (modified National Institute of standards and Technology database) using a 3-layer feed-forward neural network (the topology of the network is 784-. In fig. 10, the abscissa represents a Line Resistance (Line Resistance) representing the magnitude of the parasitic Resistance of the wire, and the ordinate represents the accuracy of classification by the neural network classifier or the neural network classification method. In fig. 10, a dotted line (denoted by base) represents an ideal output that should be obtained in the absence of the wire parasitic resistance, a solid line (denoted by Parasitics) represents a decrease in the neural network classification accuracy in the presence of the wire parasitic resistance, and a dotted line (denoted by IDMC) represents a recovery of the neural network classification accuracy after the processing apparatus and/or the processing method provided by the exemplary embodiment of the present disclosure is employed in the presence of the wire parasitic resistance.
As can be seen from fig. 10, even in the case of being affected by wire parasitic resistance and sneak path problems, the neural network classifier or the neural network classification method using the processing apparatus and/or the processing method provided by the exemplary embodiments of the present disclosure can avoid distortion in the training process.
The above description is only an exemplary embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can make various changes or substitutions within the technical scope of the present disclosure, and the changes or substitutions should be covered within the scope of the present disclosure. Accordingly, the scope of the disclosure should be determined from the following claims.
Claims (10)
1. A processing apparatus comprising an input voltage compensation device and a resistive switching cross point array, wherein,
the input voltage compensation device is configured to compensate a plurality of first voltage signals input by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and apply the plurality of second voltage signals to the resistive switching cross point array,
the resistance change cross point array comprises a plurality of bit lines, a plurality of word lines and a plurality of resistance change units, wherein the plurality of resistance change units form an array with the size of m multiplied by n, m and n are integers larger than 1, and the resistance change cross point array is configured to obtain a plurality of first current signals based on a plurality of second voltage signals applied to the plurality of word lines and the plurality of resistance change units.
2. The processing device of claim 1, wherein each of the plurality of first compensation factors is determined from an equivalent circuit of a resistive switching crossbar array that does not account for parasitic resistances on the plurality of word lines.
3. The processing device of claim 2, further comprising a first compensation factor determination device configured to determine a first compensation factor 1/a of the plurality of first compensation factors for the first voltage signal of the ith row according toi：
Wherein i is an integer of 1 to m inclusive, GkRepresenting the average or maximum conductance, g, of the resistive-switching cells of the k-th rowblAnd a conductance value representing a parasitic resistance between any two adjacent resistance change cells on the corresponding bit line.
4. The processing device according to claim 1, further comprising a first compensation factor determination means,
wherein the first compensation factor determination device is configured to:
applying the plurality of first voltage signals to the resistive switching cross point array and obtaining a plurality of uncompensated output currents from the resistive switching cross point array after application of the plurality of first voltage signals;
Obtaining a conductance value of each row of resistance change units in a first column of resistance change units from the resistance change cross point array; and
and taking the ratio of the conductance value of the resistive unit in the ith row in the resistive units in the first column to the value of the first column output current in the uncompensated output currents as a first compensation factor of the first voltage signal corresponding to the resistive unit in the ith row, wherein i is an integer greater than or equal to 1 and less than or equal to m.
5. The processing device of claim 1, wherein the input voltage compensation arrangement is configured to adjust at least one of an amplitude, a pulse width, and a number of pulses of the plurality of first voltage signals in accordance with the plurality of first compensation factors.
6. The processing apparatus according to any one of claims 1 to 5, further comprising an output current compensation device,
wherein the output current compensation device is configured to: the plurality of first current signals are compensated by using a plurality of second compensation factors to obtain a plurality of second current signals.
7. The processing device of claim 6, wherein each of the plurality of second compensation factors is determined from an equivalent circuit of a resistive switching crossbar array that does not account for parasitic resistances on the plurality of bit lines.
8. The processing apparatus according to claim 7, wherein the processing apparatus further comprises a second compensation factor determination device configured to determine a second compensation factor 1/b of the plurality of second compensation factors for the first current signal of the jth column according toj：
Wherein j is an integer of 1 or more and n or less, GkRepresenting the average or maximum conductance of the resistive cells in the kth column, gwlAnd a conductance value representing a parasitic resistance between any two adjacent resistance change units on the corresponding word line.
9. A neural network classifier comprising the processing device of any one of claims 1 to 8.
10. A method of processing, comprising:
compensating the input first voltage signals by using a plurality of first compensation factors to obtain a plurality of second voltage signals, and applying the second voltage signals to a resistance change cross point array, wherein the resistance change cross point array comprises a plurality of bit lines, a plurality of word lines and a plurality of resistance change units, the resistance change units form an array with the size of m × n, and m and n are integers more than 1; and
obtaining a plurality of first current signals based on a plurality of second voltage signals applied to the plurality of word lines of the resistive switching cross point array and the plurality of resistive switching cells.
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