CN111835344B - Phase-locked loop circuit and terminal - Google Patents

Phase-locked loop circuit and terminal Download PDF

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Publication number
CN111835344B
CN111835344B CN202010744106.8A CN202010744106A CN111835344B CN 111835344 B CN111835344 B CN 111835344B CN 202010744106 A CN202010744106 A CN 202010744106A CN 111835344 B CN111835344 B CN 111835344B
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signal
coupled
pull
output
phase
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CN111835344A (en
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金玮
郭义龙
罗大猷
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Spreadtrum Communications Shanghai Co Ltd
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Spreadtrum Communications Shanghai Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase-locked loop circuit and terminal, phase-locked loop circuit include phase discriminator, charge pump, wave filter, voltage controlled oscillator and frequency divider, phase-locked loop circuit still includes: the charging current source is used for charging a capacitor in the filter; the input end of the detection circuit is coupled with the output end of the phase discriminator, the output end of the detection circuit is coupled with the control end of the charging current source and used for detecting the difference between a pull-up signal and a pull-down signal output by the phase discriminator and controlling the charging current source to charge/discharge the capacitor in the filter according to the difference, the pull-up signal is used for controlling the charge pump to charge, and the pull-down signal is used for controlling the charge pump to discharge. The technical scheme of the invention can realize the quick locking of the phase-locked loop circuit.

Description

Phase-locked loop circuit and terminal
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a phase-locked loop circuit and a terminal.
Background
A Phase-Locked Loop (PLL) is a feedback control circuit. Currently, commonly used pll circuits are classified into digital pll and analog pll.
In the prior art, a method for realizing fast locking by an analog phase-locked loop is shown in fig. 1, a current source of a charge pump of the circuit is divided into two parts which are respectively controlled by two control circuits, one of the two parts is directly controlled by a PFD, and the other part is controlled by the PFD and a phase detection circuit together. During the locking process of the PLL, the current of the charge pump can be increased, and after the phase detection circuit outputs a LOCK signal, the current is restored to a normal value, so that the fast locking is realized.
However, the digital method for achieving fast locking of the PLL not only requires a complex algorithm, but also requires an accurate reference clock frequency detection circuit, and the whole circuit is complex. The analog phase-locked loop needs a locking detection circuit and an acceleration control circuit, and the circuit is complex; moreover, if the delay of the lock detection circuit is large, overshoot of the control voltage of the voltage controlled oscillator may be caused, which is disadvantageous to the lock of the PLL loop.
Disclosure of Invention
The invention solves the technical problem of how to realize the quick locking of a phase-locked loop circuit.
To solve the above technical problem, an embodiment of the present invention provides a phase-locked loop circuit, where the phase-locked loop circuit includes: phase discriminator, charge pump, wave filter, voltage controlled oscillator and frequency divider, phase-locked loop circuit still includes: the charging current source is used for charging a capacitor in the filter; the input end of the detection circuit is coupled with the output end of the phase discriminator, the output end of the detection circuit is coupled with the control end of the charging current source and used for detecting the difference between a pull-up signal and a pull-down signal output by the phase discriminator and controlling the charging current source to charge/discharge the capacitor in the filter according to the difference, the pull-up signal is used for controlling the charge pump to charge, and the pull-down signal is used for controlling the charge pump to discharge.
Optionally, the detection circuit detects a difference between the pull-up signal and the pull-down signal at the current time, or the detection circuit delays the pull-up signal and detects a difference between the delayed pull-up signal and the delayed pull-down signal at the current time.
Optionally, the detection circuit includes: and a clock signal end of the first level trigger is connected with the pull-down signal, a data end of the first level trigger is connected with the pull-up signal, and an output signal output by a data output end of the first level trigger is used for controlling the charging/discharging of the charging current source on/from a capacitor in the filter.
Optionally, the detection circuit includes: the input end of the delayer is connected with the pull-up signal; and the clock signal end of the second level trigger is connected into the pull-down signal, the data end of the second level trigger is coupled with the output end of the time delay unit, and the output signal output by the data output end of the second level trigger is used for controlling the charging/discharging of the charging current source on the capacitor in the filter.
Optionally, the detection circuit further includes: the input end of the delayer is connected with the pull-up signal; a third level flip-flop, a clock signal terminal of which is connected to the pull-down signal, and a data terminal of which is coupled to the output terminal of the delay; the input end of the inverter is coupled with the data output end of the third level flip-flop; and a clock signal end of the fourth level flip-flop is coupled with the output end of the inverter, a data end of the fourth level flip-flop is connected with a fixed reference signal, and an output signal output by the output end of the fourth level flip-flop is used for controlling the charging/discharging of the capacitor in the filter by the charging current source.
Optionally, the detection circuit further includes: the input end of the timer is connected with a clock control signal; an or gate, a first input terminal of which is coupled to the output terminal of the timer, a second input terminal of which is connected to the output signal, and a signal output by an output terminal of which is used for controlling the charging current source to charge/discharge a capacitor in the filter.
Optionally, the charging current source includes: the input end of the first current source is connected with a power supply voltage; and a control switch, a control terminal of which is coupled to the output terminal of the detection circuit, an input terminal of which is coupled to the output terminal of the first current source, and an output terminal of which is coupled to the capacitor in the filter.
Optionally, the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output terminal of the detection circuit, a drain of the NMOS transistor is coupled to the output terminal of the first current source, and a source of the NMOS transistor is coupled to the capacitor in the filter; or, the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output terminal of the detection circuit, a source of the PMOS transistor is coupled to the output terminal of the first current source, and a drain of the PMOS transistor is coupled to the capacitor in the filter.
Optionally, the charging current source includes: a control switch, a control end of which is coupled with the output end of the detection circuit, and an input end of which is coupled with the capacitor in the filter; and the input end of the second current source is coupled with the output end of the control switch, and the output end of the second current source is grounded.
Optionally, the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output terminal of the detection circuit, a source of the PMOS transistor is coupled to the capacitor in the filter, and a drain of the PMOS transistor is coupled to the input terminal of the second current source; or, the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output terminal of the detection circuit, a drain of the NMOS transistor is coupled to the capacitor in the filter, and a source of the NMOS transistor is coupled to the input terminal of the second current source.
The embodiment of the invention also discloses a terminal which comprises the phase-locked loop circuit.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the technical scheme of the invention, the phase-locked loop circuit comprises a charging current source, a charging unit and a control unit, wherein the charging current source is used for charging a capacitor in the filter; the detection circuit is used for detecting the difference between a pull-up signal and a pull-down signal output by the phase discriminator and controlling the charging current source to charge/discharge the capacitor in the filter according to the difference, the pull-up signal is used for controlling the charge pump to charge, and the pull-down signal is used for controlling the charge pump to discharge. According to the technical scheme, the difference between the pull-up signal and the pull-down signal of the phase-locked loop circuit in the locking process stage and the locking completion stage is utilized, for example, the pulse width difference between the pull-up signal and the pull-down signal in the locking process stage is large and tends to be consistent in the locking completion stage, namely, whether the phase-locked loop is in the locking process stage is judged only by detecting the pull-up signal and the pull-down signal output by the phase discriminator, so that the charging can be carried out by adopting a charging current source in the locking process stage, the locking process of the phase-locked loop is accelerated by combining the charging process of a charge pump, and the rapid locking of the phase-locked loop circuit is realized on the basis of simple circuit realization.
Further, the detection circuit may include a delay, an input terminal of which is connected to the pull-up signal; and a second level flip-flop, a clock signal terminal of which is connected to the pull-down signal, a data terminal of which is coupled to the output terminal of the delay, and an output signal output by the data output terminal of which is used for controlling the charging current source to charge/discharge the capacitor in the filter. According to the technical scheme, the delay device is arranged, so that when the phase-locked loop is judged to be in the locking process stage, the delayed pull-up signal is compared with the original pull-down signal, the charging current source can be turned off for charging before the locking completion stage, overshoot of the voltage controlled oscillator control voltage is avoided, and the locking stability of the phase-locked loop is ensured.
Drawings
FIG. 1 is a schematic diagram of a prior art PLL circuit;
FIG. 2 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a specific structure of a detection circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of signals in a specific application scenario according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another exemplary embodiment of a detection circuit;
FIG. 6 is a schematic diagram of another phase-locked loop circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a phase-locked loop circuit according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of a specific structure of another detection circuit according to an embodiment of the present invention;
fig. 9 is a timing diagram of signals in another specific application scenario of the embodiment of the present invention.
Detailed Description
As described in the background art, the digital method for achieving fast locking of the PLL not only requires a complex algorithm, but also requires an accurate reference clock frequency detection circuit, and the overall circuit is complex. The analog phase-locked loop needs a locking detection circuit and an acceleration control circuit, and the circuit is complex; moreover, if the delay of the lock detection circuit is large, overshoot of the control voltage of the voltage controlled oscillator may be caused, which is disadvantageous to the lock of the PLL loop.
The technical scheme of the invention utilizes the difference between the pull-up signal and the pull-down signal of the phase-locked loop circuit in the locking process stage and the locking completion stage, for example, the pulse width of the pull-up signal and the pull-down signal has larger difference in the locking process stage and tend to be consistent in the locking completion stage, namely, the phase-locked loop is judged whether to be in the locking process stage only by detecting the pull-up signal and the pull-down signal output by the phase discriminator, so that the charging current source can be adopted to charge in the locking process stage, the locking process of the phase-locked loop is accelerated by combining the charging process of the charge pump, and the rapid locking of the phase-locked loop circuit is realized on the basis of simple circuit realization.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic structural diagram of a phase-locked loop circuit according to an embodiment of the invention.
The phase-locked loop circuit of the embodiment of the present invention may include a phase detector 201, a charge pump 202, a filter 203, a voltage-controlled oscillator 204, and a frequency divider 205.
The phase detector 201, the charge pump 202, the filter 203, and the voltage controlled oscillator 204 are sequentially connected, and an output terminal of the voltage controlled oscillator 204 outputs a feedback clock signal CKFB to an input terminal of the phase detector 201 through the frequency divider 205. The input terminal of the phase detector 201 is also connected to an external clock signal CKIN.
The phase-locked loop circuit may also include a detection circuit 206 and a charging current source 207.
The output end of the phase detector 201 is connected to the input end of the detection circuit 206, and the output end of the detection circuit 206 is connected to the control end of the charging current source 207. The detection circuit 206 can detect a difference between a pull-UP signal UP and a pull-down signal DN output by the phase detector, and control the charging current source 207 to charge/discharge a capacitor in the filter 203 according to the difference.
In a specific implementation, the pull-UP signal UP is used to control the charge pump 202 to charge, and the pull-down signal DN is used to control the charge pump 202 to discharge. In other words, the pull-UP signal UP is used to control the charge pump 202 to pull UP the input voltage of the vco 204, and the pull-down signal DN is used to control the charge pump 202 to pull down the input voltage of the vco 204.
In a specific implementation, the detection circuit 206 may determine that the phase-locked loop circuit is in the phase of the locking process by detecting a difference between the pull-UP signal UP and the pull-down signal DN, and then an output signal of the detection circuit 206 may control the charging current source 207 to turn on, so as to charge in combination with the charge pump 202, and pull UP the input voltage of the voltage-controlled oscillator 204 together, thereby accelerating the locking of the phase-locked loop circuit; alternatively, the output signal of the detection circuit 206 may control the charging current source 207 to turn on to discharge in conjunction with the charge pump 202, which in combination pulls down the input voltage of the vco 204, speeding up the lock of the pll circuit.
Accordingly, the detection circuit 206 can determine that the pll circuit is in the phase of locking completion by detecting the difference between the pull-UP signal UP and the pull-down signal DN, and then the output signal of the detection circuit 206 can control the charging current source 207 to turn off, so that the pll circuit enters a stable locking state.
In a conventional phase-locked loop circuit, the output current of the charge pump 202 is small due to the limitation of bandwidth, noise and stability, so that the locking time is long. The phase-locked loop circuit structure of the embodiment of the invention can accelerate the locking process and reduce the time required by the phase-locked loop for locking.
The embodiment of the invention utilizes the difference between the pull-up signal and the pull-down signal of the phase-locked loop circuit in the locking process stage and the locking completion stage, for example, the pulse width of the pull-up signal and the pull-down signal is larger in the locking process stage and tends to be consistent in the locking completion stage, namely, whether the phase-locked loop is in the locking process stage is judged only by detecting the pull-up signal and the pull-down signal output by the phase discriminator, so that the charging can be carried out by adopting the charging current source in the locking process stage, the locking process of the phase-locked loop is accelerated by combining the charging process of the charge pump, and the rapid locking of the phase-locked loop circuit is realized on the basis of simple circuit realization.
In a non-limiting embodiment of the present invention, the detection circuit 206 detects a difference between the pull-up signal and the pull-down signal at the current time, or the detection circuit 206 delays the pull-up signal and detects a difference between the delayed pull-up signal and the pull-down signal at the current time.
In this embodiment, the detection circuit 206 may detect a difference between the pull-up signal and the pull-down signal at the current time, or a difference between the delayed pull-up signal and the pull-down signal at the current time, to determine the state of the phase-locked loop circuit. For example, if the delayed pull-up signal and the delayed pull-down signal are both at a high level at the current moment, it is determined that the phase-locked loop circuit is in the locking process stage; and if one of the delayed pull-up signal and the delayed pull-down signal is at a high level and the other is at a low level at the current moment, determining that the phase-locked loop circuit is in a locking completion stage.
In a non-limiting embodiment of the present invention, the detection circuit 206 may include a first level flip-flop having a clock signal terminal CLK connected to the pull-down signal, a data terminal connected to the pull-up signal, and an output signal output from a data output terminal for controlling the charging current source to charge/discharge the capacitor in the filter.
In a specific implementation, if the input voltage Vctrl of the voltage-controlled oscillator 204 is higher and the output frequency thereof is higher, after the phase-locked loop circuit is started (enabled), at this time, the input voltage Vctrl is very low, the output frequency of the voltage-controlled oscillator 204 is low, and the pulse width of the pull-UP signal UP is greater than that of the pull-down signal DN, so that the charge time of the charge pump 202 is greater than the discharge time to raise the input voltage Vctrl. Under the condition that the pulse width of the pull-UP signal UP is larger than that of the pull-down signal DN, a clock signal end CLK of the first level trigger is connected to the pull-down signal, and a data end CLK of the first level trigger is connected to the pull-UP signal.
On the contrary, if the input voltage Vctrl of the vco 204 is lower, the output frequency thereof is higher, and after the phase-locked loop circuit is enabled (enabled), the input voltage Vctrl is at a high level, the output frequency of the vco 204 is lower, and the pulse width of the pull-down signal DN is greater than that of the pull-UP signal UP, so that the discharge time of the charge pump 202 is greater than the charge time, so as to reduce the input voltage Vctrl. In other words, if the pulse width of the pull-down signal DN is greater than that of the pull-UP signal UP, the clock signal terminal CLK of the first level flip-flop is connected to the pull-UP signal UP, and the data terminal D thereof is connected to the pull-down signal DN.
In one non-limiting embodiment of the present invention, the detection circuit 206 may include a delay, the input of which is coupled to the pull-up signal; and the clock signal end of the second level trigger is connected into the pull-down signal, the data end of the second level trigger is coupled with the output end of the time delay unit, and the output signal output by the data output end of the second level trigger is used for controlling the charging/discharging of the charging current source on the capacitor in the filter.
Different from the foregoing embodiment, in the embodiment of the present invention, by setting the delay, when determining whether the phase-locked loop is in the phase of the locking process, the delayed pull-up signal is compared with the original pull-down signal, so that the charging current source can be turned off for charging before the phase of locking is completed, thereby avoiding causing overshoot of the control voltage of the voltage-controlled oscillator, and ensuring the stability of locking of the phase-locked loop.
IN another non-limiting embodiment of the present invention, referring to fig. 3, the detection circuit 206 may include a delay 301, a third level flip-flop 302, an inverter IN, and a fourth level flip-flop 303.
The input end of the delay unit 301 is connected to the pull-UP signal UP; the clock signal terminal Clk of the third level flip-flop 302 is connected to the pull-down signal DN, and the data terminal D thereof is coupled to the output terminal of the delay unit 301; the input end of the inverter IN is coupled with the data output end Q of the third level trigger; the clock signal terminal Clk of the fourth level flip-flop 303 is coupled to the output terminal of the inverter IN, the data terminal D thereof is connected to the fixed reference signal TIEH, and the output signal OUTN output by the output terminal Q thereof is used for controlling the charging current source to charge/discharge the capacitor IN the filter.
In a specific implementation, the third level flip-flop 302 and the fourth level flip-flop 303 are triggered at a high level.
Referring to fig. 4, in this embodiment, the higher the input voltage Vctrl of the vco 204 is, the higher the output frequency thereof is, and the pulse width of the pull-UP signal UP is greater than that of the pull-down signal DN. The signal UP _ a after the pull-UP signal UP is delayed (Delay) is accessed to the data terminal D of the third level flip-flop 302. The clock signal terminal Clk of the third level flip-flop 302 is connected to the pull-down signal DN. When the pull-down signal DN is at a high level, the third level flip-flop 302 is triggered to output the level of the data terminal D, that is, the pull-UP signal UP, and in a phase of a locking process (Fast Lock), since the pull-UP signal UP is also at a high level when the pull-down signal DN is at a high level, the signal UP _ B output by the data output terminal Q of the third level flip-flop 302 is continuously at a high level. The signal UP _ CK after UP _ B passes through the inverter IN is continuously low. The fourth level flip-flop 303 is reset to a low level (REST = 0), and thus the signal OUTN output from the data output terminal Q is continuously at a high level when the input signal UP _ CK of the clock signal terminal Clk is continuously at a low level. In the case of an NMOS transistor as the control switch of the charging current source, the charging current source continues to charge the capacitor in the filter during the phase of the locking process (Fast Lock).
With reference to fig. 4, at time T0, when the pull-down signal DN is at a high level, the pull-UP signal UP is at a low level, the signal UP _ B output by the data output terminal Q of the third level flip-flop 302 is at a low level, the signal UP _ CK after the UP _ B passes through the inverter IN is at a high level, the fourth level flip-flop 303 is triggered by the signal UP _ CK to output the fixed reference signal TIEH, the fixed reference signal TIEH is at a high level, and the signal OUTN output by the data output terminal Q is at a low level. Under the condition that a control switch of the charging current source is an NMOS tube, the charging current source is closed at the time T0 to charge the capacitor in the filter.
In a non-limiting embodiment of the present invention, referring to fig. 5, the detection circuit 206 may further include a timer 304 and an OR gate OR.
Wherein, the input end of the timer 304 is connected to the clock control signal CKIN; the first input terminal of the OR gate OR is coupled to the output terminal of the timer, the second input terminal thereof is connected to the output signal, and the signal output by the output terminal thereof is used for controlling the charging current source to charge/discharge the capacitor in the filter.
In this embodiment, by setting the timer, when the detection circuit fails to accurately determine the locking state of the phase-locked loop through the pull-up signal and the pull-down signal at the phase of completing the locking of the phase-locked loop circuit, the charging current source is timely turned off to charge, thereby avoiding causing the overshoot of the voltage-controlled oscillator control voltage and ensuring the stability of the locking of the phase-locked loop.
In one non-limiting embodiment of the present invention, the charging current source 207 may include: the input end of the first current source is connected with a power supply voltage; and a control switch, a control terminal of which is coupled to the output terminal of the detection circuit, an input terminal of which is coupled to the output terminal of the first current source, and an output terminal of which is coupled to the capacitor in the filter.
The embodiment of the invention is suitable for the condition that the switch transistor in the voltage-controlled oscillator 204 is an NMOS, and the grid control voltage of the NMOS is lower after the phase-locked loop circuit is started.
In specific implementation, the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output terminal of the detection circuit, a drain of the NMOS transistor is coupled to the output terminal of the first current source, and a source of the NMOS transistor is coupled to a capacitor in the filter; or, the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output terminal of the detection circuit, a source of the PMOS transistor is coupled to the output terminal of the first current source, and a drain of the PMOS transistor is coupled to the capacitor in the filter.
In an embodiment of the invention, referring to fig. 6, the control switch may also be an NMOS transistor MN0 and a PMOS transistor MP0 connected in parallel. Accordingly, the detection circuit 206 outputs two output signals OUTN and OUTP, which are respectively connected to the gate of the NMOS transistor MN0 and the gate of the PMOS transistor MP0. The impedance can be reduced by a parallel transistor configuration.
Fig. 5 shows a specific circuit structure of the detection circuit 206.
In conjunction with the timing diagram of signals shown in fig. 4, the switching transistor MN _ VCO in the VCO 204 is NMOS, so the higher the gate control voltage Vctrl is, the higher the output frequency of the VCO 204 is. After the pll circuit is started, the Vctrl voltage is very low, the output frequency of the vco 204 is low, the pulse width of the UP signal is greater than the pulse width of the DN signal, and the charge time of the charge pump is greater than the discharge time, so as to raise the Vctrl voltage. In the locking process stage, the DN signal cannot acquire the low level of the UP signal, the output signal OUTP continues to be the low level, the OUTN continues to be the high level, the NMOS transistor MN0 and the PMOS transistor MP0 are continuously conducted, the charging current source I1 always charges the capacitor C1, the capacitance value of the capacitor C1 is usually large, the current is large, and therefore the voltage of Vctrl rises quickly. When the output frequency of the vco 204 approaches the preset value, the DN signal acquires the low level of the UP signal, and then the NMOS transistor MN0 and the PMOS transistor MP0 are turned off.
In one non-limiting embodiment of the present invention, the charging current source 207 may include: a control switch, a control end of which is coupled with the output end of the detection circuit, and an input end of which is coupled with the capacitor in the filter; and the input end of the second current source is coupled with the output end of the control switch, and the output end of the second current source is grounded.
Unlike the first current source in the previous embodiment, the second current source in the embodiment of the present invention is grounded. The embodiment of the invention is suitable for the situation that the switch transistor in the voltage-controlled oscillator 204 is PMOS, and the grid control voltage of the switch transistor is higher after the phase-locked loop circuit is started.
In specific implementation, the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output terminal of the detection circuit, a source of the PMOS transistor is coupled to a capacitor in the filter, and a drain of the PMOS transistor is coupled to the input terminal of the second current source; or, the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output terminal of the detection circuit, a drain of the NMOS transistor is coupled to the capacitor in the filter, and a source of the NMOS transistor is coupled to the input terminal of the second current source.
In another embodiment of the present invention, referring to fig. 7, the control switch may also be an NMOS transistor MN0 and a PMOS transistor MP0 connected in parallel. Accordingly, the detection circuit 206 outputs two output signals OUTN and OUTP, which are respectively connected to the gate of the NMOS transistor MN0 and the gate of the PMOS transistor MP0. The impedance can be reduced by a parallel transistor configuration. Unlike the pll circuit configuration of fig. 6, the second current source I2 is grounded.
Fig. 8 shows a specific circuit structure of the detection circuit 206. Unlike the detection circuit 206 shown in fig. 5, the delay unit 301 receives the pull-down signal DN, and the flip-flop 302 receives the pull-UP signal UP.
In conjunction with the timing diagram of signals shown in fig. 9, the switching transistor MP _ VCO in the VCO 204 is PMOS, so the lower the gate control voltage Vctrl, the higher the output frequency of the VCO 204. After the pll circuit is started, at this time, the VCtrl voltage is at a high level, the output frequency of the vco 204 is low, and the pulse width of the DN signal is greater than that of the UP signal, so that the discharge time of the charge pump is greater than the charge time to reduce the VCtrl voltage. Because the UP signal does not acquire the low level of the DN signal in the locking process stage, the output signal OUTP is continuously at the low level, the OUTN is continuously at the high level, the NMOS transistor MN0 and the PMOS transistor MP0 are continuously conducted, the charging current source I2 always discharges the capacitor C1, the capacitance value of the capacitor C1 is usually very large, and the current is very large, so that the Vctrl voltage is reduced quickly, and when the VCO output frequency approaches the preset value, the UP signal acquires the low level of the DN signal, and then the NMOS transistor MN0 and the PMOS transistor MP0 are turned off.
The embodiment of the invention also discloses terminal equipment which can comprise the phase-locked loop circuit. The terminal device includes, but is not limited to, a mobile phone, a computer, a tablet computer, and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (11)

1. A phase-locked loop circuit, includes phase discriminator, charge pump, filter, voltage controlled oscillator and frequency divider, its characterized in that, phase-locked loop circuit still includes:
the charging current source is used for charging a capacitor in the filter;
the input end of the detection circuit is coupled with the output end of the phase discriminator, the output end of the detection circuit is coupled with the control end of the charging current source and used for detecting the difference between a pull-up signal and a pull-down signal output by the phase discriminator and controlling the charging current source to charge/discharge the capacitor in the filter according to the difference, the pull-up signal is used for controlling the charge pump to charge, and the pull-down signal is used for controlling the charge pump to discharge.
2. The phase-locked loop circuit of claim 1, wherein the detection circuit detects a difference between the pull-up signal and the pull-down signal at a current time, or wherein the detection circuit delays the pull-up signal and detects a difference between the delayed pull-up signal and the pull-down signal at the current time.
3. The phase-locked loop circuit of claim 1, wherein the detection circuit comprises:
and a clock signal end of the first level trigger is connected with the pull-down signal, a data end of the first level trigger is connected with the pull-up signal, and an output signal output by a data output end of the first level trigger is used for controlling the charging/discharging of the charging current source on/from a capacitor in the filter.
4. The phase-locked loop circuit of claim 1, wherein the detection circuit comprises:
the input end of the delayer is connected with the pull-up signal;
and the clock signal end of the second level trigger is connected into the pull-down signal, the data end of the second level trigger is coupled with the output end of the time delay unit, and the output signal output by the data output end of the second level trigger is used for controlling the charging/discharging of the charging current source on the capacitor in the filter.
5. The phase-locked loop circuit of claim 1, wherein the detection circuit further comprises:
the input end of the delayer is connected with the pull-up signal;
a third level flip-flop, a clock signal terminal of which is connected to the pull-down signal, and a data terminal of which is coupled to the output terminal of the delay;
the input end of the inverter is coupled with the data output end of the third level trigger;
and a clock signal end of the fourth level flip-flop is coupled with the output end of the inverter, a data end of the fourth level flip-flop is connected with a fixed reference signal, and an output signal output by the output end of the fourth level flip-flop is used for controlling the charging/discharging of the capacitor in the filter by the charging current source.
6. The phase-locked loop circuit of any of claims 3 to 5, wherein the detection circuit further comprises:
the input end of the timer is connected with a clock control signal;
an or gate, a first input terminal of which is coupled to the output terminal of the timer, a second input terminal of which is connected to the output signal, and a signal output by an output terminal of which is used for controlling the charging current source to charge/discharge a capacitor in the filter.
7. The phase-locked loop circuit of claim 1, wherein the charging current source comprises:
the input end of the first current source is connected with a power supply voltage;
and a control switch, a control terminal of which is coupled to the output terminal of the detection circuit, an input terminal of which is coupled to the output terminal of the first current source, and an output terminal of which is coupled to the capacitor in the filter.
8. The phase-locked loop circuit of claim 7, wherein the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output of the detection circuit, a drain of the NMOS transistor is coupled to the output of the first current source, and a source of the NMOS transistor is coupled to the capacitor in the filter; or, the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output terminal of the detection circuit, a source of the PMOS transistor is coupled to the output terminal of the first current source, and a drain of the PMOS transistor is coupled to the capacitor in the filter.
9. The phase-locked loop circuit of claim 1, wherein the charging current source comprises: a control switch, a control terminal of which is coupled to the output terminal of the detection circuit, and an input terminal of which is coupled to the capacitor in the filter;
and the input end of the second current source is coupled with the output end of the control switch, and the output end of the second current source is grounded.
10. The pll circuit of claim 9, wherein the control switch is a PMOS transistor, a gate of the PMOS transistor is coupled to the output of the detection circuit, a source of the PMOS transistor is coupled to the capacitor of the filter, and a drain of the PMOS transistor is coupled to the input of the second current source; or, the control switch is an NMOS transistor, a gate of the NMOS transistor is coupled to the output terminal of the detection circuit, a drain of the NMOS transistor is coupled to the capacitor in the filter, and a source of the NMOS transistor is coupled to the input terminal of the second current source.
11. A terminal comprising a phase locked loop circuit as claimed in any one of claims 1 to 10.
CN202010744106.8A 2020-07-29 2020-07-29 Phase-locked loop circuit and terminal Active CN111835344B (en)

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