CN111834313B - Active chip high-density TSV structure and manufacturing method - Google Patents
Active chip high-density TSV structure and manufacturing method Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
Abstract
The invention discloses an active chip high-density TSV structure, which comprises: a silicon substrate; the first dielectric layer is arranged on the upper surface of the silicon substrate; the high-density silicon through hole opening slot penetrates through the first medium layer and exposes the first medium layer; the second dielectric layer is arranged in the high-density silicon through hole open slot; the high-density through silicon via extends from the groove bottom of the high-density through silicon via open groove to the inside of the silicon substrate; and a high-density through-silicon-via interconnect structure electrically connected to the high-density through-silicon-via.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to an active chip high-density TSV structure and a manufacturing method thereof.
Background
It is more difficult to fabricate Through Silicon Vias (TSVs) on an active chip than it is to fabricate TSVs on a 2.5D interposer. The 2.5D silicon interposer is made of pure silicon material, but the active chip has a dielectric layer (usually silicon dioxide) of 5 to 10 microns on a silicon wafer, so when the active chip is fabricated with a through-silicon via, the above dielectric layer needs to be etched in addition to the conventional through-silicon via etching process.
Fig. 1 shows a structure 100 formed by fabricating a TSV on an active chip by performing a TSV process according to a conventional silicon-based material, because a dielectric layer 120 and a silicon-based wafer 110 are two different materials, a beak-shaped feature 140 is formed at an interface between the dielectric layer 120 and the silicon-based wafer 110 by a through hole 130 formed on the dielectric layer 120 and the silicon-based wafer 110 by one-time etching, and because the beak-shaped feature 140 is a concave structure, it is very difficult to achieve conductive layer coverage of the beak-shaped feature 140 during fabrication of an electroplating seed layer before TSV filling, so that subsequent TSV insulation and metallization are difficult to achieve.
In order to overcome the problem of via etching caused by the active chip having two materials, namely a dielectric layer and a silicon-based wafer, fig. 2 shows a solution in the prior art, which uses twice TSV etching on the active chip, that is, first etching a dielectric layer TSV hole 230 with a larger size on a dielectric layer 220, and then etching a TSV hole 240 with a smaller size on a silicon substrate 210 at the bottom of the dielectric layer TSV hole 230, so as to implement subsequent TSV insulation and metallization by using a structure with a large hole and a small hole. The structure of the big hole sleeve is small, so that the TSV density is limited by the size of the big hole on the medium layer, and the TSV structure with high density and small size is difficult to achieve.
The invention provides a high-density TSV structure of an active chip and a manufacturing method thereof, aiming at the problems that the size is larger and high-density and small-size cannot be realized due to the fact that a large TSV structure is sleeved with a small TSV structure in the prior art for manufacturing the TSV of the active chip, and at least part of the problems in the prior art are solved.
Disclosure of Invention
Aiming at the problems that the size is large and high density and small size cannot be achieved due to the fact that a large TSV structure and a small TSV structure are used for manufacturing an active chip TSV in the prior art, the invention provides the active chip high-density TSV structure which comprises the following components in parts by weight:
a silicon substrate;
the first dielectric layer is arranged on the upper surface of the silicon substrate;
the high-density silicon through hole open slot penetrates through the first medium layer and exposes the silicon substrate below the first medium layer;
the second dielectric layer covers the high-density silicon through hole open slot and the high-density silicon through hole;
the high-density through silicon via extends from the groove bottom of the high-density through silicon via open groove to the inside of the silicon substrate; and
a high-density through-silicon-via interconnect structure electrically connected to the high-density through-silicon-via.
In one embodiment of the present invention, the material of the first dielectric layer is silicon dioxide, silicon oxide, silicon nitride or a multilayer composite dielectric layer, and the thickness is 5 micrometers to 10 micrometers.
In an embodiment of the invention, the second dielectric layer covers an upper surface of the first dielectric layer and in the high-density through silicon via opening groove and the high-density through silicon via.
In one embodiment of the invention, the number of the high-density through silicon vias is M, wherein M is more than or equal to 2.
In one embodiment of the present invention, the high-density through-silicon-via penetrates the silicon substrate.
In one embodiment of the present invention, the high-density through-silicon-via interconnect structure further comprises an interlayer via penetrating through the second dielectric layer and electrically connected to the high-density through-silicon-via, and a re-layout wiring layer disposed on the surface or inside of the second dielectric layer.
In one embodiment of the present invention, a diameter of the interlayer via is substantially the same as a diameter of the high-density through-silicon via.
According to another embodiment of the present invention, a method for manufacturing a high-density TSV structure of an active chip is provided, which includes:
providing an active chip, wherein the active chip is provided with a first dielectric layer and a silicon substrate;
etching the first dielectric layer to form a high-density silicon through hole open slot;
forming a high-density silicon through hole from the bottom surface of the high-density silicon through hole open slot to the interior of the silicon substrate;
insulating the high-density silicon through hole, namely covering silicon oxide, silicon nitride or a multilayer composite dielectric layer, namely a second dielectric layer, in the high-density silicon through hole, on the groove bottom surface and on the surface of the first dielectric layer;
filling high-density silicon through hole metal;
removing metal layers on the surface and the side surface and the bottom surface of the groove of the high-density silicon through hole open slot, and only keeping metal in the high-density silicon through hole;
and finally, re-laying the wiring layer on the surface of the second dielectric layer.
In another embodiment of the invention, the high-density through silicon vias penetrate through the silicon substrate, and the number of the high-density through silicon vias is N, wherein N is more than or equal to 2.
In another embodiment of the present invention, after forming the second dielectric layer and performing metallization, performing chemical mechanical polishing and wet etching to remove the metal on the second dielectric layer, and only the metal in the high-density TSV is retained.
The invention provides a high-density TSV structure of an active chip and a manufacturing method thereof. The active chip high-density TSV structure provided by the invention avoids the problem that the TSV metallization is influenced by the olecranon appearance of the TSV through holes formed in one step; the TSV interconnection density is not limited by the size of the opening on the insulating layer, and high-density TSV through holes and metallization filling can be achieved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a schematic diagram of a TSV structure 100 for one-time via formation of an active chip of the prior art.
Fig. 2 shows a schematic diagram of a TSV structure 200 for active chip secondary via formation in the prior art.
Fig. 3 illustrates a cross-sectional schematic view of an active chip high density TSV structure 300 formed in accordance with an embodiment of the present invention.
Fig. 4 illustrates a cross-sectional schematic view of an active-chip high-density TSV structure 400 formed in accordance with yet another embodiment of the invention.
Fig. 5A-5G illustrate cross-sectional views of a process for forming the active-chip high-density TSV structure 300 according to an embodiment of the invention.
Fig. 6 shows a flow chart 600 of a method of forming the active chip high density TSV structure 300 according to an embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a high-density TSV structure of an active chip and a manufacturing method thereof. The active chip high-density TSV structure provided by the invention avoids the problem that the TSV metallization is influenced by the olecranon appearance of the TSV through holes formed in one step; the TSV interconnection density is not limited by the size of the opening on the insulating layer, and high-density TSV through holes and metallization filling can be achieved.
An active chip high density TSV structure according to an embodiment of the invention is described in detail below with reference to fig. 3. Fig. 3 illustrates a cross-sectional schematic view of an active chip high density TSV structure 300 formed in accordance with an embodiment of the present invention. As shown in fig. 3, the active chip high-density TSV structure 300 further includes a silicon substrate 310, a first dielectric layer 320, a high-density through-silicon via opening slot 330, a second dielectric layer 340, a high-density through-silicon via 350, and a high-density through-silicon via interconnection structure 360.
The silicon substrate 310 is a wafer substrate of an active chip. In one embodiment of the present invention, the silicon substrate 310 is a wafer level substrate, i.e., the silicon substrate 310 has not been die cut. Typically, the silicon substrate 310 is a 200 mm diameter wafer or a 300 mm diameter wafer.
A first dielectric layer 320 is disposed on the upper surface of the silicon substrate 310. In one embodiment of the present invention, the material of the first dielectric layer 320 is silicon dioxide, and the thickness is between 5 microns and 10 microns. In another embodiment of the present invention, the first dielectric layer 320 may also be a silicon nitride or other insulating dielectric layer, or a multi-layer composite dielectric layer made of silicon nitride, silicon oxide, or the like.
The high-density through-silicon via opening groove 330 is disposed at a corresponding position of the first dielectric layer 320, and the high-density through-silicon via opening groove 330 penetrates through the first dielectric layer 320 to expose the silicon substrate 310. In one embodiment of the present invention, the high-density through-silicon-via open slots 330 may be elongated slots, square slots, and other geometric slots.
The second dielectric layer 340 is disposed in the high-density through silicon via opening slot 330, and the second dielectric layer 340 may be an inorganic insulating dielectric layer such as silicon oxide, silicon nitride, or an organic insulating dielectric layer such as PI, resin, or the like. In one embodiment of the present invention, the second dielectric layer 340 covers the surface of the first dielectric layer 320 and fills the high-density through-silicon via open trench 330 and the TSV hole inner wall.
The high-density through-silicon vias 350 are disposed in the silicon substrate 310 and extend from the bottom of the high-density through-silicon via opening groove 330 to the inside of the silicon substrate 310, the number of the high-density through-silicon vias 350 is plural, and the sizes of the plural high-density through-silicon vias may be the same or different. In one embodiment of the present invention, the conductive fill material of the high-density through silicon vias 350 is copper metal.
A high-density through-silicon via interconnect structure 360 is disposed in and on the surface of the second dielectric layer 340 and electrically connected to the high-density through-silicon vias 350, functioning as an electrical and/or signal interconnect with the high-density through-silicon vias 350. In one embodiment of the present invention, the high-density through-silicon-via interconnect structure 360 further comprises an interlayer via penetrating the second dielectric layer 340 and electrically connected to the high-density through-silicon-via 350, and a re-layout wiring layer disposed on the surface of or inside the second dielectric layer 340, wherein the re-layout wiring layer may be a single layer or multiple layers, and the cross-sectional diameter of the interlayer via is substantially the same as the diameter of the high-density through-silicon-via 350. In yet another embodiment of the present invention, the cross-sectional diameter of the interlayer via may be smaller or slightly larger than the diameter of the high-density through silicon via 350.
An active chip high density TSV structure according to yet another embodiment of the present invention is described in detail below with reference to fig. 4. Fig. 4 illustrates a cross-sectional schematic view of an active-chip high-density TSV structure 400 formed in accordance with yet another embodiment of the invention. As shown in fig. 4, the active chip high-density TSV structure 400 further includes a silicon substrate 410, a first dielectric layer 420, a high-density through-silicon via opening slot 430, a second dielectric layer 440, a high-density through-silicon via 450, and a high-density through-silicon via interconnection structure 460.
The active-chip high-density TSV structure 400 differs from the foregoing active-chip high-density TSV structure 300 in that: the first is that the second dielectric layer 440 is only filled inside the high-density through silicon via opening groove 430 and does not cover the surface of the first dielectric layer 420; the second is that the high-density through-silicon via 450 penetrates the bottom surface of the silicon substrate 410.
A method of forming the active-chip high-density TSV structure 300 according to an embodiment of the invention is described in detail below with reference to fig. 5A to 5G and fig. 6. Fig. 5A-5G illustrate cross-sectional views of a process for forming the active-chip high-density TSV structure 300 according to an embodiment of the invention; fig. 6 shows a flow chart 600 of a method of forming the active chip high density TSV structure 300 according to an embodiment of the invention.
First, in step 610, as shown in fig. 5A, an active chip with a first dielectric layer 520 and a silicon substrate 510 is provided. Wherein the active devices of the active die are fabricated near the surface of the silicon substrate 510 adjacent to the first dielectric layer 520. In one embodiment of the present invention, the first dielectric layer 520 has a thickness of about 5 to 10 microns and the silicon substrate 510 has a thickness of about 50 to 150 microns. In another embodiment of the present invention, the material of the first dielectric layer 520 is silicon dioxide.
Next, in step 620, as shown in fig. 5B, a high-density through-silicon via opening groove 530 is etched in the first dielectric layer 520, and the high-density through-silicon via opening groove 530 penetrates through the first dielectric layer 520. In one embodiment of the present invention, the shape of the high-density tsv open slot 530 may be rectangular, square, or other polygonal shapes. In an embodiment of the present invention, the first dielectric layer 520 is made of silicon dioxide, and an etching mask (e.g., a photoresist etching mask layer) is formed by photolithography on the first dielectric layer 520, and then the high-density through-silicon via opening groove 530 is formed by hydrofluoric acid (HF) wet etching.
Then, in step 630, as shown in fig. 5C, high-density through-silicon vias 540 are formed at the bottom surfaces of the high-density through-silicon via opening grooves 530. In one embodiment of the present invention, high density through silicon vias 540 are formed by a patterned etch, such as patterned by a bosch etch process.
Next, at step 640, high density through silicon via metal 550 fill is performed, as shown in fig. 5D. In one embodiment of the present invention, the plating is formed by a plating seed layer deposition, plating window lithography, plating, photoresist removal, and the like.
Then, in step 650, as shown in fig. 5E, the plating seed layer and the trench bottom metal layer of the high-density through-silicon via opening 530 are removed. In an embodiment of the present invention, the removal of the plating seed layer and the bottom metal layer of the trench may be performed by a wet etching process, so as to achieve the conductive isolation of the high-density through silicon via 550.
Next, at step 650, as shown in fig. 5F, a second dielectric layer 560 is formed that fills the high density through silicon via opening 530 and covers the upper surface of the first dielectric layer 520. In an embodiment of the present invention, the material of the second dielectric layer 560 is an inorganic insulating material such as silicon dioxide and silicon nitride, or an organic insulating material such as PI and resin. In yet another embodiment of the present invention, the second dielectric layer 560 is only filled in the high-density through-silicon via opening slot 530 and does not cover the upper surface of the first dielectric layer 520, and the specific method includes removing the second dielectric layer 560 on the upper surface of the first dielectric layer 520 by Chemical Mechanical Polishing (CMP) after the second dielectric layer 560 is filled in the high-density through-silicon via opening slot 530 and covers the upper surface of the first dielectric layer 520, so as to achieve planarization of the upper surfaces of the second dielectric layer 560 and the first dielectric layer 520.
Finally, in step 660, as shown in fig. 5G, a high-density through-silicon-via interconnect structure 570 is formed on the surface of the active chip and in the second dielectric layer 560, and the high-density through-silicon-via interconnect structure 570 is electrically connected to the high-density through-silicon-via 550. In one embodiment of the present invention, the high-density through-silicon-via interconnect structure 570 further comprises an interlayer via connected to the high-density through-silicon-via 550 and a re-layout wiring layer on the upper surface of the active chip.
Based on the high-density TSV structure of the active chip and the manufacturing method thereof, firstly, a high-density silicon through hole open slot is manufactured on a medium layer of a high-density TSV region of the active chip, then a high-density silicon through hole is formed in the high-density silicon through hole open slot, then high-density silicon through hole insulation and metallization filling are carried out, and finally, a high-density silicon through hole interconnection structure is manufactured. The active chip high-density TSV structure provided by the invention avoids the problem that the TSV metallization is influenced by the olecranon appearance of the TSV through holes formed in one step; the TSV interconnection density is not limited by the size of the opening on the insulating layer, and high-density TSV through holes and metallization filling can be achieved.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. An active chip high density TSV structure comprising:
a silicon substrate;
the first dielectric layer is arranged on the upper surface of the silicon substrate, and an active device of an active chip is manufactured near the surface of the silicon substrate close to the first dielectric layer;
the high-density silicon through hole open slot penetrates through the first medium layer and exposes the silicon substrate below the first medium layer;
the second dielectric layer is arranged in the high-density silicon through hole open slot;
the high-density silicon through hole extends from the groove bottom of the high-density silicon through hole open groove to the inside of the silicon substrate; and
a high-density through-silicon-via interconnect structure electrically connected to the high-density through-silicon-via.
2. The active-chip high-density TSV structure of claim 1, wherein the material of said first dielectric layer is silicon dioxide, silicon oxide, silicon nitride or a multi-layer composite dielectric layer with a thickness of 5 to 10 microns.
3. The active-chip high-density TSV structure of claim 1, wherein said second dielectric layer covers an upper surface of said first dielectric layer.
4. The active-chip high-density TSV structure of claim 1, wherein the number of the high-density through silicon vias is M, wherein M ≧ 2.
5. The active-chip high-density TSV structure of claim 1, wherein said high-density through-silicon-vias extend through said silicon substrate.
6. The active-chip high-density TSV structure of claim 1, wherein said high-density through-silicon-via interconnect structure further comprises an inter-level via through said second dielectric layer, electrically connected to said high-density through-silicon-via, and a re-routed wiring layer disposed on a surface of or within said second dielectric layer.
7. The active-chip high-density TSV structure of claim 6, wherein a diameter of said inter-layer via is substantially the same as a diameter of said high-density through-silicon via.
8. A manufacturing method of an active chip high-density TSV structure comprises the following steps:
providing an active chip, wherein the active chip is provided with a first dielectric layer and a silicon substrate, and an active device of the active chip is manufactured near the surface of the silicon substrate close to the first dielectric layer;
etching the first dielectric layer to form a high-density silicon through hole open slot;
forming a high-density silicon through hole from the bottom surface of the high-density silicon through hole open slot to the interior of the silicon substrate;
insulating the high-density silicon through hole, namely covering silicon oxide, silicon nitride or a plurality of layers of composite dielectric layers, namely a second dielectric layer, in the high-density silicon through hole, on the groove bottom surface and on the surface of the first dielectric layer;
then, high-density silicon through hole metal filling is carried out;
removing metal layers on the surface and the side surface and the bottom surface of the groove of the high-density silicon through hole open slot, and only keeping metal in the high-density silicon through hole;
and finally, re-laying the wiring layer on the surface of the second dielectric layer.
9. The method for manufacturing the active chip high-density TSV structure of claim 8, wherein the high-density through-silicon-vias penetrate through the silicon substrate, and the number of the high-density through-silicon-vias is N, wherein N is greater than or equal to 2.
10. The method of claim 8, wherein after forming the second dielectric layer and metalizing, further comprising performing chemical mechanical polishing and wet etching removal on the metal on the second dielectric layer, leaving only the metal in the high-density TSV.
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