CN111834201A

CN111834201A - Semiconductor process

Info

Publication number: CN111834201A
Application number: CN201910309354.7A
Authority: CN
Inventors: 李天慧; 王科
Original assignee: SiEn Qingdao Integrated Circuits Co Ltd
Current assignee: SiEn Qingdao Integrated Circuits Co Ltd
Priority date: 2019-04-17
Filing date: 2019-04-17
Publication date: 2020-10-27

Abstract

The invention provides a semiconductor process method, which comprises the following steps: 1) providing a substrate; 2) forming a material layer to be etched on a substrate, wherein the upper surface of the material layer has a height difference; 3) forming an anti-reflection layer on the upper surface of the material layer to be etched; 4) forming a positive photoresist layer on the upper surface of the anti-reflection layer; 5) performing selective exposure to form an exposed region and an unexposed region on the positive photoresist layer; 6) performing negative development to remove the positive photoresist in the unexposed region; 7) forming an acidified region on a surface of the positive photoresist layer, the acidified region comprising a polymer reactive with a silicon-containing gas; 8) treating the acidized region by adopting a silicon-containing gas so as to convert the acidized region into a mask layer; 9) and removing the anti-reflection layer and the material layer to be etched. The invention can be effectively used for manufacturing ultra-fine patterns with high step difference, is beneficial to ensuring the dimensional precision of devices and improving the pattern quality, and further is beneficial to improving the process production yield and reducing the production cost.

Description

Semiconductor process

Technical Field

The invention belongs to the field of semiconductor manufacturing, and particularly relates to a semiconductor process method.

Background

In a semiconductor chip manufacturing process, the upper surface of a material layer to be etched formed on a substrate has a height difference due to various reasons, that is, the upper surface of a partial region of the material layer to be etched is higher than the height of other regions of the same layer, so that a step height (step height) is formed at a height intersection. The existence of the step difference can increase difficulty for the process, for example, uneven film deposition is easily caused in the film deposition process, and the difference of the etching rate is easily caused in the etching process. The step difference has a significant adverse effect on the photolithography process, for example, the step difference easily causes problems such as defocusing (defocus), insufficient resolution (sub-resolution), and an influence on the etch stop effect (etchprevition) of the photoresist during the photolithography process, thereby reducing the production yield.

With the shrinking of the feature size of the semiconductor device and the increasing of the device integration level, the technical challenge in the process of manufacturing the high-density ultrafine pattern is also increased, and the step difference phenomenon becomes a key factor for restricting the further improvement of the device integration level and the further reduction of the feature size of the semiconductor device. How to reduce the adverse effect of the step difference on the process, especially the adverse effect on the photolithography process, has become a problem that semiconductor device manufacturers need to solve.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor process method for solving the problems of defocusing, resolution reduction, etching blockage, etc. in the photolithography process caused by steps in the prior art.

To achieve the above and other related objects, the present invention provides a semiconductor process method, comprising:

1) providing a substrate;

2) forming a material layer to be etched on the substrate, wherein the upper surface of the material layer to be etched has a height difference;

3) forming an anti-reflection layer on the upper surface of the material layer to be etched;

4) forming a positive photoresist layer on the upper surface of the anti-reflection layer;

5) selectively exposing the positive photoresist layer to form an exposed region and an unexposed region on the positive photoresist layer;

6) carrying out negative development on the exposed positive photoresist layer to remove the positive photoresist in the unexposed area;

7) forming an acidified region on the surface of the positive photoresist layer in the exposed region, the acidified region comprising a polymer reactive with a silicon-containing gas;

8) treating the acidizing area by adopting a silicon-containing gas so as to convert the acidizing area into a mask layer;

9) and removing the anti-reflection layer and the material layer to be etched in the unexposed area according to the mask layer.

Optionally, a step of forming an etching barrier layer on the upper surface of the substrate is further included between step 1) and step 2), and the material layer to be etched is formed on the upper surface of the etching barrier layer.

Optionally, the material layer to be etched includes a region to be etched and a non-etched region, and a height of an upper surface of the non-etched region is higher than a height of an upper surface of the region to be etched.

Optionally, baking the positive photoresist layer of the exposed region in the step 7) to form the acidified region.

More optionally, the baking temperature is from 100 ℃ to 150 ℃.

Optionally, the silicon-containing gas comprises monosilane.

Optionally, the mask layer comprises a silicon oxide layer.

Optionally, in the step 9), the antireflection layer in the unexposed area is removed by oxygen plasma etching.

Optionally, the semiconductor process method further comprises a step of removing the mask layer, the positive photoresist layer and the anti-reflection layer after the step 9).

Optionally, the upper surface of the anti-reflection layer formed in the step 3) has a height difference, and the upper surface of the positive photoresist layer is a horizontal plane.

As described above, the semiconductor process method of the present invention has the following advantageous effects:

the invention adopts the anti-reflection layer to reduce the step difference in the device structure, simultaneously adopts the positive photoresist to carry out exposure on the top to ensure higher pattern resolution, then carries out negative development to remove the photoresist of the unexposed area, and carries out modification treatment on the exposed photoresist to be used as a mask for subsequent etching. The invention can be effectively used for manufacturing ultra-fine patterns with high step difference, is beneficial to ensuring the dimensional precision of devices and improving the pattern quality, and is further beneficial to improving the process production yield. The semiconductor process method can effectively reduce the manufacturing difficulty of the ultrafine pattern and reduce the production cost.

Drawings

FIG. 1 is a flow chart of a semiconductor processing method of the present invention.

Fig. 2 to 11 are schematic cross-sectional views of steps of the semiconductor processing method according to the present invention.

Description of the element reference numerals

11 substrate

12 layer of material to be etched

121 region to be etched

122 non-etched area

13 antireflection layer

14 positive photoresist layer

141 exposure area

142 non-exposure area

15 mask layer

17 etch stop layer

21 inclined plane

31 mask

h1 height difference of material layer to be etched

Angle theta

S1-S9

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Referring to fig. 1, the present invention provides a semiconductor process method, which includes the following steps:

1) providing a substrate;

The steps will be described in detail with reference to the accompanying drawings.

Referring to step S1 in fig. 1 and fig. 2, a substrate 11 is provided.

By way of example, the substrate 11 may be any substrate that can support the material layer 12 to be etched, such as a semiconductor substrate, a glass substrate, or the like; preferably, the substrate 11 may be, but is not limited to, a semiconductor substrate, such as a commonly used silicon substrate, germanium substrate, sapphire substrate, or the like, and more specifically, the substrate 11 may be a bare wafer or a wafer having other device structures already formed therein, and the substrate 11 may be cleaned in advance to improve the subsequent process yield.

In step 2), please refer to step S2 and fig. 3 in fig. 1, forming a material layer 12 to be etched on the substrate 11, wherein the upper surface of the material layer 12 to be etched has a height difference h 1; the height difference h1 may be a structure such as a groove formed in the substrate 11, so that the material layer 12 to be etched is directly formed on the upper surface of the substrate 11 and then the upper surface of the material layer 12 to be etched has a height difference; the material layer 12 to be etched may be formed on the upper surface of the substrate 11, and a height difference is formed in different regions of the material layer 12 to be etched according to a device structure, and a specific value of the height difference h1 is different according to a device structure, and may be from tens of nanometers to hundreds of nanometers or even thousands of nanometers, but the larger the value of the height difference h1 is, the larger the adverse effect on the photolithography process is, and especially, the higher the device integration level is, the smaller the critical dimension (CD for short) of the device is, the more prominent the adverse effect is, and the present invention can effectively overcome the adverse effect caused by the height difference.

In this embodiment, as an example, the material layer 12 to be etched includes a region 121 to be etched and a non-etched region 122, the region 121 to be etched is a region where a required pattern structure needs to be formed by etching, and in this example, the height of the upper surface of the non-etched region 122 is higher than the height of the upper surface of the region 121 to be etched, that is, the upper surface of the material layer 12 to be etched is in a step-shaped abrupt change at a boundary between the region 121 to be etched and the non-etched region 122, and the abrupt change is in a step-shaped vertical shape, which is very likely to cause an exposure defect. Of course, the specific position and shape of the step may be selected according to the requirements of different device structures, and the embodiment is not limited strictly.

The material of the material layer 12 to be etched is different according to the structure of the device, for example, if a contact hole structure needs to be formed, the material layer 12 to be etched may include a polysilicon layer or a dielectric layer; in other examples, the material layer 12 to be etched may also be a metal layer or other material layers, and is not limited in particular. The method for forming the material layer 12 to be etched is different according to the material of the material layer 12 to be etched, for example, a vapor deposition process is preferred in the case of a polysilicon layer, and a physical vapor deposition or chemical vapor deposition process can be selected in the case of a metal layer.

In an example (please continue to refer to fig. 3), a step of forming an etch stop layer 17 on the upper surface of the substrate 11 is further included between the step 1) and the step 2), and the material layer to be etched 12 is formed on the upper surface of the etch stop layer 17.

As an example, the etching stop layer 17 may be any material layer having a high etching selectivity ratio with respect to the material layer to be etched 12 formed subsequently, that is, under the same etching conditions, the etching rate of the material layer to be etched 12 and the etching rate of the etching stop layer 17 exhibit a significant difference. The material of the etching stop layer 17 can be selected according to the material of the material layer 12 to be etched, for example, when the material layer 12 to be etched is a polysilicon layer, the etching stop layer 17 can be one of a titanium nitride layer, a silicon nitride layer, or the like, or a composite film composed of multiple material layers. In a further example, a buffer layer, such as a silicon dioxide layer, may also be formed between the etch stop layer 17 and the substrate 11 to protect the substrate 11, enhance adhesion between the etch stop layer 17 and the substrate 11, and reduce stress effects. It should be noted that the etching rates of the two materials may present different etching rate differences under different etching conditions, so that the material selection of the etching barrier layer 17 should be selected not only according to the difference of the material layer 12 to be etched, but also according to the difference of the subsequent etching conditions, or the subsequent etching conditions should be set according to the different materials of the etching barrier layer 17 and the material layer 12 to be etched. In addition, the material selection of the etching stop layer 17 needs to consider the structure of the material at the bottom of the etching stop layer 17, for example, in this embodiment, the etching stop layer 17 needs to have a high etching selection ratio with the substrate 11. The thickness of the etching barrier layer 17 is set according to the difference of the material and/or the difference of the process, and is usually between 100 nm and 200nm, so as to reduce the process time for forming the etching barrier layer 17 and removing the etching barrier layer by subsequent etching as much as possible, and reduce the thickness of the etching barrier layer 17 as much as possible to reduce the size of the device.

In step 3), referring to step S3 in fig. 1 and fig. 4, an anti-reflective layer 13 (BARC) is formed on the upper surface of the material layer 12 to be etched. The anti-reflection layer 13 not only reduces the phenomena of light reflection, standing wave and the like in the subsequent photoetching process to improve the exposure precision and the pattern resolution, but also effectively reduces the adverse effect caused by the height difference h1 of the material layer 12 to be etched by introducing the anti-reflection layer 13. The material of the anti-reflection layer 13 can be selected according to the needs, such as organic siloxane or high carbon-containing polymer, or can be other material layers, and is not limited in particular, and it is important to match with other material layers, such as the material of the positive photoresist layer 14, and to be easily removed in the subsequent process. In this embodiment, because the positive photoresist is selected, the anti-reflective layer 13 is preferably made of an alkali-soluble material, for example, a mixture including a linear terpolymer, a cross-linking agent, a photoacid generator (PAG for short) and a quencher is selected, so that the development residue can be effectively avoided, and the anti-reflective layer has the advantages of good line steepness, high resolution and the like. And as an example, the upper surface of the anti-reflection layer 13 has a height difference which is preferably smaller than the height difference h1 of the material layer 12 to be etched, in other words, the height difference h1 of the material layer 12 to be etched is not completely offset by the anti-reflection layer 13. More preferably, in this embodiment, the anti-reflection layer 13 forms a gentle slope 21 corresponding to the step jump of the material layer 12 to be etched, and the inclination angle θ of the slope 21 is preferably an obtuse angle, and more preferably between 135 ° and 150 ° (inclusive), because this angle interval is easier to be implemented in the process, and the height difference of the anti-reflection layer 13 is easier to be set by setting the angle. The provision of the inclined surface 21 is advantageous first to improve process tolerance, since the antireflection layer 13 is generally formed by spin coating, so that the spin coating angle can be adjusted during spin coating by providing the inclined surface 21 to avoid the generation of a spin coating blind area; meanwhile, the existence of the inclined surface 21 enables the anti-reflection layer 13 to have certain tortuosity and larger surface area, so that the anti-reflection layer 13 can be better attached to the positive photoresist layer 14 coated subsequently, and the subsequent photoetching process yield can be improved. The maximum thickness of the anti-reflection layer 13 and the height difference of the upper surface of the anti-reflection layer 13 are different according to the height difference h1 of the material layer 12 to be etched, the specific material of the positive photoresist layer 14 and the process requirements, which will be explained in the following.

Next, referring to step S4 and fig. 5 in fig. 1, a positive photoresist layer 14 is formed on the upper surface of the anti-reflection layer 13, and the upper surface of the positive photoresist layer 14 is preferably horizontal, which is beneficial to improve the exposure accuracy. The positive photoresist layer 14 may be a commercially available positive photoresist material generally composed of a polymer containing a phenolic resin, a photosensitive compound such as a photoacid generator, and a solvent such as propylene glycol-methyl ethyl ether. The positive photoresist has good contrast and good resolution, so that the method is particularly suitable for manufacturing ultra-fine patterns with the line width of less than 28 nm. The positive photoresist layer 14 may be formed by spin coating, and the maximum thickness thereof may be 300nm to 2000 nm. In this embodiment, because the upper surface of the anti-reflection layer 13 has a height difference, a height difference is formed on the lower surface of the positive photoresist layer 14, which is connected to the anti-reflection layer 13, or the positive photoresist layer 14 has a thickness difference, and the sum of the thickness difference and the height difference of the anti-reflection layer 13 is equal to the height difference h1 of the material layer 12 to be etched, that is, the height difference h1 of the material layer 12 to be etched is offset by the height difference of the anti-reflection layer 13 and the thickness difference of the positive photoresist layer 14, so as to avoid the adverse effect of the step difference on the photolithography process. In the case that the height difference h1 of the material layer 12 to be etched is relatively large, the height difference is preferably offset by the height difference of the anti-reflection layer 13 as much as possible, for example, in the case that the height difference h1 of the material layer 12 to be etched is greater than 2000nm, the height difference of the anti-reflection layer 13 is greater than one half of h1, that is, the maximum thickness of the positive photoresist layer 14 is reduced as much as possible to minimize the use of positive photoresist while ensuring that the minimum coating thickness (for example, 300nm) of the positive photoresist layer 14 corresponding to the region 121 to be etched (i.e., corresponding to the region where the desired pattern needs to be formed) is maintained, so as to reduce the production cost, and at the same time, the lithography precision is improved by reducing the thickness difference of the positive photoresist layer 14 (the thickness difference is preferably greater than zero). It should be noted that, in this example, the thinner region of the positive photoresist layer 14 corresponds to the non-etching region 122 of the material layer 12 to be etched. In addition, as an example, a top anti-reflective coating (not shown) may be further formed on the upper surface of the positive photoresist layer 14 to further improve the photolithography precision.

Referring next to step S5 in fig. 1 and fig. 6 and 7, the positive photoresist layer 14 is selectively exposed to form exposed regions 141 and unexposed regions 141 on the positive photoresist layer 14.

As an example, the selective exposure is usually performed by using a mask 31(mask), an opening is formed on the mask 31 to correspond to the exposure region 141, and the exposure region 141 usually corresponds to a position where a pattern to be formed is located. The influence on the antireflection layer 13 is to be minimized when the exposure energy is set. In the present embodiment, as an example, the exposure energy is the minimum exposure energy required for the thickness of the positive photoresist layer 14 corresponding to the region to be etched 121.

After exposure, the positive photoresist in the exposed areas 141 degrades and can be readily dissolved in an alkaline developer, such as TMAH (tetramethylammonium hydroxide), which is commonly used. In the prior art, a positive photoresist is developed by using an alkaline aqueous developing solution after being exposed. However, in the present invention, step S6 in fig. 1 is performed after exposure, and Negative Tone Developer (NTD) is performed on the exposed positive photoresist layer 14 to remove the positive photoresist in the unexposed area 141, more specifically, the present invention uses an organic solvent negative developer, such as xylene, to develop the exposed positive photoresist layer 14, thereby performing image reversal, which is beneficial to further improving image contrast, and is more beneficial to preparing ultra-fine and highly integrated patterns, and in addition, organic solvents such as butyl acetate, ethanol or trichloroethylene may be used to clean the exposed positive photoresist layer 14 to remove residues after development, so as to improve the yield of the process. After the negative development, the positive photoresist in the non-exposed regions 142 is removed, and the resulting structure is shown in FIG. 7.

Then, referring to step S7 in fig. 1 and fig. 8, an acidified region 15 is formed on the surface of the positive photoresist layer 14 in the exposed region 141, wherein the acidified region 15 comprises a polymer capable of reacting with a silicon-containing gas.

As an example, this step may be performed by baking, for example, the structure obtained in step S6 may be placed in a baking device (e.g., a baking oven) to be baked at a temperature of 100 ℃ to 150 ℃, because the inventors found that baking in this temperature range can avoid the resolution reduction caused by the photoresist melting due to too high temperature, and can avoid the poor adhesion and corrosion resistance of the photoresist due to too low temperature. The baking time is set according to the thickness and material of the photoresist, and is usually 1-2 minutes. Since the positive photoresist contains a photoacid generator, hydrogen ions (H) are decomposed during baking⁺) The hydrogen ions are dissociated to the surface of the positive photoresist layer 14 to form the acidified region 15 on the surface of the positive photoresist layer 14, and the thickness of the acidified region 15 is generally less than the maximum thickness of the positive photoresist layer 14.

With continued reference to step S8 of fig. 1 and fig. 9, the acidified region 15 is treated with a silicon-containing gas to convert the acidified region 15 into the mask layer 16. The silicon-containing gas is preferably monosilane, but in other examples, the silicon-containing gas may be other gases such as disilane, and importantly, contains a silicon component.

This step may be performed, for example, in a plasma chamber, and a silicon-containing gas is introduced into the reaction chamber at a suitable reaction temperature, the silicon-containing gas reacts with the acidified region 15, and silicon atoms therein penetrate into the acidified region 15 to modify the material of the acidified region 15 to form, for example, a silicon oxide layer or a silicon carbide layer (which may be different depending on the silicon-containing gas), i.e., the mask layer 16. The mask layer 16 can have a good etching blocking effect, thereby being beneficial to improving the image resolution and the etching precision.

Referring to step S9 of fig. 1 and fig. 10, the antireflection layer 13 and the material layer to be etched 12 in the unexposed area 141 are removed according to the mask layer 16.

The specific process of this step varies according to the specific materials of the anti-reflection layer 13 and the material layer 12 to be etched. For example, if the anti-reflection layer 13 is an organic siloxane or a polymer with high carbon content, the step of removing the anti-reflection layer 13 may be performed in the same step as the step S8, for example, in the same plasma chamber, by introducing oxygen to remove the anti-reflection layer 13; and the etching of the layer of material 12 to be etched may continue within the chamber to form the desired pattern.

Under the condition that the etching barrier layer 17 is formed, the method further includes a step of removing the etching barrier layer 17 after the etching of the material layer 12 to be etched is completed, and the substrate 11 is exposed at a position corresponding to the non-exposure region 142 after the etching. Since the process of removing the etch stop layer 17 is well known to those skilled in the art, it will not be expanded in detail.

Finally, the mask layer 16, the positive photoresist layer 14 and the anti-reflection layer 13 in the exposure region 141 are removed to obtain the structure shown in fig. 11. The manner of removing the mask layer 16 may be different according to the material of the mask layer 16, for example, if the mask layer 16 is silicon oxide, hydrogen fluoride gas may be used for removal, and oxygen plasma may be used for removal of the positive photoresist layer 14 and the anti-reflection layer 13, which is well known to those skilled in the art and is not described in detail for brevity.

In summary, the present invention provides a semiconductor process method, which includes the following steps: 1) providing a substrate; 2) forming a material layer to be etched on the substrate, wherein the upper surface of the material layer to be etched has a height difference; 3) forming an anti-reflection layer on the upper surface of the material layer to be etched; 4) forming a positive photoresist layer on the upper surface of the anti-reflection layer; 5) selectively exposing the positive photoresist layer to form an exposed region and an unexposed region on the positive photoresist layer; 6) carrying out negative development on the exposed positive photoresist layer to remove the positive photoresist in the unexposed area; 7) forming an acidified region on the surface of the positive photoresist layer in the exposed region, the acidified region comprising a polymer reactive with a silicon-containing gas; 8) treating the acidizing area by adopting a silicon-containing gas so as to convert the acidizing area into a mask layer; 9) and removing the anti-reflection layer and the material layer to be etched in the unexposed area according to the mask layer. The invention adopts the anti-reflection layer to reduce the step difference in the device structure, simultaneously adopts the positive photoresist to carry out exposure on the top to ensure higher pattern resolution, then carries out negative development to remove the photoresist of the unexposed area, and carries out modification treatment on the exposed photoresist to be used as a mask for subsequent etching. The invention can be effectively used for manufacturing ultra-fine patterns with high step difference, is beneficial to ensuring the dimensional precision of devices and improving the pattern quality, and is further beneficial to improving the process production yield. The semiconductor process method can effectively reduce the manufacturing difficulty of the ultrafine pattern and reduce the production cost.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A semiconductor processing method is characterized by comprising the following steps:

1) providing a substrate;

2. The semiconductor processing method of claim 1, wherein: the method also comprises a step of forming an etching barrier layer on the upper surface of the substrate between the step 1) and the step 2), wherein the material layer to be etched is formed on the upper surface of the etching barrier layer.

3. The semiconductor processing method of claim 1, wherein: the material layer to be etched comprises a region to be etched and a non-etched region, wherein the height of the upper surface of the non-etched region is higher than that of the upper surface of the region to be etched.

4. The semiconductor processing method of claim 1, wherein: baking the positive photoresist layer of the exposed region in the step 7) to form the acidified region.

5. The semiconductor processing method of claim 4, wherein: the baking temperature is 100-150 ℃.

6. The semiconductor processing method of claim 1, wherein: the silicon-containing gas includes monosilane.

7. The semiconductor processing method of claim 1, wherein: the mask layer includes a silicon oxide layer.

8. The semiconductor processing method of claim 1, wherein: and in the step 9), removing the anti-reflection layer in the unexposed area by adopting oxygen plasma etching.

9. The semiconductor processing method of claim 1, wherein: the semiconductor process method further comprises the step of removing the mask layer, the positive photoresist layer and the anti-reflection layer after the step 9).

10. The semiconductor processing method according to any one of claims 1 to 9, wherein: the upper surface of the anti-reflection layer formed in the step 3) has a height difference, and the upper surface of the positive photoresist layer is a horizontal plane.