CN111833819A - Pixel compensation circuit structure of active matrix organic light emitting display and display thereof - Google Patents
Pixel compensation circuit structure of active matrix organic light emitting display and display thereof Download PDFInfo
- Publication number
- CN111833819A CN111833819A CN201910326914.XA CN201910326914A CN111833819A CN 111833819 A CN111833819 A CN 111833819A CN 201910326914 A CN201910326914 A CN 201910326914A CN 111833819 A CN111833819 A CN 111833819A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pole
- light emitting
- circuit structure
- compensation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a pixel compensation circuit structure of an active matrix organic light-emitting display, which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a storage capacitor, a parasitic capacitor and a light-emitting device, wherein the first transistor is connected with the second transistor; wherein the first transistor connects the light emitting device and the sixth transistor; the second transistor is connected with the first scanning control end, the reset signal end and the fifth transistor; the third transistor is connected with the second scanning control end, the sixth transistor and the data signal end; the fourth transistor is connected with the sixth transistor and the first power supply signal end; the fifth transistor is connected with the second power supply signal end and the sixth transistor; the sixth transistor is connected with the third transistor, the fifth transistor and the fourth transistor; one end of the storage capacitor is connected with the sixth transistor and the second transistor; the parasitic capacitor is connected with the second power supply signal terminal and the second transistor. Therefore, the influence of process fluctuation on the light emitting uniformity of the display is eliminated.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a pixel circuit structure of an active matrix organic light-emitting display and a display with the pixel circuit structure.
Background
Organic Light Emitting Diodes (OLEDs), which are current type Light Emitting devices, are increasingly used in high performance display fields due to their characteristics of self-luminescence, fast response, wide viewing angle, and being fabricated on flexible substrates. The OLED is classified into a PMOLED (Passive Matrix Driving OLED) and an AMOLED (Active Matrix Driving OLED) according to a Driving method. The conventional PMOLED generally requires a reduction in driving time of a single pixel as the size of a display device increases, and thus requires an increase in transient current, resulting in a large increase in power consumption. In the AMOLED technology, each OLED scans an input current line by line through a TFT (Thin Film Transistor) switching circuit, and thus the problems can be solved well.
In the conventional AMOLED panel, a low-temperature polysilicon thin film transistor (LTPS TFT) or an Oxide thin film transistor (Oxide TFT) is often used as a TFT switching circuit. Compared with a common amorphous silicon thin film transistor (amorphous-Si TFT), the LTPS TFT and the Oxide TFT have higher mobility and more stable characteristics, and are more suitable for AMOLED display. However, due to the limitations of crystallization processes and manufacturing levels, the TFT switching circuits manufactured on the large-area glass substrate often have non-uniformity in electrical parameters such as threshold voltage, mobility, and the like, so that the threshold voltage shifts of the respective TFTs are not uniform, which causes current differences and luminance differences of the OLED display device and is perceived by human eyes; in addition, the threshold voltage of the TFT may shift even under long-time pressurization and high temperature, and the threshold shift amount of the TFT in each portion of the panel may be different due to different display screens, thereby causing a difference in display luminance, and such a difference may be related to an image displayed before, and thus may be an afterimage phenomenon.
In view of the above, the present inventors have made diligent experiments and studies to overcome the above-mentioned shortcomings in the prior art, and as a result, have provided a novel pixel compensation circuit structure for an active matrix organic light emitting display, which effectively compensates the threshold voltage shift of the TFT by using a single Nmos process to improve the uniformity of the light emitting luminance of the display device.
Disclosure of Invention
The invention aims to: the pixel circuit structure of an active matrix organic light emitting display and the display thereof are provided to solve the technical problems in the prior art.
To achieve the purpose of the present invention, a technical solution provided by the present invention is as follows:
a pixel circuit structure of an active matrix organic light emitting display, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a storage capacitor, a parasitic capacitor, and a light emitting device; the first pole of the first transistor is connected with the light-emitting device, and the second pole of the first transistor is connected with the second pole of the sixth transistor; the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor; the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the data signal end; the first pole of the fourth transistor is connected with the second pole of the sixth transistor, and the second pole of the fourth transistor is connected with the first power supply signal end; the first pole of the fifth transistor is connected with the second power supply signal end, and the second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the sixth transistor is connected with the first electrode of the third transistor, the first electrode of the sixth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the sixth transistor is connected with the first electrode of the fourth transistor; one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor; one end of the parasitic capacitor is connected with the second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; the other end of the light-emitting device is also connected with a first power signal end.
In the above possible design, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors.
In the above possible design, the first poles of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are the drains, and the second poles of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are the sources.
In the above possible design, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are amorphous indium gallium zinc oxide thin film transistors.
To achieve another objective of the present invention, another technical solution provided by the present invention is as follows:
a pixel circuit structure of an active matrix organic light emitting display, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor, a parasitic capacitor, and a light emitting device; the first pole of the first transistor is connected with the light-emitting device, and the second pole of the first transistor is connected with the second pole of the sixth transistor; the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor; the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the resetting control end; the first pole of the fourth transistor is connected with the second pole of the sixth transistor, and the second pole of the fourth transistor is connected with the first power supply signal end; the first pole of the fifth transistor is connected with the second power supply signal end, and the second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the sixth transistor is connected with the first electrode of the third transistor, the first electrode of the sixth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the sixth transistor is connected with the first electrode of the fourth transistor; the grid electrode of the seventh transistor is connected with the third scanning control end, the first pole of the seventh transistor is connected with the data signal end, and the second pole of the seventh transistor is connected with the grid electrode of the sixth transistor; one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor; one end of the parasitic capacitor is connected with the second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; the other end of the light-emitting device is also connected with a first power signal end.
In the above possible design, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are N-type transistors.
In the above possible design, the first poles of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are drains, and the second poles of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are sources.
In the above possible design, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are amorphous indium gallium zinc oxide thin film transistors.
To achieve another objective of the present invention, another technical solution provided by the present invention is as follows:
an active matrix organic light emitting display comprising: a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and a pixel compensation circuit structure configured at a portion where scanning control lines in a row form supplying control signals and signal lines in a column form supplying data signals cross each other; it includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a storage capacitor, a parasitic capacitor, and a light emitting device; the first pole of the first transistor is connected with the light-emitting device, and the second pole of the first transistor is connected with the second pole of the sixth transistor; the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor; the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the data signal end; the first pole of the fourth transistor is connected with the second pole of the sixth transistor, and the second pole of the fourth transistor is connected with the first power supply signal end; the first pole of the fifth transistor is connected with the second power supply signal end, and the second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the sixth transistor is connected with the first electrode of the third transistor, the first electrode of the sixth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the sixth transistor is connected with the first electrode of the fourth transistor; one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor; one end of the parasitic capacitor is connected with the second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; the other end of the light-emitting device is also connected with a first power signal end.
To achieve another objective of the present invention, another technical solution provided by the present invention is as follows:
an active matrix organic light emitting display comprising: a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and a pixel compensation circuit structure configured at a portion where scanning control lines in a row form supplying control signals and signal lines in a column form supplying data signals cross each other; it includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor, a parasitic capacitor, and a light emitting device; the first pole of the first transistor is connected with the light-emitting device, and the second pole of the first transistor is connected with the second pole of the sixth transistor; the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor; the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the resetting scanning control end; the first pole of the fourth transistor is connected with the second pole of the sixth transistor, and the second pole of the fourth transistor is connected with the first power supply signal end; the first pole of the fifth transistor is connected with the second power supply signal end, and the second pole of the fifth transistor is connected with the first pole of the sixth transistor; the grid electrode of the sixth transistor is connected with the first electrode of the third transistor, the first electrode of the sixth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the sixth transistor is connected with the first electrode of the fourth transistor; the grid electrode of the seventh transistor is connected with the third scanning control end, the first pole of the seventh transistor is connected with the data signal end, and the second pole of the seventh transistor is connected with the grid electrode of the sixth transistor; one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor; one end of the parasitic capacitor is connected with the second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; the other end of the light-emitting device is also connected with a first power signal end.
Drawings
FIG. 1 is a block diagram of a pixel compensation circuit according to a first embodiment of the present invention.
FIG. 2 is a timing diagram of FIG. 1 according to the present invention.
FIGS. 3-6 are timing diagrams illustrating the driving of the equalizer circuit of FIG. 1 according to the present invention.
FIG. 7 is a block diagram of a pixel compensation circuit according to a second embodiment of the present invention.
FIG. 8 is a timing diagram of FIG. 7 according to the present invention.
FIGS. 9-12 are timing diagrams illustrating the driving of the equalizer circuit of FIG. 7 according to the present invention.
Description of reference numerals: s1-a first scan control terminal, S2-a second scan control terminal, S3-a third scan control terminal, S4-a fourth scan control terminal, S6-a fifth scan control terminal, T1-a first transistor, T2-a second transistor, T3-a third transistor, T4-a fourth transistor, T5-a fifth transistor, T6-a sixth transistor, T7-a seventh transistor, C1-a storage capacitor, C2-a parasitic capacitor, an EL-light emitting device, S1-a first scan control terminal, S2-a second scan control terminal, S3-a third scan control terminal, a Vint-a reset signal terminal,
vref-reset control terminal, Vdata-data signal terminal, ELVDD-first power signal terminal, ELVSS-second power signal terminal, P1-initialization stage, P2-compensation stage, P3-data write stage, P4-light emitting stage.
Detailed Description
The following detailed description and technical contents of the present invention are described with reference to the drawings, which are provided for reference and illustration purposes only and are not intended to limit the present invention. Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents, and alternatives that may be included within the spirit and scope of the invention. In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.
Referring to fig. 1, a first embodiment of a pixel compensation circuit structure of an active matrix organic light emitting display according to the present invention includes a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and a pixel compensation circuit structure configured at a portion where scanning control lines in a row form supplying control signals and signal lines in a column form supplying data signals cross each other; the pixel circuit structure includes a plurality of transistors, a capacitor and a light emitting device, wherein gates of the transistors are respectively connected with a plurality of scan control terminals, the transistors are numbered in groups according to an order of the scan control terminals connected with the gates in the following related circuit driving descriptions of the invention, the plurality of scan control terminals include a first scan control terminal S1 and a second scan control terminal S2, and the transistors include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor C1, a parasitic capacitor C2, and a light emitting device EL.
Wherein a first pole of the first transistor T1 is connected to the light emitting device EL and a second pole thereof is connected to a second pole of the sixth transistor T6; the gate of the second transistor T2 is connected to the first scan control terminal S1, the first pole thereof is connected to the reset signal terminal Vint and the second pole thereof is connected to the first pole of the fifth transistor T5; the gate of the third transistor T3 is connected to the second scan control terminal S2, the first pole thereof is connected to the gate of the sixth transistor T6, and the second pole thereof is connected to the data signal terminal Vdata; the fourth transistor T4 has a first pole connected to the second pole of the sixth transistor T6 and a second pole connected to the first power signal terminal ELVDD; a first pole of the fifth transistor T5 is connected to the second power signal terminal ELVSS, and a second pole thereof is connected to the first pole of the sixth transistor T6; the gate of the sixth transistor T6 is connected to the first pole of the third transistor T3, the first pole thereof is connected to the second pole of the fifth transistor T5 and the second pole thereof is connected to the first pole of the fourth transistor T4; one end of the storage capacitor C1 is connected to the gate of the sixth transistor T6, and the other end thereof is connected to the second pole of the second transistor T2; one end of the parasitic capacitor C2 is connected to the second power signal terminal ELVSS, and the other end thereof is connected to the second pole of the second transistor T2; the other end of the light emitting device EL is also connected to the first power supply signal terminal ELVDD. The Light Emitting device EL in the embodiment of the present invention may be various current-driven Light Emitting devices including an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode) in the related art. In the embodiment of the present invention, an OLED is taken as an example for description.
In a specific embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are N-type transistors.
In a specific embodiment, the first poles of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are drains, and the second poles of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are sources.
In a specific embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are amorphous indium gallium zinc oxide thin film transistors (IGZO TFTs). Alternatively, enhancement type MOSFET, depletion type MOSFET, bipolar junction type transistor can be used.
The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors as an example, and when the pixel circuit shown in fig. 1 works, the working process can be specifically divided into four stages, which are respectively: the device comprises an initialization phase, a compensation phase, a data writing phase and a light emitting phase. Fig. 2 is a timing chart of each signal line in the operation of the pixel circuit shown in fig. 1. The operation of the pixel compensation circuit will be briefly described with reference to the timing relationship of each signal and the equivalent circuit diagrams of the pixel compensation circuit at each stage shown in fig. 3 to 6. An "X" in the equivalent circuit shown in the schematic diagrams 3-6 indicates non-conduction.
Specifically, the stage P1 is an initialization stage, and an equivalent circuit of the stage is shown in fig. 3. In the initialization stage, the first scan control terminal S1 and the second scan control terminal S2 each input a high level, the first power signal terminal ELVDD inputs a low level (Vss), and the data signal terminal Vdata inputs a low level initialization signal (Vref), where Vref-Vth > Vss (Vth is a threshold voltage of the T6 transistor). At this time, the light emitting device D does not emit light, the first transistor T1, the fourth transistor T1, and the fifth transistor T5 are turned off and the sources and drains of the transistors are not turned on, and the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on. The anode voltage of the light emitting device EL is Vss, and the light emitting device EL is in an off state.
The P2 stage is a compensation stage, and the equivalent circuit of the stage is shown in fig. 4. In the compensation phase, the second scan control terminal S2 and the first power signal terminal ELVDD are both inputted with a high level, and the data signal terminal Vdata is inputted with an initialization signal (Vref) of a low level. At this time, the first transistor T1, the fifth transistor T5 remain turned off, the second transistor T2 is turned off and the fourth transistor T4 is turned on, and the anode voltage of the light emitting device EL increases with the charging of the fourth transistor T4 until the voltage is equal to Vref-Vth. At the end of the compensation phase, the charge stored across the storage capacitor C1 is Vth · CST, where CST is the capacitance value of the storage capacitor C1.
The P3 phase is the data write phase. The equivalent circuit at this stage is shown in fig. 5. Before the data is ready to be written, the fourth transistor T4 needs to be turned off, at which time the anode voltage of the light emitting device EL is Vref-Vth. In the data writing phase, the second scan control terminal S2 inputs a high level, and the data signal terminal Vdata inputs a high level data signal (Vdata). At this time, the first transistor T1, the second transistor T2, and the fifth transistor T5 remain turned off, the fourth transistor T4 turns off, and the anode voltage of the light emitting device EL becomes Vref-Vth + R (Vdata-Vref), where R is CST/(CST + CL), where CST is the capacitance value of the storage capacitor C1 and CL is the capacitance value of the parasitic capacitor C2.
The P4 phase is a glow phase. The equivalent circuit at this stage is shown in fig. 6. The third transistor T3 needs to be turned off before the pixel circuit is ready to drive the light emitting device to emit light. In the light emitting period, the first power signal terminal ELVDD is inputted with a high level, the first control signal terminal S1 and the data signal terminal Vdata are inputted with a low level, so that the third transistor T3 is turned off, at which time the second transistor T2, the fourth transistor T4 remain turned off, and the first transistor T1 and the fifth transistor T5 are turned on, at which time the gate-source voltage Vgs of the first transistor T1 is Vdata-Vref + Vth-R (Vdata-Vref).
The current Ids flowing through the first transistor T1, the fifth transistor T5, and the light emitting device EL at this time is: k [ Vdata-Vref-R (Vdata-Vr)ef)〕2。
Where K is a parameter related to TFT mobility, Vgs and Vds in turn relate to the OLED drive voltage and the supply voltage. It can be known that the parameters affecting the current magnitude include the mobility of the TFT, the threshold voltage, the driving voltage of the OLED, and the magnitude of the power supply voltage. The main purpose of the compensation technique is to eliminate the influence of these factors, and finally to make the brightness of all pixels reach the ideal value. According to the formula, the current of the light-emitting device EL is irrelevant to the threshold voltage of the TFT and the voltage at two ends of the OLED, so that the influence of non-uniformity and drift of the threshold voltage is effectively eliminated.
In the pixel compensation circuit structure described in this embodiment, the scanning control terminal is reset to capture the threshold voltage in a collinear manner through the data signal terminal Vdata and the reset control terminal Vref, the number of transistors can be effectively reduced, the circuit is switched and charged and discharged through a plurality of transistors and capacitors, the current for driving the light emitting device through the transistors is unrelated to the threshold voltage of the transistors, the current difference flowing through the light emitting device due to inconsistency or deviation of the threshold voltage of the transistors is compensated, the uniformity of the light emitting brightness of the display device is improved, the influence of non-uniformity of the threshold voltage can be compensated for both enhancement type and depletion type TFTs, and therefore, the applicability is wider. In addition, the number of required signal lines and the number of used TFTs are small, control signals are simple, and the method is suitable for high-resolution pixel design. The display effect is obviously improved.
In different embodiments, if the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all P-type transistors, the timing of each control signal may be opposite to the timing of the signals in fig. 2 (i.e., the phase difference is 180 degrees).
Referring to fig. 7, a second embodiment of a pixel compensation circuit structure of an active matrix organic light emitting display is further provided. In the present embodiment, the pixel circuit structure includes a plurality of transistors, a capacitor and a light emitting device, gates of the transistors are respectively connected to a plurality of scan control terminals, the transistors are numbered in groups according to an order of the scan control terminals connected to the gates in the following related circuit driving description of the invention, the plurality of scan control terminals include a first scan control terminal S1 and a second scan control terminal S2, the transistors include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor C1, a parasitic capacitor C2, and a light emitting device EL.
Wherein a first pole of the first transistor T1 is connected to the light emitting device EL and a second pole thereof is connected to a second pole of the sixth transistor T6; the gate of the second transistor T2 is connected to the first scan control terminal S1, the first pole thereof is connected to the reset signal terminal Vint and the second pole thereof is connected to the first pole of the fifth transistor T5; the gate of the third transistor T3 is connected to the second scan control terminal S2, the first pole thereof is connected to the gate of the sixth transistor T6 and the second pole thereof is connected to the reset control terminal Vref; the fourth transistor T4 has a first pole connected to the second pole of the sixth transistor T6 and a second pole connected to the first power signal terminal ELVDD; a first pole of the fifth transistor T5 is connected to the second power signal terminal ELVSS, and a second pole thereof is connected to the first pole of the sixth transistor T6; the gate of the sixth transistor T6 is connected to the first pole of the third transistor T3, the first pole thereof is connected to the second pole of the fifth transistor T5 and the second pole thereof is connected to the first pole of the fourth transistor T4; a gate of the seventh transistor T7 is connected to the third scan control terminal S3, a first pole thereof is connected to the data signal terminal Vdata, and a second pole thereof is connected to the gate of the sixth transistor T6; one end of the storage capacitor C1 is connected to the gate of the sixth transistor T6, and the other end thereof is connected to the second pole of the second transistor T2; one end of the parasitic capacitor C2 is connected to the second power signal terminal ELVSS, and the other end thereof is connected to the second pole of the second transistor T2; the other end of the light emitting device EL is also connected to the first power supply signal terminal ELVDD.
In a specific embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are N-type transistors.
In a specific embodiment, the first poles of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are drains, and the second poles of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are sources.
In a specific embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are amorphous indium gallium zinc oxide thin film transistors (IGZO TFTs). Alternatively, enhancement type MOSFET, depletion type MOSFET, bipolar junction type transistor can be used.
Taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as examples, when the pixel circuit shown in fig. 7 works, the working process can be divided into four stages: the device comprises an initialization phase, a compensation phase, a data writing phase and a light emitting phase. Fig. 8 is a timing chart of each signal line in the operation of the pixel circuit shown in fig. 7. The operation of the pixel compensation circuit will be briefly described with reference to the timing relationship of each signal and the equivalent circuit diagrams of the pixel compensation circuit at each stage shown in fig. 9-12.
Specifically, the stage P1 is an initialization stage, and an equivalent circuit of the stage is shown in fig. 9. In the initialization stage, the first scan control terminal S1 and the second scan control terminal S2 each input a high level, the third scan control terminal S3 and the first power signal terminal ELVDD input a low level (Vss), and the data signal terminal Vdata input a low level initialization signal (Vref), where Vref-Vth > Vss (Vth is a threshold voltage of the T6 transistor). At this time, the light emitting device D does not emit light, the first transistor T1, the fourth transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned off and the sources and drains of the transistors are not turned on, and the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on. The anode voltage of the light emitting device EL is Vss, and the light emitting device EL is in an off state.
The P2 stage is a compensation stage, and the equivalent circuit of the stage is shown in fig. 10. In the compensation phase, the second scan control terminal S2 and the first power signal terminal ELVDD are both inputted with a high level, and the data signal terminal Vdata is inputted with an initialization signal (Vref) of a low level. At this time, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 remain turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on, and the anode voltage of the light emitting device EL rises with the charge of the fourth transistor T4 until the voltage is equal to Vref-Vth. At the end of the compensation phase, the charge stored across the storage capacitor C1 is Vth · CST, where CST is the capacitance value of the storage capacitor C1.
The P3 phase is the data write phase. The equivalent circuit at this stage is shown in fig. 11. Before the data is ready to be written, the fourth transistor T4 needs to be turned off, at which time the anode voltage of the light emitting device EL is Vref-Vth. In the data writing phase, the second scan control terminal S2 inputs a high level, and the data signal terminal Vdata inputs a high level data signal (Vdata). At this time, the first transistor T1, the second transistor T2, and the fifth transistor T5 are kept off, the third transistor T3, the fourth transistor T4 are turned off, and the seventh transistor T7 is turned on, and the anode voltage of the light emitting device EL becomes Vref-Vth + R (Vdata-Vref), where R is CST/(CST + CL), where CST is the capacitance value of the storage capacitor C1 and CL is the capacitance value of the parasitic capacitor C2.
The P4 phase is a glow phase. The equivalent circuit at this stage is shown in fig. 12. The seventh transistor T7 needs to be turned off before the pixel circuit is ready to drive the light emitting device to emit light. In the light emitting period, the first power signal terminal ELVDD is inputted with a high level, the first control signal terminal S1 and the data signal terminal Vdata are inputted with a low level, so that the seventh transistor T7 is turned off, at which time the second transistor T2, the fourth transistor T4 remain turned off, and the first transistor T1 and the fifth transistor T5 are turned on, at which time the gate-source voltage Vgs of the first transistor T1 is Vdata-Vref + Vth-R (Vdata-Vref).
The current Ids flowing through the first transistor T1, the fifth transistor T5, and the light emitting device EL at this time is: k [ Vdata-Vref-R (Vdata-Vref) ]2。
Where K is a parameter related to TFT mobility, Vgs and Vds in turn relate to the OLED drive voltage and the supply voltage. It can be known that the parameters affecting the current magnitude include the mobility of the TFT, the threshold voltage, the driving voltage of the OLED, and the magnitude of the power supply voltage. The main purpose of the compensation technique is to eliminate the influence of these factors, and finally to make the brightness of all pixels reach the ideal value. According to the formula, the current of the light-emitting device EL is irrelevant to the threshold voltage of the TFT and the voltage at two ends of the OLED, so that the influence of non-uniformity and drift of the threshold voltage is effectively eliminated.
In different embodiments, if the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors, the timing of each control signal may be opposite to the timing of the signals in fig. 8 (i.e., the phase difference is 180 degrees).
In the pixel compensation circuit structure described in this embodiment, threshold grabbing is performed in a manner that the data signal terminal Vdata and the reset control terminal Vref are independent from each other, which has the advantages that the load of an IC can be effectively reduced when a high-resolution product is manufactured, the number of transistors can be effectively reduced, switching and charging and discharging control is performed on a circuit through a plurality of transistors and capacitors, so that a current for driving a light emitting device through the transistors is independent from a threshold voltage of the transistors, a current difference flowing through the light emitting device due to inconsistency or deviation of the threshold voltage of the transistors is compensated, uniformity of light emission luminance of a display device is improved, and influence of threshold voltage nonuniformity can be compensated for an enhancement type TFT or a depletion type TFT, and thus, the applicability is wider. In addition, the number of required signal lines and the number of used TFTs are small, control signals are simple, and the method is suitable for high-resolution pixel design. The display effect is obviously improved.
An embodiment of the present invention further provides an active matrix organic light emitting display, including the pixel compensation circuit structure according to any one of the above embodiments. The active matrix organic light emitting display may include a plurality of pixel cell arrays, each pixel cell including the pixel compensation circuit structure of any one of the embodiments described above. Optionally, the pixel compensation circuit structure shown in fig. 1 or fig. 7 has the same beneficial effects as the pixel compensation circuit provided in the foregoing embodiment of the present invention, and since the pixel circuit has been described in detail in the foregoing embodiment, no further description is given here.
Specifically, the active matrix organic light emitting display provided by the embodiment of the invention may be a display apparatus having a current-driven light emitting device including an LED display or an OLED display.
In summary, the present invention provides pixel compensation circuit structures of different embodiments, in one embodiment, the scanning control terminal is reset to capture the threshold voltage mainly in a manner that the data signal terminal Vdata and the reset control terminal Vref are collinear; in another embodiment, the threshold capture is mainly performed in a manner that the data signal terminal Vdata and the reset control terminal Vref are independent from each other, which is advantageous in that the burden of an IC can be effectively reduced when a high-resolution product is manufactured, the pixel compensation circuit structure described in different embodiments can effectively reduce the number of transistors, the switching and charging and discharging control is performed on the circuit through a plurality of transistors and capacitors, so that the current for driving the light emitting device through the transistors is independent from the threshold voltage of the transistors, the current difference flowing through the light emitting device due to the inconsistency or deviation of the threshold voltage of the transistors is compensated, the compensation value of Vth is compensated into the scan control terminal (Gate terminal) of the control tube during the light emitting stage, which helps to stabilize the luminance displayed by the OLED pixel within one frame, thereby eliminating the influence of process fluctuation on the overall light emitting uniformity of the display, the uniformity of the display luminance is improved, and the influence of non-uniformity of threshold voltage can be compensated for both enhancement type and depletion type TFTs, so that the display luminance uniformity is wider in applicability.
In addition, the pixel compensation circuit structure adopts the N-type transistor with single attribute, the steps of the manufacturing process are greatly reduced, the number of required signal lines and the number of used TFTs are small, the control signal is simple, and the pixel compensation circuit structure is suitable for high-resolution pixel design.
The foregoing description shows and describes several preferred embodiments of the invention, but as before, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A pixel compensation circuit structure of an active matrix organic light emitting display is characterized in that the pixel compensation circuit structure of the active matrix organic light emitting display comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a storage capacitor, a parasitic capacitor, and a light emitting device;
wherein a first pole of the first transistor is connected to the light emitting device, and a second pole thereof is connected to a second pole of the sixth transistor;
the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor;
the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the data signal end;
a first pole of the fourth transistor is connected with a second pole of the sixth transistor, and a second pole of the fourth transistor is connected with the first power supply signal end;
a first pole of the fifth transistor is connected with a second power supply signal end, and a second pole of the fifth transistor is connected with a first pole of the sixth transistor;
the grid electrode of the sixth transistor is connected with the first pole of the third transistor, the first pole of the sixth transistor is connected with the second pole of the fifth transistor, and the second pole of the sixth transistor is connected with the first pole of the fourth transistor;
one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor;
one end of the parasitic capacitor is connected with a second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; and
the other end of the light-emitting device is also connected with a first power signal end.
2. The pixel compensation circuit structure of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors.
3. The pixel compensation circuit structure of claim 1, wherein first electrodes of said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, and said sixth transistor are drain electrodes, and second electrodes of said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, and said sixth transistor are source electrodes.
4. The pixel compensation circuit structure of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are amorphous indium gallium zinc oxide thin film transistors.
5. A pixel compensation circuit structure of an active matrix organic light emitting display is characterized in that the pixel compensation circuit structure of the active matrix organic light emitting display comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor, a parasitic capacitor, and a light emitting device;
wherein a first pole of the first transistor is connected to the light emitting device, and a second pole thereof is connected to a second pole of the sixth transistor;
the grid electrode of the second transistor is connected with the first scanning control end, the first pole of the second transistor is connected with the reset signal end, and the second pole of the second transistor is connected with the first pole of the fifth transistor;
the grid electrode of the third transistor is connected with the second scanning control end, the first pole of the third transistor is connected with the grid electrode of the sixth transistor, and the second pole of the third transistor is connected with the reset control end;
a first pole of the fourth transistor is connected with a second pole of the sixth transistor, and a second pole of the fourth transistor is connected with the first power supply signal end;
a first pole of the fifth transistor is connected with a second power supply signal end, and a second pole of the fifth transistor is connected with a first pole of the sixth transistor;
the grid electrode of the sixth transistor is connected with the first pole of the third transistor, the first pole of the sixth transistor is connected with the second pole of the fifth transistor, and the second pole of the sixth transistor is connected with the first pole of the fourth transistor;
the grid electrode of the seventh transistor is connected with the third scanning control end, the first pole of the seventh transistor is connected with the data signal end, and the second pole of the seventh transistor is connected with the grid electrode of the sixth transistor;
one end of the storage capacitor is connected with the grid electrode of the sixth transistor, and the other end of the storage capacitor is connected with the second pole of the second transistor;
one end of the parasitic capacitor is connected with a second power supply signal end, and the other end of the parasitic capacitor is connected with the second pole of the second transistor; and
the other end of the light-emitting device is also connected with a first power signal end.
6. The pixel compensation circuit structure of claim 5, wherein said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, said sixth transistor, and said seventh transistor are N-type transistors.
7. The pixel compensation circuit structure of claim 5, wherein a first pole of said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, said sixth transistor, and said seventh transistor is a drain, and a second pole of said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, said sixth transistor, and said seventh transistor is a source.
8. The pixel compensation circuit structure of claim 5, wherein said first transistor, said second transistor, said third transistor, said fourth transistor, said fifth transistor, said sixth transistor and said seventh transistor are amorphous indium gallium zinc oxide thin film transistors.
9. An active matrix organic light emitting display, comprising:
a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and pixel circuits arranged at portions where scanning control lines in a row form to which control signals are supplied and signal lines in a column form to which data signals are supplied cross each other; wherein the pixel circuit comprises a pixel compensation circuit structure according to any one of claims 1-4.
10. An active matrix organic light emitting display, comprising:
a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and pixel circuits arranged at portions where scanning control lines in a row form to which control signals are supplied and signal lines in a column form to which data signals are supplied cross each other; wherein the pixel circuit comprises a pixel compensation circuit structure according to any one of claims 5-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910326914.XA CN111833819A (en) | 2019-04-23 | 2019-04-23 | Pixel compensation circuit structure of active matrix organic light emitting display and display thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910326914.XA CN111833819A (en) | 2019-04-23 | 2019-04-23 | Pixel compensation circuit structure of active matrix organic light emitting display and display thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111833819A true CN111833819A (en) | 2020-10-27 |
Family
ID=72912460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910326914.XA Pending CN111833819A (en) | 2019-04-23 | 2019-04-23 | Pixel compensation circuit structure of active matrix organic light emitting display and display thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111833819A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093639A (en) * | 2006-06-22 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Organic light-emitting diode display device and driving method thereof |
| KR20090095913A (en) * | 2008-03-06 | 2009-09-10 | 엘지디스플레이 주식회사 | Organic Light Emitting Diode Display And Driving Method Thereof |
| KR20100039066A (en) * | 2008-10-07 | 2010-04-15 | 엘지디스플레이 주식회사 | Organic electroluminescent display device |
| CN101976545A (en) * | 2010-10-26 | 2011-02-16 | 华南理工大学 | Pixel drive circuit of OLED (Organic Light Emitting Diode) display and drive method thereof |
| CN102651197A (en) * | 2011-11-01 | 2012-08-29 | 京东方科技集团股份有限公司 | Organic light emitting diode driving circuit, display panel, display and driving method |
| CN103474022A (en) * | 2013-08-22 | 2013-12-25 | 京东方科技集团股份有限公司 | Pixel circuit, pixel circuit driving method, array baseplate and display device |
| US9786227B2 (en) * | 2014-03-19 | 2017-10-10 | Samsung Display Co., Ltd. | Organic light emitting display device and driving method thereof |
| CN107731161A (en) * | 2016-08-12 | 2018-02-23 | 鸿富锦精密工业（深圳）有限公司 | Display device |
-
2019
- 2019-04-23 CN CN201910326914.XA patent/CN111833819A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093639A (en) * | 2006-06-22 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Organic light-emitting diode display device and driving method thereof |
| KR20090095913A (en) * | 2008-03-06 | 2009-09-10 | 엘지디스플레이 주식회사 | Organic Light Emitting Diode Display And Driving Method Thereof |
| KR20100039066A (en) * | 2008-10-07 | 2010-04-15 | 엘지디스플레이 주식회사 | Organic electroluminescent display device |
| CN101976545A (en) * | 2010-10-26 | 2011-02-16 | 华南理工大学 | Pixel drive circuit of OLED (Organic Light Emitting Diode) display and drive method thereof |
| CN102651197A (en) * | 2011-11-01 | 2012-08-29 | 京东方科技集团股份有限公司 | Organic light emitting diode driving circuit, display panel, display and driving method |
| CN103474022A (en) * | 2013-08-22 | 2013-12-25 | 京东方科技集团股份有限公司 | Pixel circuit, pixel circuit driving method, array baseplate and display device |
| US9786227B2 (en) * | 2014-03-19 | 2017-10-10 | Samsung Display Co., Ltd. | Organic light emitting display device and driving method thereof |
| CN107731161A (en) * | 2016-08-12 | 2018-02-23 | 鸿富锦精密工业（深圳）有限公司 | Display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11699394B2 (en) | Pixel circuit, driving method thereof and display device | |
| CN113838421B (en) | Pixel circuit, driving method thereof and display panel | |
| US11915651B2 (en) | Electroluminescent display | |
| CN107452334B (en) | Pixel circuit and driving method thereof, display substrate and driving method thereof, and display device | |
| US10700146B2 (en) | Pixel and organic light-emitting display device having the same | |
| US9947269B2 (en) | Organic light emitting display and circuit thereof | |
| US20190259785A1 (en) | Pixel circuit of active-matrix light-emitting diode comprising oxide semiconductor transistor and silicon semiconductor transistor and display panel having the same | |
| CN103218970B (en) | Active matrix organic light emitting diode (AMOLED) pixel unit, driving method and display device | |
| CN102982767B (en) | Pixel unit driving circuit, driving method and display device | |
| CN104036725B (en) | Image element circuit and its driving method, organic electroluminescence display panel and display device | |
| CN105427809B (en) | Pixel compensation circuit and AMOLED display device | |
| US9852685B2 (en) | Pixel circuit and driving method thereof, display apparatus | |
| CN103258501B (en) | Pixel circuit and driving method thereof | |
| CN107346654B (en) | Pixel circuit, driving method thereof and display device | |
| CN103310728B (en) | Light emitting diode pixel unit circuit and display panel | |
| CN109300436B (en) | AMOLED pixel driving circuit and driving method | |
| CN108777131B (en) | AMOLED pixel driving circuit and driving method | |
| CN107369412B (en) | Pixel circuit, driving method thereof and display device | |
| CN110675829B (en) | Pixel driving circuit, driving method thereof, display panel and display device | |
| CN108389551B (en) | Pixel circuit, driving method thereof and display device | |
| CN110570819B (en) | Pixel driving circuit and driving method thereof, array substrate and display device | |
| JP2012516456A (en) | Display device and drive control method thereof | |
| CN105139805A (en) | Pixel driving circuit, driving method thereof and display device | |
| CN104537984B (en) | Pixel circuit and driving method thereof | |
| CN114093319A (en) | Pixel compensation circuit, pixel driving method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20201027 |