CN111819705B

CN111819705B - Novel distributed array and CMOS architecture for 2-stack 3D phase change memory with higher array efficiency

Info

Publication number: CN111819705B
Application number: CN202080001051.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-05-12
Filing date: 2020-05-12
Publication date: 2021-08-17
Anticipated expiration: 2040-05-12
Also published as: WO2021226815A1; CN111819705A

Abstract

A three-dimensional memory architecture includes a bottom cell array of memory cells, a top cell array of memory cells, a plurality of bottom cell bitlines coupled to the bottom cell array, a plurality of top cell bitlines coupled to the top cell array, and a plurality of wordlines coupled to both arrays. A bit line decoder and a word line decoder are provided to selectively activate the bit lines and the word lines. The arrays of memory cells are arranged in offset sub-portions, respectively. The bit lines and the word lines are arranged in the shifted portions, respectively. The bit line decoder is arranged in an offset bit line decoder subsection. Word line decoders are also arranged in offset word line decoder subsections.

Description

Novel distributed array and CMOS architecture for 2-stack 3D phase change memory with higher array efficiency

Technical Field

The present disclosure relates generally to three-dimensional electronic memories, and more particularly to increasing the density of memory cells in three-dimensional phase change (3D PCM) memories.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of the planar memory cell approaches the upper limit. There remains a need for a three-dimensional (3D) memory architecture that can address density limitations in planar memory cells.

Disclosure of Invention

The three-dimensional memory and methods disclosed herein solve the problems of the prior art and provide further benefits. According to one aspect, a distributed array and CMOS (complementary metal oxide semiconductor) architecture for 3D PCM memory is disclosed and shown. The Word Line (WL) and Bit Line (BL) decoders of each memory block are divided into several parts and arranged in a distributed pattern. In the middle of the word line and the bit line, the middle of the WL and BL decoder regions is connected. The TCBL (top cell bit line) blocks are offset by half a block to establish connections between the BCBL (bottom cell bit line) blocks with CMOS TCBL decoding. The BCBL, TCBL block, and BCWL (bottom cell word line) block are offset to maximize area usage. As a result, array efficiency is greatly improved compared to state of the art systems.

In another aspect, a bottom cell array of memory cells is arranged in the first bottom cell array subsection and the second bottom cell array subsection. The first bottom cell array subsection and the second bottom cell array subsection are offset. The bottom cell bit line is coupled to a bottom cell array of memory cells. The bottom cell bit lines include a first portion of bottom cell bit lines and a second portion of bottom cell bit lines. A first bottom cell bit line decoder subsection having a first set of bottom cell bit line decoders is coupled to the first portion of bottom cell bit lines and is operable to selectively activate the first portion of bottom cell bit lines. A second bottom cell bit line decoder subsection having a second set of bottom cell bit line decoders is coupled to the second portion of bottom cell bit lines and is operable to selectively activate the second portion of bottom cell bit lines. The top cell array of memory cells is arranged above the bottom cell array of memory cells in the depth direction. The top cell array of memory cells is arranged in a first top cell array subsection and a second top cell array subsection, wherein the first top cell array subsection and the second top cell array subsection are offset. The top cell bit line is coupled to a top cell array of memory cells. The top cell bit lines include a first portion of top cell bit lines and a second portion of top cell bit lines. A first top cell bit line decoder subsection having a first set of top cell bit line decoders is coupled to the first portion of top cell bit lines and is operable to selectively activate the first portion of top cell bit lines. A second top cell bit line decoder subsection having a second set of top cell bit line decoders is coupled to the second portion of top cell bit lines and is operable to selectively activate the second portion of top cell bit lines. The word line is coupled to the bottom cell array of memory cells and to the top cell array of memory cells. The word line includes at least two offset word line portions. The plurality of word line decoder sub-portions includes at least one set of word line decoders coupled to the word lines of the first portion and operable to selectively activate the word lines of the first portion. At least one set of word line decoders is coupled to the second portion of word lines and is operable to selectively activate the second portion of word lines.

In another aspect, a method for forming CMOS and array architectures for 3D PCM memories is disclosed. The method comprises the following steps: the WL decoder region is divided into two parts offset in the X direction. The bit line decoder is divided into two parts offset in the Y direction. The bottom cell bitline contact is located in the middle of the bottom cell block. The word line contacts are located intermediate the word lines and the word line decoder. The top cell bitline contact is located between two adjacent bottom cell blocks.

In another aspect, a method of forming a three-dimensional memory includes: a bottom cell array of memory cells, a top cell array of memory cells, a bottom cell bit line coupled to the bottom cell array of memory cells, a top cell bit line coupled to the top cell array of memory cells, a word line coupled to the top cell array of memory cells and to the bottom cell array of memory cells, a bottom cell bit line decoder coupled to the bottom cell bit line and operable to selectively activate the bottom cell bit line, a top cell bit line decoder coupled to the top cell bit line and operable to selectively activate the top cell bit line, and a word line decoder coupled to the word line and operable to selectively activate the word line are provided. The bottom cell array of memory cells is formed as first and second bottom cell array sub-sections that are offset from each other, and the top cell array of memory cells is formed as first and second top cell array sub-sections that are offset from each other. The word lines are formed in a plurality of word line portions that are offset from each other. The word line decoders are formed in word line decoder subsections that are offset from each other. The bottom cell bit line decoders are formed in bottom cell bit line decoder subsections that are offset from one another. Further, the bottom cell bit line decoders are formed in bottom cell bit line decoder subsections that are offset from each other.

Drawings

The foregoing aspects, features and advantages of the disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for the sake of clarity. However, aspects of the disclosure are not intended to be limited to the specific terminology used.

FIG. 1 is an isometric view of a portion of a three-dimensional phase change memory.

Fig. 2 is a plan view of a portion of a conventional three-dimensional phase change memory.

Fig. 3A and 3B are plan views of a portion of a conventional three-dimensional phase change memory.

Fig. 4A and 4B are plan views of a portion of a conventional three-dimensional phase change memory.

Fig. 5A and 5B are plan views of a portion of a three-dimensional phase change memory according to an embodiment.

Fig. 6 is a plan view of portions of a three-dimensional phase change memory according to the embodiment of fig. 5A and 5B.

Fig. 7A is a plan view of portions of a three-dimensional phase change memory according to the embodiment of fig. 5A and 5B.

Fig. 7B and 7C are cross-sectional views of portions of the three-dimensional phase change memory of fig. 7A.

FIG. 8 is a plan view of a portion of a three-dimensional phase change memory according to another embodiment.

FIGS. 9A-C are plan views of portions of a three-dimensional phase change memory according to another embodiment.

Detailed Description

The technology is applied to the field of three-dimensional memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. Specifically, FIG. 1 is an isometric view of a portion of a three-dimensional phase change memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first-layer memory cells 5 and the second-layer memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. In the depth (Z) direction, above the first-layer memory cells 5 are a plurality of first bit lines 20 extending in the vertical (Y) direction, and below the second-layer memory cells 10 are a plurality of second bit lines 25 extending in the Y direction.

As further shown in fig. 1, the sequential structure of bit lines, memory cells, word lines, memory cells may be repeated along the Z-direction to form a stacked configuration. In the example of fig. 1, a first layer of the stack may include first layer memory cells 5, bit lines 20, and word lines 15, and a second layer of the stack may include second layer memory cells 10, bit lines 25, and word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their respective sets of

bit lines

20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 illustrates a 2-layer stacked configuration, in other examples, the stacked configuration may include any number of memory cell layers and other components. In any event, each memory cell in the structure can be accessed by selectively activating the word line and bit line corresponding to that cell.

To selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown). The word line decoder is coupled to the word lines through word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode bit line addresses so that a particular bit line is activated when addressed. Thus, the stacked configuration of the memory may also include bit line contacts and decoders, as well as word line contacts and decoders for selectively activating bit lines and word lines in the stack. For example, the stacked configuration may be arranged as an array of elements, where each array includes a set of memory cells and a corresponding set of bit lines, word lines, bit line and word line contacts and bit line and word line decoders. The positioning of the word line decoders and contacts and the bit line decoders and contacts are further illustrated and discussed with reference to FIG. 2.

Fig. 2 is a plan view of a portion of a three-dimensional phase change memory of a conventional configuration. The figure depicts a section viewed in the Z (depth) direction. In this example, the configuration of the stack is a 2-layer stack. The stacked configuration includes a plurality of memory cell arrays including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in fig. 2, they are shown in fig. 1, for example in a top array, the memory cells may be arranged as first level memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as second level memory cells 10 shown in fig. 1.

The portion includes word and bit lines, word and bit line contacts, and word and bit line decoders corresponding to the top and bottom cells. As shown, a number of word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to the top and bottom cells. The portion also includes a plurality of top cell bit lines (e.g., bit line 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a plurality of bottom cell bit lines (e.g., bit line 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed from a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are aligned in the horizontal direction for a given cell array. For example, as shown, word lines for the

cell arrays

60, 61, 65, and 66 are all horizontally aligned with each other along the X direction. Each of these word lines is shown extending across the entire width of the respective cell array. The top cell bit lines of a given top cell array or the bottom cell bit lines of a given bottom cell array are vertically aligned. For example, the top cell bit lines 35 are vertically aligned along the Y-direction, and the bottom cell bit lines 40 are vertically aligned along the Y-direction. The top cell bit lines of the top cell array and the bottom cell bit lines of the overlapping bottom cell array (e.g., top cell bit line 35 and bottom cell bit line 40) are also horizontally aligned with each other, but they are shown slightly offset in fig. 2 to clearly show the two layers. However, it is also acceptable to have a slight offset between the top cell bit line and the bottom cell bit line. Each of these bit lines is shown as extending over the entire length of the respective cell array.

The memory portion of fig. 2 includes word line contact regions 45, top cell bit line contact regions 50, and bottom cell bit line contact regions 55. The word line contact regions 45 extend in a vertical direction, while the top cell bit line contact regions 50 and the bottom cell contact regions 55 extend in a horizontal direction. The word line contact area 45 includes a plurality of word line contacts (e.g., contacts 45a), which are shown as dots surrounded by the word line contact area 45. The top cell bit line contact region 50 includes a plurality of word line contacts (e.g., contacts 50a), shown as dots surrounded by the top cell bit line contact region 50. The bottom cell bit line contact area 55 includes a plurality of bottom cell bit line contacts (e.g., contact 55a), shown as dots surrounded by the bottom cell bit line contact area 55.

Word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus, as shown, word line contact region 45 is located in the horizontal middle of word line 40, bottom cell bit line contact region 55 is located in the vertical middle of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical middle of top cell bit line 35. Since the word lines for a given cell array are aligned in the horizontal direction, the word line contacts for a given cell array are also substantially aligned in the horizontal direction. Also, since the bit lines of a given cell array are aligned in the vertical direction, the bit line contacts for a given cell array are also substantially aligned in the vertical direction.

The word line contact regions 45 also include a plurality of word line decoders (not shown). The word line decoder generally conforms to the word line contact regions and generally extends in a vertical direction. The word line decoder is coupled to a word line through a word line contact. The top cell bit line contact region 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally conforms to the top cell bit line contact region 50 and generally extends in a horizontal direction. A top cell bitline decoder is coupled to the top cell bitline through a top cell bitline contact. The bottom cell bit line contact region 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally conforms to the bottom cell bit line contact region 55 and generally extends in a horizontal direction. The bottom cell bit line decoder is coupled to the bottom cell bit line through a bottom cell bit line contact.

Those skilled in the art have recognized that the prior configuration illustrated in fig. 2 is inefficient in terms of storage space usage, and that other configurations may provide improved memory cell density and bit line density. The disadvantages of the prior art constructions are primarily related to the arrangement of the word line decoders. As shown in fig. 2, word line contact regions 45 and corresponding word line contacts and word line decoders are arranged along a horizontal middle portion of the memory structure. For example, as shown, word line contacts 45 and word line decoders are arranged along the horizontal middle of the top and bottom arrays of memory cells 60 and 65 (but at different depths in the Z direction). The same is true for other arrays in the memory, such as the top cell array 61 and the bottom cell array 66, where the word line contact regions also occupy the horizontal middle of these arrays. As described above, the decoder is arranged because: within a given array, word lines are horizontally aligned and bit lines are vertically aligned. This configuration and its disadvantages are further illustrated and discussed with reference to fig. 3A and 3B.

Fig. 3A is a plan view of a portion of a conventional three-dimensional phase change memory. The figure depicts a section viewed in the depth or Z direction. This example is a 2-layer stack configuration. The figure shows a plurality of bottom cell arrays including a bottom cell array 60 extending from a first or top edge 75 to a second or bottom edge 80, and a plurality of top cell arrays including a top cell array 65 extending from a first or top edge 76 to a second or bottom edge 81. Fig. 3B is the same plan view as fig. 3A except that the marks representing the bottom cell array 60 and the top cell array 65 have been removed. For clarity of fig. 3A and 3B, only portions of the bottom cell array 60 and the top cell array 65 will be discussed, it being understood that such discussion may readily apply to other portions of the figures. In addition, it should be noted that the figures only show the word line decoder, the top cell bit line decoder, and the bottom cell bit line decoder, and do not show other portions of the memory.

Referring to fig. 3A and 3B, it can be seen that the memory portion includes a set of word line decoders 70, the set of word line decoders 70 being arranged in continuous vertical stripes extending in the Y-direction from a top edge 75 of the bottom cell array 60 to a bottom edge 80 of the bottom cell array 60. The memory portion also includes a set of top cell bit line decoders 85 of the top cell array 65 (which are divided into two

sections

85a and 85b along the horizontal or X direction and vertically aligned) and a set of bottom cell bit line decoders 90 of the bottom cell array 60 (which are divided into two

sections

90a and 90b vertically aligned along the horizontal or X direction). Thus, as shown in fig. 3A and 3B, the bit line and word line decoders are symmetrically arranged in the memory structure. As described with respect to fig. 2, this is because: the word lines are horizontally aligned within a given array, while the bit lines are vertically aligned within a given array. Thus, this prior configuration shown in fig. 3A and 3B dedicates vertical stripes of storage area to the word line contacts and word line decoders, which do not include any bit lines or memory cells for data storage, thereby limiting storage efficiency.

The present technology has been developed in view of the above-described problems, and it is an object of the present technology to provide a method for manufacturing a semiconductor device.

A comparison of a prior art memory architecture with embodiments of the present technology is provided in fig. 4A-5B. Fig. 4A and 4B are plan views of a portion of a conventional three-dimensional phase change memory. Fig. 5A and 5B are plan views of a portion of a three-dimensional phase change memory according to an embodiment. It should be noted that for the sake of clarity of presentation, the figures only show some elements of the memory.

Fig. 4A shows a bottom cell array architecture of a prior art memory. The architecture is similar to that shown in connection with the bottom cell array 60 of fig. 3A and 3B. In addition, fig. 4A shows a set of bottom cell bit lines 95, the set of bottom cell bit lines 95 being coupled to the set of bottom cell bit line decoders 90. As shown, the bottom cell array architecture includes vertical stripes of memory regions dedicated to the word line decoder 70, and thus, none of the bottom cell bit lines 95 pass through to overlap the word line decoder 70. Fig. 4B shows how the bottom cell array 60 overlaps the top cell array 65, as shown simply in fig. 3A and 3B. As further shown in fig. 4B, since the area dedicated to the word line decoder 70 is also shared by the top cell array 65, the bit lines of the top cell array 65 also do not overlap with the word line decoder 70. Thus, as the number of arrays increases, the inefficiency also increases due to the area dedicated to the word line decoders.

Fig. 5A illustrates a bottom cell array architecture in accordance with one embodiment. The architecture includes a bottom cell array 100 of memory cells. The bottom cell array 100 of memory cells is represented by dashed lines and is divided into sub-portions. The bottom cell array 100 in fig. 5A is shown divided into a first bottom cell array subsection 100a and a second bottom cell array subsection 100b along the horizontal or X-direction. The two bottom

cell array sub-sections

100a and 100b are offset by a predetermined distance, for example, in the vertical or Y direction as shown. The predetermined distance may be a portion of the length of the bottom cell array 100.

The bit line decoders for the bottom cell array 100 may be distributed for the two bottom

cell array sub-portions

100a and 100 b. For example, as shown, a first bit line decoder subsection 110a may be disposed to overlap the bottom cell array subsection 100a, and a second bit line decoder subsection 110b may be disposed to overlap the bottom cell array subsection 100 b. The bit

line decoder subsections

110a and 110b may be offset by a predetermined distance, for example, along the Y-direction. The offset between the bit

line decoder sub-sections

110a and 110b may be the same as or different from the offset between the two corresponding bottom

cell array sub-sections

100a and 100 b. For example, the predetermined distance may be a portion of the length of the bottom cell array 100.

The word line decoders for the bottom cell array 100 may be distributed for the two bottom

cell array sub-sections

100a and 100 b. For example, as shown, a first word line decoder subsection 120a and a second word line decoder subsection 120b may be disposed to overlap the bottom cell array subsection 100a, while a third word line decoder subsection 120c and a fourth word line decoder subsection 120d may be disposed to overlap the bottom cell array subsection 100 b. Word

line decoder subsections

120a and 120c may be offset by a predetermined distance along the Y-direction, while word

line decoder subsections

120b and 120d may be offset by a predetermined distance along the Y-direction. The offset between the word

line decoder sub-sections

120a and 120c (or 120b and 120d) may be the same or different than the offset between the two corresponding bottom

cell array sub-sections

100a and 100b, and/or may be the same or different than the offset between the corresponding

bit line sub-sections

110a and 110 b. For example, the predetermined distance may be a portion of the length of the bottom cell array 100.

In contrast to fig. 3A, which has horizontally aligned word lines, fig. 5A further illustrates the division of the word lines in fig. 5A into portions having horizontal and/or vertical offsets. For example, a first portion of word lines 106a and a second portion of word lines 106b extend from the area overlapping the adjacent array through the bottom cell array subsection 100a to the area overlapping the bottom cell array subsection 100b, while a third portion of word lines 106c and a fourth portion of word lines 106d extend from the area overlapping the bottom cell array subsection 100a through the bottom cell array subsection 100b into the area overlapping the adjacent array. Due to this offset, the first portion of word lines 106a and the second portion of word lines 106b may be coupled to word line decoders in the region that overlaps the bottom cell array subsection 100a (e.g., those in word

line decoder subsections

120a and 120b, respectively), while the third portion of word lines 106c and the fourth portion of word lines 106d may be coupled to word line decoders in the region that overlaps the bottom cell array subsection 100b (e.g., word

line decoder subsections

120c and 120d, respectively).

The word lines and bit lines may be coupled to respective word line decoders and bit line decoders through word line contacts and bit line contacts. For example, bit lines corresponding to memory cells in bottom array subsection 100a may be coupled to bit line decoders in bit line decoder subsection 110a through bottom cell bit line contacts, while bit lines corresponding to memory cells in bottom array subsection 100b may be coupled to bit line decoders in bit line decoder subsection 110b through bottom cell bit line contacts. Likewise, word lines corresponding to memory cells in the bottom array subsection 100a may be coupled to word line decoders in word

line decoder subsections

120a and 120b through word line contacts, while word lines corresponding to memory cells in the bottom array subsection 100b may be coupled to word line decoders in word

line decoder subsections

120c and 120d through word line contacts. The word line decoder and the bit line decoder arranged in their respective sub-portions are operable to selectively activate the word lines and the bit lines in their respective sub-portions. Although not shown, the word line contacts and bit line contacts may generally be located in the same region as the word line decoder and bit line decoder to which they are coupled, as will be further described with respect to fig. 7A.

In this embodiment, since the word line for the cell array is divided into horizontally offset portions, the word line decoder for the cell array is located at a position along the horizontal middle of the sub-portion of the memory cell array, not along the horizontal middle of the memory cell array. Thus, as shown, word

line decoder sub-portions

120a and 120b are located along the horizontal middle of bottom cell array sub-portion 100a, while word

line decoder sub-portions

120a and 120b are located along the horizontal middle of bottom cell array sub-portion 100 b.

The architecture of fig. 5A allows the bit lines to be introduced in the area provided for the word line decoder, but excludes the area provided for the word line contacts. In addition, the architecture of FIG. 5A also allows memory cells to be included in the area provided for the word line decoder, but excludes the area provided for the word line contacts. That is, the architecture of fig. 5A does not require a region dedicated to the word line decoder that is much larger than the region dedicated to the word line contacts, thus allowing for a higher storage density and higher efficiency architecture relative to existing architectures.

In the embodiment of FIG. 5A, the set of bottom cell bit lines 105 includes those in the area of word

line decoder subsections

120a, 120b, 120c, and 120 d. For example, the bottom cell bit line in the region for the word line decoder may be arranged in a region directly above or directly below the depth or Z direction of the word

line decoder subsections

120a, 120b, 120c, and 120d, but it does not include the region provided for the word line contacts. Further, in the embodiment of FIG. 5A, memory cells are included in the areas of word

line decoder subsections

120a, 120b, 120c, and 120d, but excluding the area provided for word line contacts. For example, the memory cells in the region of the word line decoder may be arranged in a region directly above or directly below the depth direction of the word

line decoder sub-sections

120a, 120b, 120c, and 120 d. These relationships will be further described with reference to fig. 7B and 7C.

Fig. 5B shows how the bottom cell array architecture of fig. 5A overlaps with the top cell array 200. The embodiment of fig. 5B includes all of the features of the embodiment of fig. 5A including similarly arranged memory cells, word lines, bit lines. The top cell array 200 is arranged above the bottom cell array 100 in the depth of the Z direction. The top cell array 200 is offset from the bottom cell array 100 in the vertical direction. In this aspect, the vertical offset may be a predetermined distance, such as a portion of the length of the bottom cell array 100 (or the top cell array 200). In the illustrated example, the top cell array 200 is offset in the vertical direction by half the length of the bottom cell array 100 (or the top cell array 200) as compared to the bottom cell array 100.

The top cell array 200 of memory cells may also be divided into sub-sections. For example, as shown, the top cell array 200 is divided into two top cell array subsections 200a and 200b that overlap with the bottom

cell array subsection

100a and 100b, respectively. The top unit array sub-section 200a is vertically offset from the bottom unit array sub-section 100a by a predetermined distance, and the top unit array sub-section 200b is vertically offset from the bottom unit array sub-section 100b by a predetermined distance.

The embodiment of FIG. 5B includes a top cell bit line decoder arranged in a subsection. The top cell bit line decoders are shown arranged in a first bit line decoder subsection 210a and a second bit line decoder subsection 210 b. The bit line decoder in subsection 210a may correspond to the memory cells in top cell array subsection 200a, while the bit line decoder in subsection 210b may correspond to the memory cells in top cell array subsection 200 b.

In addition, the embodiment of FIG. 5B also includes word line decoders also arranged in the subsections. The top cell array 200 may share one or more word lines with the bottom cell array 100. In this way, the top cell array 200 may also share one or more word line decoders with the bottom cell array 100. Thus, the top cell word line decoders in word

line decoder subsections

120b and 120d are shared with the top cell array 200. Other top cell word line decoders in word line decoder subsections 220a and 220b (and corresponding word lines) may be shared with another bottom cell array (not shown here, but shown in fig. 6).

The architecture of fig. 5B allows the introduction of bit lines and memory cells into the area provided for the word line decoder in a two-layer stack, which further improves storage density and efficiency relative to existing architectures. Efficiency is further improved because the elements are shared between the arrays.

Fig. 6 is a plan view of a portion of a three-dimensional phase change memory according to the embodiment of fig. 5A and 5B. The portion in fig. 6 may be formed of a plurality of portions as shown in fig. 5B. In this manner, the first bottom cell array 610 overlaps the first top cell array 620. In turn, the first top cell array 620 overlaps the second bottom cell array 630, and the second bottom cell array 630 also overlaps the second top cell array 640. Further, as shown, the pattern in the column may be repeated in one or more other columns. The embodiment of fig. 6 includes all of the features of the embodiments of 5A and 5B. For example, the memory cells, word lines, bit lines, word line and bit line contacts, and word line and bit line decoders in each array in fig. 6 may be similarly arranged as described with respect to fig. 5A and 5B.

Fig. 6 also shows how word lines extend partially through adjacent arrays. As shown, a portion of the word lines 650 extend from an area overlapping the first bottom cell array 610 to an area overlapping a horizontally adjacent bottom cell array 660. In this example, the partial word line 650 extends from the second bottom cell array sub-portion 612 of the first bottom cell array 610 through the first bottom cell array sub-portion 661 of the horizontally adjacent bottom cell array 660 into the second bottom cell array sub-portion 662 of the horizontally adjacent bottom array 660. Specifically, the partial word lines 650 extend from the middle of the second bottom cell array sub-portion 612, across the entire width of the first bottom cell array sub-portion 661, to the middle of the second bottom cell array sub-portion 662. This example also shows that another portion of the word lines 670 extend from the first bottom cell array subsection 661 to the second bottom cell array subsection 662 into the first bottom cell array subsection of another horizontally adjacent cell (not shown). Thus, the word lines 650 and 670 of these portions are horizontally offset from each other.

7A-7C are various views of a portion of a three-dimensional phase change memory according to the embodiment of FIGS. 5A and 5B. Fig. 7A is a plan view, and fig. 7B and 7C are cross-sectional views. The portions in fig. 7A-C may be formed from multiple portions as shown in fig. 5B. The embodiment of fig. 7A-7C includes all of the features of the embodiment of fig. 5A and 5B. For example, the memory cells, word lines, bit lines, word line and bit line contacts, and word line and bit line decoders in each of the arrays in fig. 7A-C may be similarly arranged as described with respect to fig. 5A and 5B. Figures 7A-C are provided to illustrate the positioning of word line and bit line contacts relative to word lines and bit lines.

Referring to fig. 7A, a bottom cell array 700 is highlighted, which may be configured similarly to the bottom cell array 100 of fig. 5A. As shown, the bottom cell array 700 is divided into two bottom

cell array subsections

700a and 700 b. The first portion of bottom cell bit lines 710a extends along the length of bottom cell array subsection 700a and the second portion of bottom cell bit lines 710b extends along the length of bottom cell array subsection 700 b. A first set of bottom cell bitline contacts 720a is provided along a vertical middle of the first portion of the bottom cell bitline 710a and a second set of bottom cell bitline contacts 720b is provided along a vertical middle of the second portion of the bottom cell bitline 710 b.

In this example, the two bottom

cell array subsections

700a and 700b are offset from each other in the vertical Y-direction. Likewise, the first portion of bottom cell bit lines 710a and the second portion of bottom cell bit lines 710b also have a vertical offset between them. Since the bitline contacts are placed along the vertical middle of the bitline, the first set of bottom cell bitline contacts 720a and the second set of bottom cell bitline contacts 720b also have a vertical offset between them. In this regard, the vertical offsets between bottom cell array sub-portions, between portions of the bottom cell bit lines, and between bottom cell bit line contacts may be different or the same as one another (as shown). The vertical offset may be a predetermined length (e.g., a fraction of the length of the bottom cell array 700). In this particular example shown, the vertical offset is less than half the length of the bottom cell array subsection 700a (or 700 b).

Above the first set of bottom cell bitline contacts 720a, a first portion of wordlines 730a extend from horizontally adjacent first cells through the first bottom cell array subsection 700a into the second bottom cell array subsection 700 b. A first set of word line contacts 740a is provided along a horizontal middle of a first portion of the word line 730a to couple the first portion of the word line 730a to a first set of word line decoders (not shown, but may be in substantially the same area as the word line contacts 740a) in a first word line decoder subsection. Below the first set of bottom cell bit line contacts 720a, a second portion of word lines 730b also extend from the first horizontally adjacent cell through the first bottom cell array subsection 710a to the second bottom cell array subsection 710 b. A second set of word line contacts 740b is provided along a horizontal middle of the second portion of word lines 730b to couple the second portion of word lines 730b to a second set of word line decoders (not shown, but may be in substantially the same area as the word line contacts 740 b) in a second word line decoder subsection.

Above the second set of bottom cell bitline contacts 720b, a third portion of the wordline 730c extends from the bottom cell array subsection 700a through the second subsection 700b into the area of the second horizontally adjacent cell. A third set of word line contacts 740c is disposed along a horizontal middle of the third portion of the word lines 730c to couple the third portion of the word lines 730c to a third set of word line decoders (not shown, but may be in substantially the same area as the word line contacts 740 c) in a third word line decoder subsection. A fourth portion of word lines 730d extends from the bottom cell array subsection 700a through the second bottom cell array subsection 700b into the area of the second horizontally adjacent cell, under the second set of bottom cell bit line contacts 720 b. A fourth set of word line contacts 730d is provided along the horizontal middle of the fourth portion's word line 730d to couple the fourth portion's word line 730d to a fourth set of word line decoders (not shown, but may be in substantially the same area as the word line contacts 740 d) in a fourth word line decoder subsection. Although not shown, the word line decoder may typically be located in the same area as the word line contacts.

Accordingly, the first portion of word lines 730a and the second portion of word lines 730b are horizontally offset from the third portion of word lines 730c and the fourth portion of word lines 730d, respectively. The horizontal offset may be a predetermined distance (e.g., a portion of the length of the bottom cell array 700). In this particular example, the predetermined distance is half the width of the first bottom cell array subsection 700a (or the second bottom cell array subsection 700 b). Because the word line contacts are located along the horizontal middle of the word lines, the first and second sets of

word line contacts

740a and 740b are also horizontally offset from the third and fourth sets of

word line contacts

740b and 740d, respectively. The horizontal offset may be a predetermined distance that is different from or the same as (as shown) the offset between the various portions of the word line.

Thus, by introducing an offset between a word line and a bit line, an offset is also introduced to the respective word line contact, bit line contact, word line decoder and bit line decoder. Due to the distributed positioning of these elements, the bit lines and memory cells may occupy an area that overlaps the word line decoder (except for the area occupied by the word line contacts). While fig. 7A appears to show that the bit lines do not overlap the area of the word line contacts because a large spacing is used for ease of illustration, such overlap between the top cell bit lines and the word line contacts is possible and increases the efficiency of the memory structure, overlap between the bottom cell bit lines and the word line contacts is not allowed.

Fig. 7B shows a cross section of the memory shown in fig. 7A along the vertical direction or Y direction. As shown, the bottom cell array 700 includes a first level of memory cells 810. Under the first tier of memory cells 810, bit lines and bit line contacts are provided. For example, two portions of bottom cell bitlines may be provided (only 710a is visible from this cross-section), and two sets of bottom

cell bitline contacts

720a and 720b may be provided. Above the first level of memory cells 810, word lines and word line contacts are provided. For example, four portions of word lines may be provided, only two

portions

730a and 730b being visible from this view, and four sets of word line contacts may be provided, only two

sets

740a and 740b being visible from this view. Depending on the implementation, the bottom cell bit line will block the passage of the word line contact.

Fig. 7B further illustrates a top cell array 750 partially overlapping the bottom cell array 710. The top cell array 750 includes a second layer of memory cells 820. Over the second tier of memory cells 820, two portions of the top cell bitline may be provided (only 760a visible), and two sets of top cell bitline contacts may be provided (only 770a visible). Under the second tier of memory cells 820, word lines and word line contacts are provided, some of which may be shared with the bottom cell array 700. For example, the top cell array 750 may include four portions of word lines (where only two

portions

780a and 730a are visible from this view) and four sets of word line contacts (where only 740a is visible from this view). Thus, the top cell bit line and the top cell memory cell are provided in a region overlapping with the region of the word line contact. Although not shown, the word line decoder and the bit line decoder may generally be located in the same region as the corresponding word line contacts and bit line contacts, respectively.

Fig. 7C shows a cross section of the memory shown in fig. 7A along the horizontal direction or X direction. In this view, many of the same elements in the bottom cell array 710, the top cell array 750, and FIG. 7B are shown and labeled as such. From this view, two portions of bottom

cell bit lines

710a and 710b can be seen, and two portions of top

cell bit lines

760a and 760b can be seen. Further, two sets of bottom

cell bitline contacts

720a and 720b can be seen, while the set of top cell bitline contacts can fall on the bottom

cell bitline contacts

720a and 720 b. From this view, two portions of

word lines

730a and 730c and corresponding

word line contacts

740a and 740c can be seen. Thus, as shown, in the region overlapping with the region of the word line decoder, the bottom cell bit line and the top cell bit line and the memory cell are provided.

Fig. 8 is a plan view of a portion of a three-dimensional phase change memory according to another example embodiment. Fig. 8 shows a plurality of bottom cell arrays including a bottom cell array 800, and a plurality of top cell arrays including a top cell array 850. The bottom cell array 800 is shown as being divided into two bottom

cell array subsections

800a and 800 b. As further shown, the bottom

cell array subsections

800a and 800b are horizontally offset, rather than vertically offset as in the embodiment shown in fig. 5A-7C. The horizontal shift amount may be a predetermined distance, and for example, the horizontal shift amount may be a part of the width of the element array in the X direction. In the particular example shown, the horizontal offset is less than half the width of the bottom

cell array subsection

800a or 800 b.

Due to the offset between the two bottom

cell array sub-portions

800a and 800b, the word line 810a corresponding to the first portion of the first bottom cell array sub-portion 800a may have a horizontal offset from the word line 810b corresponding to the second portion of the second bottom cell array sub-portion 800 a. Word line contacts and word line decoders may also be provided along the horizontal middle of the respective word lines, and thus may also be horizontally offset from each other. For example, a first set of word line decoders in the first word line decoder subsection 820a may be coupled to a horizontal middle portion of the first portion of word lines 810a through a first set of word line contacts (not shown), while a second set of word line decoders in the second word line decoder subsection 820b may be coupled to a horizontal middle portion of the second portion of word lines 810b through a second set of word line contacts (not shown).

Further, the bottom cell bit line may also be divided into several parts, but since there is no vertical offset between the bottom cell array sub-parts 800a and 800b, the two parts of the bottom cell bit lines 830a and 830b may be vertically aligned in the Y-direction. However, the bottom cell bit line decoder may be arranged in vertically offset sub-sections. For example, as shown, a first set of bottom cell bit line decoders may be provided in a first bit line decoder subsection 840a, where the first bit line decoder subsection 840a is slightly offset from the vertical middle of the first portion of the bottom cell bit lines 830 a. Likewise, a second set of bottom cell bit line decoders may be provided in a second bit line decoder subsection 840b, where the second bit line decoder subsection 840b is slightly offset from the vertical middle of the first section of bit lines 830 b. The vertical offset may be a predetermined distance, for example, a portion of the length of the bottom cell array 800. In this particular example, the predetermined distance is less than half the length of the first bottom cell array subsection 800a (or the second bottom cell array subsection 800 b). Bit line contacts may still be placed along the vertical middle of the corresponding bit lines. Accordingly, between portions of the bottom cell bit lines and the corresponding bottom cell bit line decoders (e.g., between the bottom cell bit line 830a of the first portion and the first set of bottom cell bit line decoders in sub-portion 840 a), routing, such as through conductive traces or wires, may be required.

As further shown, the top cell array 850 is configured similarly to the bottom cell array 800, except for being vertically offset in the Y-direction. For example, the top cell array 850 is divided into two top

cell array subsections

850a and 850b that are horizontally offset from each other. The word lines are divided into portions, some of which may be shared with the bottom cell array 800. For example, the word lines for the top cell array 850 may include: a second portion of word lines 810b shared with the bottom cell array 800 for the top cell array subsection 850a, and a portion of word lines 860a for the top cell array subsection 850 b. The word line contacts and decoders may also be divided into word line decoder subsections, such as those in the second word line decoder subsection 820b that are shared with the bottom cell array 800, and those in the word line decoder subsection 870 a. The top cell array 850 may include vertically aligned top cell bit lines (e.g., a first portion of top cell bit lines 880a and a second portion of top cell bit lines 880 b). As shown, a top cell bit line decoder may be provided in top cell bit

line decoder subsections

890a and 890b (which are slightly offset from the vertical middle of the portions of top

cell bit lines

880a and 880 b). Routing, e.g., via conductive traces or wires, may be provided between bit line contacts located in the vertical middle of the bit lines to reach the decoders in the

respective decoder subsections

890a and 890 b.

The architecture of fig. 8 allows the top cell bit line to be introduced into the area provided for the word line decoder and the bottom cell bit line to be introduced into the area provided for the word line decoder (except for the area provided for the word line contacts). For example, the bit lines in the region of the word line decoder may be arranged in a region directly above or below the depth or Z direction of the word line decoder subsection. Furthermore, the architecture of fig. 8 allows for the inclusion of the top cell memory cell in the area provided for the word line decoder and the introduction of the bottom cell memory cell into the area provided for the word line decoder (in addition to the area provided for the word line contacts). For example, the memory cells in the region of the word line decoder may be arranged in a region directly above or below the depth or Z direction of the word line decoder subsection. That is, the architecture of FIG. 8 does not require a region dedicated to the word line decoder, thus allowing for a higher storage density and higher efficiency architecture relative to existing architectures.

Fig. 9A-C illustrate a portion of a three-dimensional phase change memory according to another exemplary embodiment. Fig. 9A highlights assemblies of a bottom cell array in an exemplary embodiment, fig. 9B highlights assemblies of a top cell array in an exemplary embodiment, and fig. 9C shows assemblies of a bottom cell array and a top cell array in a stack.

Referring to fig. 9A, a plurality of bottom cell arrays including a bottom cell array 900 are divided into two bottom cell array sub-sections 900a and 900 b. As further shown, the bottom cell array subsections 900a and 900b are vertically offset. The vertical shift amount may be a predetermined distance, and for example, the vertical shift amount may be a part of the length of the cell array in the Y direction. In the particular example shown, the vertical offset is less than half the length of the bottom cell array subsection 900a (or 900 b). The bottom cell bit lines may be arranged in vertically offset sections. For example, the bottom cell bit line 930a of the first portion may be vertically offset from the bottom cell bit line 930b of the second portion. Because the bottom cell bit lines are vertically offset, the bottom cell bit line decoders and contacts may be similarly arranged in a vertical offset. For example, a first set of bottom cell bit line decoders disposed in bottom cell bit line decoder subsection 940a may be vertically offset from a second set of bottom cell bit line decoders disposed in bottom cell bit line decoder subsection 940 b.

The word lines are arranged in horizontally offset portions. For example, the first portion of word lines 910a and the second portion of word lines 910b are horizontally offset from the third portion of word lines 910c and the fourth portion of word lines 910d, respectively. These offsets are created because the word lines extend from the horizontally adjacent bottom cell array into the bottom cell array 900, similar to that described with reference to FIG. 7A. The horizontal shift amount may be a predetermined distance, and for example, the horizontal shift amount may be a part of the width of the cell array in the Y direction. In this particular example shown, the horizontal offset is less than half the width of the bottom cell array subsection 900a (or 900 b). Because the word lines are horizontally offset, the word line decoders and contacts may similarly be arranged in a horizontal offset. For example, a first set of word line decoders disposed in word line decoder subsection 920a and a second set of word line decoders disposed in word line decoder subsection 920b may be horizontally offset from a third set of word line decoders disposed in word line decoder subsection 920c and a fourth set of word line decoders disposed in word line decoder subsection 920d, respectively.

Referring to fig. 9B, a top cell array 950 is configured similarly to the bottom cell array 900 of fig. 9A (except for being vertically shifted in the Y direction). For example, the top cell array 950 is divided into two top

cell array subsections

950a and 950b that are horizontally offset from each other. The word lines are divided into two portions that can be shared with the bottom cell array 900. For example, the word lines for the top cell array subsection 950a may include a portion of the word line 960a, and a portion of the word line 910a shared with the bottom cell array subsection 900 a. The word lines for the top cell array subsection 950b may include a portion of word line 960c, and a portion of word line 910c shared with the bottom cell array subsection 900 b. The word line contacts and decoders may also be divided into word line decoder subsections, such as those in word

line decoder subsections

970a and 970c, and those in word

line decoder subsections

920a and 920c that are shared with the bottom cell array 900. The top cell array 950 may include vertically offset top cell bit lines (e.g., a first portion of top cell bit lines 980a and a second portion of top cell bit lines 980 b). As shown, the top cell bit line decoders may be provided in top cell bit

line decoder subsections

990a and 990b along the vertical middle of the sections of the top

cell bit lines

980a and 980b, respectively.

Fig. 9C is substantially a superposition of fig. 9A and 9B except that the mark indicating the bit line is deleted. Fig. 9C is provided to illustrate an offset arrangement of decoder subsections. For example, FIG. 9C thus shows that

word line sub-portions

920a, 920b, and 970a are horizontally offset from word line sub-portions 920C, 920d, and 970C. Fig. 9C also shows bottom cell bit line decoder subsection 940a vertically offset from bottom cell decoder subsection 940b and top cell bit line decoder subsection 990a vertically offset from bottom cell decoder subsection 990 b.

The architecture of fig. 9A-C allows the top cell bit line to be introduced into the area provided for the word line decoder and the bottom cell bit line to be introduced into the area provided for the word line decoder (except for the area provided for the word line contacts). For example, the bit lines in the region of the word line decoder may be arranged in a region directly above or below the depth or Z direction of the word line decoder subsection. In addition, the architecture of fig. 9A-C allows for the inclusion of the top cell memory cell in the area provided for the word line decoder and the introduction of the bottom cell memory cell into the area provided for the word line decoder (in addition to the area provided for the word line contacts). For example, the memory cells in the region of the word line decoder may be arranged in a region directly above or below the depth or Z direction of the word line decoder subsection. That is, the architecture of FIGS. 9A-C does not require an area dedicated to word line decoders, thus allowing for a higher storage density and higher efficiency architecture relative to existing architectures.

Most of the foregoing alternatives are not mutually exclusive and can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order (e.g., reversed or performed concurrently). Steps may also be omitted unless otherwise noted. Additionally, the provision of examples described herein, as well as terms expressed as "such as," "including," and the like, should not be construed to limit claimed subject matter to the particular examples; rather, these examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a bottom cell array of memory cells arranged in a first bottom cell array subsection and a second bottom cell array subsection, wherein the first bottom cell array subsection and the second bottom cell array subsection are offset;

a bottom cell bit line coupled to the bottom cell array of memory cells, the bottom cell bit line comprising a first portion of bottom cell bit lines and a second portion of bottom cell bit lines;

a first bottom cell bit line decoder subsection having a first set of bottom cell bit line decoders coupled to and operable to selectively activate bottom cell bit lines of the first portion and a second bottom cell bit line decoder subsection having a second set of bottom cell bit line decoders coupled to and operable to selectively activate bottom cell bit lines of the second portion;

a top cell array of memory cells over the bottom cell array of memory cells in a depth direction, the top cell array of memory cells arranged into a first top cell array subsection and a second top cell array subsection, wherein the first top cell array subsection and the second top cell array subsection are offset;

a top cell bit line coupled to the top cell array of memory cells, the top cell bit line comprising a first portion of top cell bit lines and a second portion of top cell bit lines;

a first top cell bit line decoder subsection having a first set of top cell bit line decoders coupled to and operable to selectively activate top cell bit lines of the first portion and a second top cell bit line decoder subsection having a second set of top cell bit line decoders coupled to and operable to selectively activate top cell bit lines of the second portion;

a word line coupled to the bottom cell array of memory cells and to the top cell array of memory cells, the word line comprising at least two offset word line portions;

a plurality of word line decoder sub-portions including at least one set of word line decoders coupled to the word lines of the first portion and operable to selectively activate the word lines of the first portion, and at least one set of word line decoders coupled to the word lines of the second portion and operable to selectively activate the word lines of the second portion.

2. The three-dimensional memory of claim 1, wherein the first bottom cell array subsection and the second bottom cell array subsection are offset in a vertical direction, the at least two word line sections are offset in a horizontal direction, and at least two of the plurality of word line decoder subsections are offset in a horizontal direction.

3. The three-dimensional memory of claim 2, wherein the first portion of bottom cell bit lines and the second portion of bottom cell bit lines are offset in the vertical direction, and the first bottom cell bit line decoder subsection and the second bottom cell bit line decoder subsection are offset in the vertical direction; and wherein the first portion of top cell bit lines and the second portion of top cell bit lines are offset in the vertical direction, and the first top cell bit line decoder subsection and the second top cell bit line decoder subsection are offset in the vertical direction.

4. The three-dimensional memory of claim 2, wherein the word line extends across a portion of the width of an adjacent cell array, across the width of one of the two bottom cell array sub-portions, and across a portion of the width of the other of the two bottom cell array sub-portions.

5. The three-dimensional memory of claim 2, wherein the bottom cell array of memory cells and the top cell array of memory cells are offset in the vertical direction by half a length of the bottom cell array of memory cells such that at least two word line portions and at least two word line decoder sub-portions are located in an overlapping region of the bottom cell array of memory cells and the top cell array of memory cells.

6. The three-dimensional memory of claim 2, wherein each of the plurality of word line decoder sub-portions is located in a horizontal middle of one of the first bottom cell array sub-portion, the second bottom cell array sub-portion, the first top cell array sub-portion, or the second top cell array sub-portion.

7. The three-dimensional memory of claim 2, wherein each of the plurality of word line decoder sub-portions is located at an offset from a horizontal middle of one of the first bottom cell array sub-portion, the second bottom cell array sub-portion, the first top cell array sub-portion, or the second top cell array sub-portion.

8. The three-dimensional memory of claim 2, further comprising:

word line contacts respectively connecting a horizontal middle portion of a corresponding one of the word lines to the word line decoder;

bottom cell bit line contacts respectively connecting a vertical middle portion of a respective one of the bottom cell bit lines to the bottom cell bit line decoder;

top cell bit line contacts respectively connecting a vertically middle portion of a respective one of the top cell bit lines to the top cell bit line decoder.

9. The three-dimensional memory of claim 1, wherein the first bottom cell array subsection and the second bottom cell array subsection are offset in a horizontal direction, and the at least two word line sections are offset in the horizontal direction, and the at least two word line decoder subsections are offset in the horizontal direction.

10. The three-dimensional memory of claim 9, wherein the first bottom cell bit line decoder subsection and the second bottom cell bit line decoder subsection are offset in a vertical direction, and the first top cell bit line decoder subsection and the second top cell bit line decoder subsection are offset in the vertical direction.

11. The three-dimensional memory of claim 9, further comprising:

bottom cell bit line contacts respectively connecting a vertically central portion of a respective one of the bottom cell bit lines to the bottom cell bit line decoder, wherein the bottom cell bit line decoder sub-portions are vertically offset from the vertically central portion of the bottom cell bit line;

top cell bit line contacts respectively connecting a vertical middle portion of a respective one of the top cell bit lines to the top cell bit line decoder, wherein the top cell bit line decoder sub-portion is vertically offset from the vertical middle portion of the top cell bit line.

12. A method of forming a three-dimensional memory, comprising:

providing a bottom cell array of memory cells, a top cell array of memory cells, a bottom cell bit line coupled to the bottom cell array of memory cells, a top cell bit line coupled to the top cell array of memory cells, a word line coupled to the top cell array of memory cells and to the bottom cell array of memory cells, a bottom cell bit line decoder coupled to the bottom cell bit line and operable to selectively activate the bottom cell bit line, a top cell bit line decoder coupled to the top cell bit line and operable to selectively activate the top cell bit line, and a word line decoder coupled to the word line and operable to selectively activate the word line;

forming the bottom cell array of memory cells into first and second bottom cell array sub-sections that are offset from each other and forming the top cell array of memory cells into first and second top cell array sub-sections that are offset from each other;

forming the word lines in a plurality of word line portions that are offset;

forming the word line decoder in offset word line decoder subsections;

forming the bottom cell bit line decoder in a phase-offset bottom cell bit line decoder subsection; and

the top cell bit line decoder is formed in a phase-offset top cell bit line decoder subsection.

13. The method of claim 12, wherein the first and second bottom cell array sub-portions are formed with an offset in a vertical direction, the first and second top cell array sub-portions are formed with an offset in the vertical direction, at least two of the word line portions are formed with an offset in a horizontal direction, and at least two of the word line decoder sub-portions are formed with an offset in the horizontal direction.

14. The method of claim 12 wherein at least two of the bottom-cell bit line decoder sub-portions are formed with an offset in a vertical direction and at least two of the top-cell bit line decoder sub-portions are formed with an offset in the vertical direction.

15. The method of claim 12, further comprising:

a majority of the area of the word line decoder is used to increase the efficiency of the three-dimensional memory.