CN111799332A - Groove MOSFET device and preparation method - Google Patents
Groove MOSFET device and preparation method Download PDFInfo
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- CN111799332A CN111799332A CN202010672209.8A CN202010672209A CN111799332A CN 111799332 A CN111799332 A CN 111799332A CN 202010672209 A CN202010672209 A CN 202010672209A CN 111799332 A CN111799332 A CN 111799332A
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- 238000002360 preparation method Methods 0.000 title abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 170
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 55
- 229920005591 polysilicon Polymers 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 23
- 238000009826 distribution Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention discloses a trench MOSFET device and a preparation method thereof, and relates to the field of semiconductor power devices. The method is used for solving the problems of poor reliability and weak peripheral withstand voltage of the conventional MOSFET peripheral withstand voltage. The method comprises the following steps: an active region trench, a peripheral trench and an epitaxial layer; the epitaxial layer is provided with the active region groove and the peripheral groove; the width of the peripheral groove is larger than that of the active region groove; the depth of the peripheral groove is greater than that of the active region groove; the distance between the peripheral grooves is equal to the distance between the active region grooves; the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active area groove.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a trench MOSFET device and a preparation method thereof.
Background
In the peripheral voltage-resistant design of a traditional power device MOSFET (Metal-Oxide-Semiconductor Field effect transistor, Chinese: Metal-Oxide-Semiconductor Field effect transistor), JTE (Junction Termination Extension) or a trench voltage-resistant terminal structure is mainly adopted at present, wherein the JTE structure utilizes a PN Junction to resist voltage, and the terminal structure has the defects that the diffusion of an outermost voltage-resistant ring is uncontrollable and needs to occupy a large terminal area due to the action of a thermal process in the process, so that the area of a working area of an actual device is compressed; the trench type terminal structure is mainly affected by the oxide layer inside the trench, the withstand voltage range is mainly in the low-voltage field, and when the device is subjected to external impact, the device is unstable and poor in reliability.
In summary, the conventional MOSFET has the problems of poor reliability and weak peripheral withstand voltage.
Disclosure of Invention
The embodiment of the invention provides a trench MOSFET device and a preparation method thereof, which are used for solving the problems of poor reliability and weak peripheral withstand voltage of the conventional MOSFET peripheral withstand voltage.
An embodiment of the present invention provides a trench MOSFET device, including: an active region trench, a peripheral trench and an epitaxial layer;
the epitaxial layer is provided with the active region groove and the peripheral groove;
the width of the peripheral groove is larger than that of the active region groove;
the depth of the peripheral groove is greater than that of the active region groove;
the distance between the peripheral grooves is equal to the distance between the active region grooves;
the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active area groove.
Preferably, a polysilicon layer is also included;
the polycrystalline silicon layer is arranged in the active region groove and the peripheral groove, the upper surface of the polycrystalline silicon layer in the active region groove has the same height with the grid oxide layer, and the upper surface of the polycrystalline silicon layer in the peripheral groove has the same height with the SAC oxide layer.
Preferably, the semiconductor device further comprises a P-type well region layer and an N-type source layer;
the P-type well region layer is positioned between the active region grooves and the peripheral grooves;
and the N-type source layer is arranged on the upper surface of the P-type well region layer positioned between the active region grooves.
Preferably, the semiconductor device further comprises a cut-off ring region groove, a source region metal layer, a peripheral cut-off region metal layer and a gate region metal layer;
the stop ring region groove is adjacent to the peripheral groove;
the source region metal layer is respectively contacted with the P-type well region layers positioned between the active region grooves and the peripheral grooves through contact hole metal layers;
the gate region metal layer is in contact with the polycrystalline silicon layer through the contact hole metal layer;
and the peripheral cut-off region metal layer is respectively contacted with the P-type well region layer positioned on one side of the cut-off ring region groove and the polycrystalline silicon layer positioned in the peripheral groove through the contact hole metal layer.
Preferably, the width of the peripheral trench is 1.5 times the width of the active region trench;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove.
The embodiment of the invention provides a preparation method of a trench MOSFET device, which comprises the following steps:
forming an active region trench and a peripheral trench in the epitaxial layer by an etching method; the width of the peripheral groove is larger than that of the active area groove, and the depth of the peripheral groove is larger than that of the active area groove;
forming SAC oxide layers on the epitaxial layer, in the active region groove and in the peripheral groove, wherein the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active region groove;
forming a polysilicon layer and a polysilicon annealing oxide layer on the SAC oxide layer and the gate oxide layer by deposition, etching and thermal oxidation processes;
forming a P-type well region layer and an N-type source layer between the active region trenches and between the active region and the peripheral trench by means of ion implantation;
and forming contact hole metal layers on the P-type well region layer and the polycrystalline silicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact holes.
Preferably, after forming the SAC oxide layer on the epitaxial layer, in the active region trench and in the peripheral trench, the method further includes:
photoetching and removing the active region groove and the SAC oxide layer on the upper surface of the active region groove through an SAC photomask;
and generating the grid electrode oxidation layer on the upper surfaces of the active region groove and the active region groove by a thermal oxidation method.
Preferably, the forming a P-type well region layer and an N-type source layer between the active region trenches and between the active region and the peripheral trench by ion implantation specifically includes:
forming the P-type well region layer among the active region grooves and the peripheral grooves through first ion implantation;
and forming N-type source region photoresist on the peripheral groove and between the peripheral groove and the active groove through a photoetching process, and forming an N-type source region layer on the P-type well region layer between the active region grooves through second ion implantation.
Preferably, the forming a contact hole metal layer on the P-type well region layer and the polysilicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact hole specifically includes:
forming silicon dioxide layers on the peripheral grooves and the active grooves through a deposition process, forming contact hole metal layers on the silicon dioxide layers through a photoetching process, and sequentially contacting the contact hole metal layers with the P-type well region layer between the active area grooves, the P-type well region layer between the active area grooves and the peripheral grooves and the polycrystalline silicon layer in the peripheral grooves to form a gate area metal layer and a source area metal layer.
Preferably, the width of the peripheral trench is 1.5 times the width of the active region trench;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove;
the method further comprises the following steps: forming a stop ring outside the peripheral trench.
An embodiment of the present invention provides a trench MOSFET device, including: an active region trench, a peripheral trench and an epitaxial layer; the epitaxial layer is provided with the active region groove and the peripheral groove; the width of the peripheral groove is larger than that of the active region groove; the depth of the peripheral groove is greater than that of the active region groove; the distance between the peripheral grooves is equal to the distance between the active region grooves; the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active area groove. The voltage-resistant area of the peripheral groove in the MOSFET device is designed to be a net structure, the width of the peripheral groove is larger than that of the groove of the active area, and the groove depth of the peripheral groove is larger than that of the groove of the active area, so that the electric field distribution of the active area and the peripheral boundary area can be optimized; the thickness of the SAC oxide layer on the peripheral groove is larger than that of the gate oxide layer on the active region groove, so that the problem that a device breaks down at the bottom of the groove can be effectively solved, and the voltage withstanding property of the device is improved; moreover, the distance between the active region grooves is equal to the distance between the peripheral grooves, so that the electric field distribution of the peripheral region can be improved, and the peripheral voltage resistance of the device is higher than that of the active region. The trench MOSFET device solves the problems of poor reliability and weak peripheral withstand voltage of the conventional MOSFET.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a trench MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic view illustrating a process for manufacturing a trench MOSFET device according to an embodiment of the present invention;
fig. 3A is a schematic view of an epitaxial layer preparation according to an embodiment of the present invention;
fig. 3B is a schematic diagram illustrating the preparation of an active region trench, a peripheral trench and a stop ring region trench according to an embodiment of the present invention;
FIG. 3C is a schematic diagram of the preparation of SAC oxide layer according to an embodiment of the present invention;
FIG. 3D is a schematic diagram of a SAC oxide layer with the active region and the stop ring removed according to an embodiment of the present invention;
fig. 3E is a schematic diagram illustrating a gate oxide layer prepared on the surface of the epitaxial layer at the active region position and the stop ring position according to the embodiment of the present invention;
FIG. 3F is a schematic diagram of a polysilicon layer according to an embodiment of the present invention;
FIG. 3G is a schematic diagram illustrating the preparation of an annealed oxide layer of polysilicon according to an embodiment of the present invention;
FIG. 3H is a schematic diagram illustrating the fabrication of a P-well region layer according to an embodiment of the present invention;
FIG. 3I is a schematic diagram illustrating fabrication of an N-type source layer according to an embodiment of the invention;
FIG. 3J is a schematic diagram illustrating the preparation of a silicon dioxide layer according to an embodiment of the present invention;
FIG. 3K is a schematic diagram illustrating a contact hole metal layer according to an embodiment of the present invention;
fig. 3L is a schematic view of a metal layer according to an embodiment of the invention.
The structure comprises a substrate layer 1, an epitaxial layer 2, an active region groove 3, a gate groove 4, a peripheral voltage-resistant region groove 5, a stop ring region groove 6, a SAC oxide layer 7, a gate oxide layer 8, a polycrystalline silicon layer 9, a polycrystalline silicon annealing oxide layer 10, a P-type well region layer 11, an N-type source region photoresist 12, an N-type source region layer 13, a silicon dioxide layer 14, a contact hole metal layer 15, a source region metal layer 17, a gate region metal layer 18, a peripheral stop region metal layer 19, a drain region metal layer 20 and a peripheral groove 45.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 schematically shows a structure of a trench MOSFET device according to an embodiment of the present invention, as shown in fig. 1, the trench MOSFET device mainly includes an active region trench, a peripheral trench, and an epitaxial layer.
As shown in fig. 1, the active region trench 3, the peripheral trench 45, and the stop ring region trench 6 are all disposed on the epitaxial layer 2, wherein the active region trench 3 and the stop ring region trench 6 are disposed on both sides of the peripheral trench 45, respectively. In the embodiment of the present invention, in order to optimize the electric field distribution of the active region and the peripheral interface region, it is preferable that, on the one hand, the depth of the peripheral trench 45 is greater than the depth of the active region trench 3; on the other hand, the width of the peripheral trench 45 is also larger than the width of the active region trench 3.
Further, in order to prevent the device from being broken down at the bottom of the trench, i.e., to improve the withstand voltage characteristic of the device, it is preferable that the thickness of the SAC (SAC Sacrificial) oxide layer in the peripheral trench 45 is greater than the thickness of the gate oxide layer 8 in the active region trench 3.
In practical application, the peripheral trench 45 includes a gate trench 4 and a peripheral voltage-withstanding region trench 5, where the gate trench 4 is located between the active region trench 3 and the peripheral voltage-withstanding region trench 5, and correspondingly, the peripheral voltage-withstanding region trench 5 is located between the gate trench 4 and the stop ring region trench 6. It should be noted that the peripheral trench 45 includes a plurality of gate trenches 4 and peripheral voltage-withstanding region trenches 5, and the plurality of peripheral trenches 45 are equally spaced from each other. In order to improve the electric field distribution in the peripheral region so that the withstand voltage of the periphery of the device is higher than that of the active region, it is preferable that the pitches between the plurality of peripheral trenches 45 and the active region trench 3 are also equal. Further, the gate trench 4 and the peripheral voltage-withstanding region trench 5 have the same width, and the gate trench 4 and the peripheral voltage-withstanding region trench 5 also have the same trench depth.
As shown in fig. 1, a polysilicon layer 9 is deposited in the active region trench 3, the gate trench 4, the peripheral withstand voltage region trench 5 and the stop ring region trench 6, since a gate oxide layer 8 is grown in the active region trench 3 and the stop ring region trench 6 through a thermal oxidation process, and a SAC oxide layer 7 is deposited in the gate trench 4 and the peripheral withstand voltage region trench 5, and the thickness of the SAC oxide layer 7 is larger than that of the gate oxide layer 8, therefore, when the polysilicon layer 9 deposited on the active region trench 3, the gate trench 4, the peripheral withstand voltage region trench 5 and the stop ring region trench 6 has different heights, specifically, as shown in fig. 1, the upper surface of the polysilicon layer 9 positioned in the active region trench 3 and the stop ring region trench 6 has the same height as the gate oxide layer 8, and the upper surface of the polysilicon layer 9 in the gate trench 4 and the peripheral withstand voltage region trench 5 has the same height as the SAC oxide layer 7.
Since the active region trenches 3 include a plurality of trenches, P-type well regions 11 are included between the active region trenches 3, and further, P-type well regions 11 are also included on one side of the off-ring region trench 6. As shown in fig. 1, the region of the active region trench 3 adjacent to the gate trench 4 also includes a P-type well region layer 11, and no P-type well region layer 11 is disposed between the off-ring region trench 6 and the peripheral voltage-withstanding region trench 5, but the other side of the off-ring region trench 6 includes a P-type well region layer 11.
Further, an N-type source layer 13 is further included on the P-type well region layer 11 between the active region trenches 3, and an N-type source layer 13 is also included on the P-type well region layer 11 on the side of the off ring region trench 6. And N-type source layer 13 is not included on P-type well region layer 11 adjacent to active region trench 3 and gate trench 4.
As shown in fig. 1, a contact hole metal layer 15 is disposed on the P-type well region layer 11 and the N-type source layer 13 between the active region trenches 3, a contact hole metal layer 15 is disposed on the P-type well region layer 11 between the active region trenches 3 and the gate trenches 4, and the two contact hole metal layers 15 are in contact with the active region metal layer; contact hole metal layers 15 are arranged on the P-type well region layer 11 and the N-type source layer 13 which are positioned on one side of the cut-off ring region groove 6, the contact hole metal layers 15 are arranged on the polycrystalline silicon layer 9 in the cut-off ring region groove 6, and the two contact hole metal layers 15 are in contact with the peripheral cut-off region metal layer 19; in order to ensure that the dynamic characteristics of the gate region are superior to those of other MOSfet devices, which is similar to the charge balance principle of the split gate MOSfet device, in the embodiment of the present invention, the contact hole metal layer 15 is disposed on the polysilicon layer 9 located in the gate trench 4, and the contact hole metal layer 15 is in contact with the gate region metal layer 18. Preferably, the contact hole metal layer 15 contacting the gate metal layer is surrounded by a trench on both sides, i.e., the polysilicon layer 9 contacting the contact hole metal layer 15 further has a plurality of polysilicon layers 9 on both sides thereof, and the polysilicon layers 9 each represent the polysilicon layer 9 disposed in the trench.
In the embodiment of the present invention, in order to optimize the electric field distribution in the peripheral interface region outside the active region, preferably, the widths of the gate trench 4 and the peripheral voltage-withstanding region trench 5 are 1.5 times the width of the active region trench 3, and the depths of the gate trench 4 and the peripheral voltage-withstanding region trench 5 are 0.2 μm greater than the depth of the active region trench 3.
In order to more clearly describe the trench MOSFET device provided in the embodiments of the present invention, a method for manufacturing the trench MOSFET device is described below.
Fig. 2 is a schematic view illustrating a process for manufacturing a trench MOSFET device according to an embodiment of the present invention; fig. 3A is a schematic view of an epitaxial layer preparation according to an embodiment of the present invention; fig. 3B is a schematic diagram illustrating the preparation of an active region trench, a peripheral trench and a stop ring region trench according to an embodiment of the present invention; FIG. 3C is a schematic diagram of the preparation of SAC oxide layer according to an embodiment of the present invention; FIG. 3D is a schematic diagram of a SAC oxide layer with the active region and the stop ring removed according to an embodiment of the present invention; fig. 3E is a schematic diagram illustrating a gate oxide layer prepared on the surface of the epitaxial layer at the active region position and the stop ring position according to the embodiment of the present invention; FIG. 3F is a schematic diagram of a polysilicon layer according to an embodiment of the present invention; FIG. 3G is a schematic diagram illustrating the preparation of an annealed oxide layer of polysilicon according to an embodiment of the present invention; FIG. 3H is a schematic diagram illustrating the fabrication of a P-well region layer according to an embodiment of the present invention; FIG. 3I is a schematic diagram illustrating fabrication of an N-type source layer according to an embodiment of the invention; FIG. 3J is a schematic diagram illustrating the preparation of a silicon dioxide layer according to an embodiment of the present invention; FIG. 3K is a schematic diagram illustrating a contact hole metal layer according to an embodiment of the present invention; fig. 3L is a schematic view of a metal layer according to an embodiment of the invention.
In the following, the manufacturing method flow diagram provided by fig. 2 is combined with the manufacturing diagrams provided by fig. 3A to 3L to describe in detail the manufacturing method of the trench MOSFET device, and specifically, as shown in fig. 2, the method mainly includes the following steps:
102, forming SAC oxide layers on the epitaxial layer, in the active region groove and in the peripheral groove, wherein the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active region groove
103, forming a polycrystalline silicon layer and a polycrystalline silicon annealing oxidation layer on the SAC oxidation layer and the grid oxidation layer through precipitation, etching and thermal oxidation processes;
104, forming a P-type well region layer and an N-type source layer between the active region grooves and between the active region and the peripheral groove in an ion implantation mode;
and 105, forming a contact hole metal layer on the P-type well region layer and the polycrystalline silicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact holes.
Specifically, as shown in fig. 3A, an N-type heavily doped semiconductor substrate layer 1 is provided, and then an N-type lightly doped epitaxial layer 2 is grown on the N-type heavily doped semiconductor substrate layer 1.
In step 101, as shown in fig. 3B, an active region trench 3, a peripheral trench 45, and a stop ring region trench 6 are sequentially formed in the N-type lightly doped epitaxial layer 2 by etching. Note that the peripheral trench 45 includes the gate trench 4 and the peripheral voltage-withstanding region trench 5.
In the embodiment of the present invention, in order to optimize the electric field distribution of the active region and the peripheral interface region, it is preferable that, on the one hand, the depth of the peripheral trench 45 is greater than the depth of the active region trench 3; on the other hand, the width of the peripheral trench 45 is also larger than the width of the active region trench 3. Further, in order to improve the electric field distribution in the peripheral region so that the withstand voltage in the periphery of the device is higher than the withstand voltage capability of the active region, it is preferable that the pitches between the plurality of peripheral trenches 45 and the active region trench 3 are also equal.
In step 102, as shown in fig. 3C, a sacrificial oxide layer is grown inside the N-type lightly doped epitaxial layer 2, the active region trench 3, the gate trench 4, the peripheral withstand voltage region trench 5, and the stop ring region trench 6 by a thermal oxidation process, and then an oxide layer is deposited by a chemical vapor deposition process, thereby forming a SAC oxide layer 7.
Further, as shown in fig. 3D, a SAC photomask is used for photolithography to remove the SAC oxide layer 7 in the active region trench 3 and on the upper surface of the epitaxial layer 2 on both sides of the active region trench 3, and to remove the SAC oxide layer 7 in the stop ring region trench 6 and on the upper surface of the epitaxial layer 2 on one side of the stop ring region trench 6. Note that the epitaxial layer 2 on the inner side of the stop ring region trench 6 indicates the side not adjacent to the peripheral withstand voltage region trench 5.
Further, as shown in fig. 3E, a gate oxide layer 8 is grown in the active region trench 3 and on the upper surface of the epitaxial layer 2 on both sides of the active region trench 3, in the stop ring region trench 6 and on the upper surface of the epitaxial layer 2 on one side of the stop ring region trench 6 by a thermal oxidation process. In the embodiment of the present invention, in order to prevent the device from being broken down at the bottom of the trench, that is, to improve the withstand voltage characteristic of the device, it is preferable that the thicknesses of the SAC oxide layer 7 in the gate trench 4 and the peripheral withstand voltage region trench 5 be greater than the thickness of the gate oxide layer 8 in the active region trench 3.
In step 103, as shown in fig. 3F, an N-type heavily doped polysilicon layer 9 is deposited on the upper surface of the SAC oxide layer 7 and the upper surface of the gate oxide layer 8 by a deposition process, that is, while the polysilicon layer 9 is formed in the active region trench 3, the gate trench 4, the peripheral voltage withstanding region trench 5, and the stop ring region trench 6, an N-type heavily doped polysilicon layer 9 is deposited on the gate oxide layer 8 on both sides of the active region trench 3 and on one side of the stop ring region trench 6, and an N-type heavily doped polysilicon layer 9 is deposited on the SAC oxide layer 7 on both sides of the gate trench 4 and the peripheral voltage withstanding region trench 5. Further, an N-type heavily doped polysilicon layer 9 is deposited on the gate oxide layer 8 on two sides of the active region trench 3 and one side of the stop ring region trench 6 and etched by a back etching process, and an N-type heavily doped polysilicon layer 9 is deposited on the gate trench 4 and the SAC oxide layer 7 on two sides of the peripheral pressure-resistant region trench 5 and also etched.
As shown in fig. 3G, annealing is performed by a thermal oxidation process to activate the doped elements inside the polysilicon layer 9, so as to grow a polysilicon annealed oxide layer 10 on the upper surface of the SAC oxide layer 7 and the upper surface of the gate oxide layer 8.
In step 104, as shown in fig. 3H, a P-type well region layer 11 is formed on the epitaxial layer 2 by a first implantation, where it should be noted that the P-type well region layer 11 is located between the active region trenches 3, between the active region trenches 3 and the gate trenches 4, and on one side of the stop ring region trench 6.
As shown in fig. 3I, an N-type heavily doped source region photoresist is formed on the polysilicon annealed oxide layer 10 through a photolithography process, and it should be noted that the N-type heavily doped source region photoresist includes a portion located on the SAC oxide layer 7 and a portion located above adjacent regions of the active region trench 3 and the gate trench 4. And forming N-type source regions in the P-type well region layers 11 at two sides of the active region groove 3 and forming N-type source regions in the P-type well region layers 11 at one side of the stop ring region groove 6 by a second injection mode. It should be noted that, since the N-type heavily doped source region photoresist is formed above the adjacent region between the active region trench 3 and the gate trench 4, no N-type source region is formed in the P-type well region layer 11 between the active region trench 3 and the gate trench 4.
Note that, in the first implantation, the upper surface of SAC oxide layer 7 is blocked by photolithography, and the upper surface of gate oxide layer 8 is exposed, so that P-type well region layer 11 is formed between active region trenches 3, between active region trenches 3 and gate trench 4, and on one side of stop ring region trench 6 by this implantation.
In step 105, as shown in fig. 3J, an isolation silicon dioxide layer 14 is deposited on the surface of the polysilicon annealed oxide layer 10 by a deposition process. Further, as shown in fig. 3K, a contact hole metal layer 15 is formed on the silicon dioxide layer 14 by means of etching and filling. Specifically, a contact hole metal layer 15 is arranged on the P-type well region layer 11 and the N-type source layer 13 between the active region trenches 3, and a contact hole metal layer 15 is arranged on the P-type well region layer 11 between the active region trenches 3 and the gate trenches 4; a contact hole metal layer 15 is arranged on the P-type well region layer 11 and the N-type source layer 13 which are positioned on one side of the cut-off ring region groove 6, and a contact hole metal layer 15 is arranged on the polycrystalline silicon layer 9 in the cut-off ring region groove 6; a contact hole metal layer 15 is disposed on the polysilicon layer 9 within the gate trench 4.
Sputtering a metal layer on the surface of the silicon dioxide layer 14 by a sputtering process, defining a source region metal layer 17, a gate region metal layer 18 and a peripheral cut region metal layer by photoetching and etching processes, thinning the wafer by a grinding process, and forming a drain region metal layer 20 by a metal evaporation process. As shown in fig. 3L, the contact hole metal layer 15 on the P-type well region layer 11 and the N-type source layer 13 between the active region trenches 3 and the contact hole metal layer 15 on the P-type well region layer 11 between the active region trenches 3 and the gate trenches 4 are both in contact with the active region metal layer; the contact hole metal layer 15 of the P-type well region layer 11 and the N-type source layer 13 positioned on one side of the cut-off ring region groove 6 and the contact hole metal layer 15 of the polycrystalline silicon layer 9 positioned in the cut-off ring region groove 6 are both in contact with the peripheral cut-off region metal layer 19; the contact hole metal layer 15 of the polysilicon layer 9 located in the gate trench 4 is in contact with the gate region metal layer 18. The drain region metal layer 20 is in contact with the lower surface of the substrate layer 1.
In summary, an embodiment of the present invention provides a trench MOSFET device, including: an active region trench, a peripheral trench and an epitaxial layer; the epitaxial layer is provided with the active region groove and the peripheral groove; the width of the peripheral groove is larger than that of the active region groove; the depth of the peripheral groove is greater than that of the active region groove; the distance between the peripheral grooves is equal to the distance between the active region grooves; the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active area groove. The voltage-resistant area of the peripheral groove in the MOSFET device is designed to be a net structure, the width of the peripheral groove is larger than that of the groove of the active area, and the groove depth of the peripheral groove is larger than that of the groove of the active area, so that the electric field distribution of the active area and the peripheral boundary area can be optimized; the thickness of the SAC oxide layer on the peripheral groove is larger than that of the gate oxide layer on the active region groove, so that the problem that a device breaks down at the bottom of the groove can be effectively solved, and the voltage withstanding property of the device is improved; moreover, the distance between the active region grooves is equal to the distance between the peripheral grooves, so that the electric field distribution of the peripheral region can be improved, and the peripheral voltage resistance of the device is higher than that of the active region. The trench MOSFET device solves the problems of poor reliability and weak peripheral withstand voltage of the conventional MOSFET.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A trench MOSFET device, comprising: an active region trench, a peripheral trench and an epitaxial layer;
the epitaxial layer is provided with the active region groove and the peripheral groove;
the width of the peripheral groove is larger than that of the active region groove;
the depth of the peripheral groove is greater than that of the active region groove;
the distance between the peripheral grooves is equal to the distance between the active region grooves;
the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active area groove.
2. The device of claim 1, further comprising a polysilicon layer;
the polycrystalline silicon layer is arranged in the active region groove and the peripheral groove, the upper surface of the polycrystalline silicon layer in the active region groove has the same height with the grid oxide layer, and the upper surface of the polycrystalline silicon layer in the peripheral groove has the same height with the SAC oxide layer.
3. The device of claim 2, further comprising a P-type well region layer and an N-type source layer;
the P-type well region layer is positioned between the active region grooves and the peripheral grooves;
and the N-type source layer is arranged on the upper surface of the P-type well region layer positioned between the active region grooves.
4. The device of claim 3, further comprising a stop-ring region trench, a source region metal layer, a peripheral stop region metal layer, and a gate region metal layer;
the stop ring region groove is adjacent to the peripheral groove;
the source region metal layer is respectively contacted with the P-type well region layers positioned between the active region grooves and the peripheral grooves through contact hole metal layers;
the gate region metal layer is in contact with the polycrystalline silicon layer through the contact hole metal layer;
and the peripheral cut-off region metal layer is respectively contacted with the P-type well region layer positioned on one side of the cut-off ring region groove and the polycrystalline silicon layer positioned in the peripheral groove through the contact hole metal layer.
5. The device according to any of claims 1 to 4,
the width of the peripheral groove is 1.5 times that of the active region groove;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove.
6. A method for manufacturing a trench MOSFET device, comprising:
forming an active region trench and a peripheral trench in the epitaxial layer by an etching method; the width of the peripheral groove is larger than that of the active area groove, and the depth of the peripheral groove is larger than that of the active area groove;
forming SAC oxide layers on the epitaxial layer, in the active region groove and in the peripheral groove, wherein the thickness of the SAC oxide layer in the peripheral groove is larger than that of the gate oxide layer in the active region groove;
forming a polysilicon layer and a polysilicon annealing oxide layer on the SAC oxide layer and the gate oxide layer by deposition, etching and thermal oxidation processes;
forming a P-type well region layer and an N-type source layer between the active region trenches and between the active region and the peripheral trench by means of ion implantation;
and forming contact hole metal layers on the P-type well region layer and the polycrystalline silicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact holes.
7. The method of claim 6, wherein after forming a SAC oxide layer on the epitaxial layer, in the active region trench and in the peripheral trench, further comprising:
photoetching and removing the active region groove and the SAC oxide layer on the upper surface of the active region groove through an SAC photomask;
and generating the grid electrode oxidation layer on the upper surfaces of the active region groove and the active region groove by a thermal oxidation method.
8. The method of claim 6, wherein the forming a P-type well region layer and an N-type source layer between the active region trenches and between the active region and the peripheral trench by ion implantation comprises:
forming the P-type well region layer among the active region grooves and the peripheral grooves through first ion implantation;
and forming N-type source region photoresist on the peripheral groove and between the peripheral groove and the active groove through a photoetching process, and forming an N-type source region layer on the P-type well region layer between the active region grooves through second ion implantation.
9. The method according to claim 6, wherein the forming of the contact hole metal layer on the P-type well region layer and the polysilicon layer, and the sequentially forming of the gate region metal layer and the source region metal layer through the contact holes comprises:
forming silicon dioxide layers on the peripheral grooves and the active grooves through a deposition process, forming contact hole metal layers on the silicon dioxide layers through a photoetching process, and sequentially contacting the contact hole metal layers with the P-type well region layer between the active area grooves, the P-type well region layer between the active area grooves and the peripheral grooves and the polycrystalline silicon layer in the peripheral grooves to form a gate area metal layer and a source area metal layer.
10. The method according to any one of claims 6 to 9, wherein the width of the peripheral trench is 1.5 times the width of the active region trench;
the depth of the peripheral groove is 0.2 microns more than the depth of the active region groove;
the peripheral groove comprises a grid groove and a peripheral voltage-resisting area groove;
the method further comprises the following steps: forming a stop ring outside the peripheral trench.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112234103A (en) * | 2020-11-04 | 2021-01-15 | 华羿微电子股份有限公司 | MOSFET device and preparation method thereof |
| CN113675078A (en) * | 2021-08-24 | 2021-11-19 | 江苏东海半导体科技有限公司 | Forming method of MOS device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112234103A (en) * | 2020-11-04 | 2021-01-15 | 华羿微电子股份有限公司 | MOSFET device and preparation method thereof |
| CN113675078A (en) * | 2021-08-24 | 2021-11-19 | 江苏东海半导体科技有限公司 | Forming method of MOS device |
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