CN111799210A

CN111799210A - Substrate processing carrier

Info

Publication number: CN111799210A
Application number: CN202010249030.1A
Authority: CN
Inventors: M·J·塞登
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-04-02
Filing date: 2020-04-01
Publication date: 2020-10-20
Also published as: DE102020002006A1

Abstract

The invention provides a substrate processing carrier. Implementations of the substrate carrier may include: a top ring configured to encapsulate an edge of the first side of the substrate; and a bottom support configured to encapsulate the entire second side of the substrate and an edge of the second side.

Description

Substrate processing carrier

Cross reference to related patent applications

This document claims benefit of the filing date of U.S. provisional patent application 62/827,982 entitled "substrate processing Carrier" (filed 2019 on 4/2) to Michael j.seddon, the disclosure of which is hereby incorporated by reference in its entirety.

This application is a continuation-in-part application of U.S. utility patent application entitled "Semiconductor Wafer and Probe Testing" previously assigned to Michael Seddon (patent serial No. 15/907,931, filed 2018 on 28.2.2017, now pending), which is U.S. patent application No. 15/704,246 (now filed on 14.9.2017, and published on 1.1.2019, which is a continuation-in-part application of U.S. patent application No. 15/230,875, which is now filed on 8.8.2016, and published on 10.17.2017), the disclosure of each of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor substrates and methods of probe testing.

Background

The semiconductor substrate includes a base substrate material. In various cases, the semiconductor die formed on the substrate may be thinned to minimize the size of the semiconductor package. The semiconductor die is tested and inspected for quality assurance and reliability.

Disclosure of Invention

Implementations of the substrate carrier may include: a top ring configured to encapsulate an edge of the first side of the substrate; and a bottom support configured to encapsulate the entire second side of the substrate and an edge of the second side.

Implementations of the substrate carrier may include one, all, or any of the following:

the edge may be an edge ring of the substrate.

The first side of the substrate may be a background.

The second side of the substrate may include a plurality of semiconductor dies therein.

The substrate may have a thickness of less than 39 microns.

The substrate may have a thickness of less than 10 microns.

The top ring may be configured to be coupled to the bottom support with a clamp, friction fit, snap, or hinge.

The substrate carrier may not be bonded to the substrate.

Implementations of the substrate carrier may include: a top ring configured to encapsulate an edge of the first side of the substrate; and a bottom support configured to encapsulate the entire second side of the substrate and an edge of the second side. The bottom support may also include a cavity therein configured to receive a backgrinding tape applied to the second side of the substrate.

the edge may be an edge ring of the substrate.

The first side of the substrate may be a background.

The substrate may have a thickness of less than 39 microns.

The substrate may have a thickness of less than 10 microns.

The substrate carrier may not be bonded to the substrate.

Implementations of an apparatus for testing semiconductor substrates may include: a substrate carrier including a top ring configured to encapsulate an edge of a first side of a substrate and a bottom support. The bottom support may be configured to allow electrical testing of a semiconductor substrate coupled to the substrate carrier using a probe.

Implementations of the apparatus for testing semiconductor substrates may include one, all, or any of the following:

the apparatus may also include one or more openings in the bottom support configured to allow the probes to directly contact the substrate during electrical testing.

The substrate carrier may be formed of metal, plastic coated in metal or metal coated in a secondary metal.

The substrate carrier may be formed of or may include a conductive material coupled thereto.

The above and other aspects, features and advantages will be apparent to one of ordinary skill in the art from the specification and drawings, and from the claims.

Drawings

Implementations will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and:

FIGS. 1a-1b illustrate a semiconductor wafer having a plurality of semiconductor dies separated by saw lanes;

FIGS. 2a-2h illustrate a method of thinning a semiconductor wafer with an edge support ring;

3a-3s illustrate a method of probe testing from the backside of a thinned semiconductor wafer through one or more openings in a tape portion of a film frame;

FIGS. 4a-4c illustrate a method of forming conductive pathways in a ribbon;

FIG. 5 is a side view of an implementation of a semiconductor substrate with an edge ring;

FIG. 6 is a side view of an implementation of a semiconductor substrate with an applied backgrinding tape;

FIG. 7 is a side view of an embodiment of a semiconductor substrate after it has been background to a first thickness;

FIG. 8 is a side view of an implementation of a substrate partially encapsulated by an implementation of a substrate carrier after it is background to a second thickness;

FIG. 9 is a side view of an implementation of a substrate that is partially encapsulated by an implementation of a substrate carrier after it is etched to a third thickness;

FIG. 10 is a side view of an implementation of a substrate partially encapsulated by a substrate carrier implementation having a locking mechanism;

FIG. 11 is a side view of a substrate implementation without an edge ring partially encapsulated by a substrate carrier implementation;

FIG. 12 is a top view of an implementation of a substrate partially encapsulated by an implementation of a substrate carrier;

FIG. 13 is a side view of a substrate implementation having an edge ring partially encapsulated by a substrate carrier implementation;

FIG. 14 is a top view of a substrate implementation having an edge ring partially encapsulated by a substrate carrier implementation; and is

FIG. 15 is a side view of a substrate carrier having an opening on the bottom of the carrier; and is

Fig. 16 is a side view of an embodied substrate carrier.

Detailed Description

The present disclosure, aspects, and implementations thereof, are not limited to the specific components, assembly procedures, or method elements disclosed herein. Many additional components, assembly procedures, and/or method elements known in the art to conform to the anticipated substrate processing carrier will be readily apparent for use with the specific implementations of the present disclosure. Thus, for example, although particular implementations are disclosed, such implementations and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc. known in the art for such substrate processing carriers and implementation components and methods consistent with the intended operation and method.

Semiconductor die/substrate testing typically involves contacting a surface of a semiconductor wafer with test probes. However, for thinning semiconductor wafers/substrates, wafer test probing can lead to breakage or damage from probe pressure on the thin wafer surface, as well as wafer handling and wafer warpage. Thin semiconductor wafers also experience warpage due to film stress. Warped thin semiconductor wafers are difficult to test because the test probes may not be in contact with the warped surface.

In some cases, wafer test probing may be performed before thinning of the wafer, because large thin wafers (e.g., wafers having a diameter of 150-300 millimeters (mm)) may warp beyond test probe contact tolerances, or because the thin wafer surface cannot handle the intrusive nature of the test. Wafer testing prior to wafer thinning may be incomplete because some features added after wafer thinning (e.g., backside metal) are not present to be used in testing. Furthermore, for MOSFETs or wafers with through-silicon vias, current flows through the silicon and out the back side of the thinned wafer, i.e., through the back side metal. Testing such devices is impractical for full thickness wafers because the structure to be tested does not exist until after thinning. The thickness of the wafer can also affect electrical performance. Thicker T-MOSFET wafers have a greater resistance than thin wafers because the current passes through more silicon. Wafer testing and inspection before all features are present reduces quality assurance and increases manufacturing costs because untested defective die must be assembled as untested die before functionality can be confirmed.

Fig. 1a shows a semiconductor wafer 100 with a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium nitride, indium phosphide, silicon carbide or other base semiconductor material. A plurality of semiconductor die 104 are formed on the wafer 100, separated by saw lanes 106, as described above. The saw streets 106 provide cutting areas to separate the semiconductor wafer 100 into individual semiconductor dies 104. In one implementation, the semiconductor wafer 100 has a width or diameter of 100-450mm and a thickness of 675-775 microns (μm). In another implementation, the semiconductor wafer 100 has a width or diameter of 150-300 mm.

Fig. 1b shows a cross-sectional view of a portion of the semiconductor wafer 100. Each semiconductor die 104 has a non-active back surface 108 and an active surface or region 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface or area 110 to implement analog circuits or digital circuits, such as Digital Signal Processors (DSPs), microcontrollers, ASICs, power conversion, standard logic, amplifiers, clock management, memory, interface circuits, and other signal processing circuits. Semiconductor die 104 may also include Integrated Passive Devices (IPDs), such as inductors, capacitors, and resistors, for radio frequency signal processing. Active surface 110 may contain image sensor regions implemented as semiconductor Charge Coupled Devices (CCDs) and active pixel sensors in Complementary Metal Oxide Semiconductor (CMOS) or N-type metal oxide semiconductor (NMOS) technology. Alternatively, the semiconductor die 104 may be an optical lens, a detector, a Vertical Cavity Surface Emitting Laser (VCSEL), a waveguide, a stacked die, an Electromagnetic (EM) filter, or a multi-chip module.

An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium Tungsten (TiW), or other suitable conductive material. Conductive layer 112 serves as an interconnect pad for electrical connection to circuitry on active surface 110.

In other implementations, semiconductor wafer 100 represents a stacked semiconductor wafer, a stacked semiconductor die on a wafer, a silicon-on-insulator type wafer, a stacked memory wafer, a memory device stacked on an ASIC wafer, a stacked conductive Through Silicon Via (TSV) semiconductor wafer, or any other configuration of a stacked wafer, a stacked die on a wafer, and a stacked device.

Figures 2a-2h illustrate a method of thinning a semiconductor wafer with an edge support ring. Fig. 2a shows the entire area of the semiconductor wafer 100 with the back surface 108 and the active surface 110. The semiconductor die 104 is present in the active surface 110, see fig. 1a-1b, but is not labeled for purposes of this description. The semiconductor wafer 100 has a pre-ground thickness T1 of 675-775 μm.

In fig. 2b, the semiconductor wafer 100 is inverted and mounted with the active surface 110 oriented to the backgrind strip 120. In fig. 2c, the entire back surface 108 is subjected to a first backgrinding operation using a grinding or grinding wheel 122 to move a portion of the base substrate material 102 down to the surface 124. Semiconductor wafer 100 has a back-ground thickness T of 355 μm between active surface 110 and surface 124₂。

In fig. 2d, a second grinding operation is applied to surface 124 using a grinding machine or wheel 128. The grinding wheel 128 moves in a cyclical rotational pattern across an interior region or wafer grinding region 130 of the semiconductor wafer 100 to move a portion of the base substrate material 102 down to the surface 134. The grinding wheel 128 is controlled such that an edge support ring 136 of base substrate material 102 surrounds the periphery of the semiconductor wafer 100 for structural support. In one implementation, the back-ground thickness T of the semiconductor wafer 100₃Is 75 μm or less. In another implementation, the back-ground thickness T of the semiconductor wafer 100₃Is 10-50 μm.

Fig. 2e shows a top view of grinding wheel 128, which removes a portion of surface 134 of semiconductor wafer 100 to reduce the thickness of the semiconductor wafer and corresponding semiconductor die 104 in grinding region 130, while leaving edge support ring 136 of base substrate material 102 around the perimeter of the semiconductor wafer. The edge support ring 136 has a thickness of 3.0mm from the inner wall 154 to the outer edge 156 surrounding the semiconductor wafer 100⁺Width W of 0.3mm₁₃₆. The height of the edge support ring 136 is the first back-grind thickness T₂Greater than the second back-grinding thickness T of the semiconductor wafer 100₃To maintain the structural integrity of the thinner semiconductor wafer.

In fig. 2f, a post-grinding stress relief etch is used to remove or reduce damage in the surface 134 of the base substrate material 102 caused by the grinding process. The surface 134 of the semiconductor wafer 100 is cleaned with a rinsing solution. Conductive layer 172 is formed over surface 134 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 172 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, or other suitable conductive material. Conductive layer 172 provides backside electrical interconnection for semiconductor die 104. Conductive layer 172 is connected to circuitry on active surface 110 through TSVs. The conductive layer 172 is patterned into electrically common or electrically isolated portions depending on the function of the semiconductor die 104. The backing tape 120 is removed by exposing the tape to Ultraviolet (UV) light and peeling.

In fig. 2g, the thinned semiconductor wafer 100 is mounted with the active surface 110 oriented to the tape portion 176 of the film frame or carrier 178. In FIG. 2h, edge support ring 136 is removed to have a flat surface or just above (10-13 μm) conductive layer 172 or surface 134.

Figures 3a-3s illustrate various configurations for probe testing semiconductor wafers. In fig. 3a, the thinned semiconductor wafer 100 is removed from the film frame 178 and positioned over a film frame or carrier 180 with the conductive layer 172 on the surface 134 oriented toward the film frame. The semiconductor die 104 on the thinned semiconductor wafer 100 has a complete set of features, i.e., all functional components and layers have been formed, ready for probe testing of the final semiconductor die. The film frame 180 includes a tape portion 182 and an edge support 184. In particular, the band portion 182 includes an opening 186 extending through a central region of the band portion. Thinned semiconductor wafer 100 is positioned over film frame 180 with conductive layer 172 aligned and centered with opening 186. Fig. 3b shows a top view of the film frame 180 with the band portion 182 and the opening 186 extending through a central region of the band portion. Semiconductor wafer 100 is mounted on tape portion 182 of film frame 180 with a portion of conductive layer 172 disposed over opening 186. Fig. 3c shows a top view of the semiconductor wafer 100 mounted on the tape portion 182 of the film frame 180. Conductive layer 172 is accessible through an opening 186 in strap portion 182.

In fig. 3d, the semiconductor wafer 100 and the film frame 180 are positioned over the surface 190 of the wafer probe chuck 194. The surface 190 has a lower portion 190a and a raised portion 190 b. The raised portion 190b is aligned with the opening 186. Fig. 3e shows film frame 180 with semiconductor wafer 100 mounted on surface 190 of wafer probe chuck 194, with tape portion 182 contacting lower portion 190a of surface 190 and raised portion 190b extending through opening 186 to contact conductive layer 172. In one implementation, wafer probe chuck 194 pulls a vacuum through port 193 to hold tape portion 182 and semiconductor wafer 100 securely in place, with surface 134 and a first portion of conductive layer 172 held flat against and in contact with tape portion 182, tape portion 182 held flat against and in contact with lower portion 190a of surface 190, and a second portion of conductive layer 172 held flat against and in contact with raised portion 190b of surface 190. In fig. 3f, a porous ceramic chuck 194 having the same surface 190 (including lower portion 190a and raised portion 190b) uniformly distributes the vacuum force to hold the semiconductor wafer 100 and film frame 180 flat against the lower portion 190a and raised portion 190b of the surface 190. The semiconductor wafer 100 and the film frame 180 are held flat against the lower portion 190a and the raised portion 190b of the surface 190 by the vacuum port 193 or the porous chuck 194, thereby keeping the wafer stable and flat during probe testing. Alternatively, tape portion 182 and semiconductor wafer 100 are held securely in place by a press fit with force F, as shown in fig. 3g, wherein surface 134 and a first portion of conductive layer 172 are held flat against and in contact with tape portion 182, tape portion 182 is held flat against and in contact with a lower portion 190a of surface 190 of chuck 195, and a second portion of conductive layer 172 is held flat against and in contact with a raised portion 190b of surface 190. The chuck 195 has the same surface 190 as the lower portion 190a and the raised portion 190 b.

As part of the quality control process, the semiconductor wafer 100 is subjected to electrical testing and inspection. The semiconductor wafer 100 is inspected using manual visual inspection and automated optical systems. Software may be used to perform automated optical analysis of the semiconductor wafer 100. The visual inspection method may employ equipment such as a scanning electron microscope, high intensity light or ultraviolet light, a metallographic microscope, or an optical microscope. The semiconductor wafer 100 is inspected for structural characteristics including warpage, thickness variation, surface particles, irregularities, cracking, delamination, contamination and discoloration.

Active and passive components within the semiconductor die 104 are subjected to wafer-level electrical performance and circuit function testing. Each semiconductor die 104 is tested for functional and electrical parameters. Raised portions 190b of surface 190 of wafer probe chuck 194 are in electrical contact with conductive layer 172 through openings 186. A computer controlled test system 196 sends electrical test signals through wafer probe chuck 194 and raised portions 190b of surface 190 extending through openings 186 to provide electrical stimulation to conductive layer 172. Alternatively, the computer controlled test system 196 sends electrical test signals through conductive channels in the wafer probe chuck 194 and the raised portions 190b of the surface 190 to provide electrical stimulation to the conductive layer 172. Conductive layer 172 is coupled to circuitry on active surface 110 through TSVs or vertically formed semiconductor devices. The semiconductor die 104 responds to the electrical stimulus, which is measured by the computer test system 196 and compared to an expected response to test the functionality of the semiconductor die.

Testing of semiconductor wafer 100 from the backside directly to conductive layer 172 is accomplished by raised portions 190b of surface 190 of wafer probe chuck 194 that extend through openings 186 in strap portion 182 of film frame 180. Many testing procedures may be performed using the wafer probe contact of raised portion 190b with conductive layer 172. For example, electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, radio frequency performance, drive current, threshold current, leakage current, and operating parameters specific to the component type. Testing is performed with the thinned semiconductor wafer 100 after wafer grinding. The thinned semiconductor wafer 100 remains flat and stable by the nature of the lower portion 190a and raised portion 190b of the surface 190 of the wafer probe chuck 194 held against the conductive layer 172. After wafer thinning, inspection and electrical testing of the semiconductor wafer 100 enables semiconductor dies 104 with a qualified full feature set to be designated as known qualified dies for semiconductor packages.

Wafer level testing also encompasses advanced testing procedures including curve tracking of the semiconductor wafer 100 or other characterization of devices to assess detailed electrical and thermal performance of thin or stacked wafers.

The semiconductor wafer 100 may also be tested from the active surface 110 as shown in fig. 3 h. Each semiconductor die 104 is tested for functional and electrical parameters using a test probe head 200 or other test equipment that includes a plurality of probes or test leads 202. Probes 202 are used to make electrical contact with nodes or conductive layers 112 on each semiconductor die 104 and provide electrical stimulation to interconnect pads 112. The semiconductor die 104 responds to the electrical stimulus, which is measured by the computer test system 206 and compared to an expected response to test the functionality of the semiconductor die. Electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, radio frequency performance, drive current, threshold current, leakage current, and operating parameters specific to the component type. The inspection and electrical testing of the semiconductor wafer 100 enables the semiconductor die 104 that are qualified for inspection to be designated as known qualified die for the semiconductor package.

The band portion may have multiple openings to provide access to different areas of the conductive layer 172. As described above, the conductive layer 172 is patterned into electrically common or electrically isolated portions, depending on the function of the semiconductor die 104. Fig. 3i shows a top view of a membrane frame 210 comprising a band portion 212, edge supports 214, and a plurality of openings 216. The strip portion 212 has as many openings 216 as necessary to test the necessary areas of the conductive layer 172. The opening 216 may be cut or die cut through the belt portion 212 prior to mounting the belt portion to the edge support 214, or after mounting the belt portion to the edge support. Cutting the opening 216 prior to mounting the strap portion 212 to the edge support 214 allows a standard cut pattern to match a particular wafer 100, such as a punched strap. The cut-out openings 216 after mounting the tape portion 212 to the edge support 214 allow for a cut-out pattern customized for a particular wafer 100. The opening 216 may be cut using a laser or a blade, or simply a precut portion of the tape removed.

The semiconductor wafer 100 is then mounted to the tape portion 212 as shown in fig. 3 j. In this case, the wafer probe chuck 194 will have a plurality of raised portions 190b aligned with the openings 216. A film frame 210 having a semiconductor wafer 100 is mounted to the surface 190 of the wafer probe chuck 194 with a tape portion 212 contacting a lower portion 190a of the surface 190 and a plurality of raised portions 190b extending through a plurality of openings 216 to contact different areas of the conductive layer 172. The tape portion 212 and semiconductor wafer 100 are held securely in place by a press fit or vacuum assist, with the surface 134 and a first portion of the conductive layer 172 held flat against and in contact with the tape portion 212, the tape portion 212 held flat against and in contact with a lower portion 190a of the surface 190, and a second portion of the conductive layer 172 held flat against and in contact with a raised portion 190b of the surface 190. The semiconductor wafer 100 and the film frame 210 are held flat against the lower portion 190a and the raised portion 190b of the surface 190 by press-fitting or vacuum assistance, thereby keeping the wafer stable and flat during probe testing.

A plurality of raised portions 190b of the surface 190 of the wafer probe chuck 194 are in electrical contact with corresponding regions of the conductive layer 172 through the openings 216. Computer controlled test system 220 sends electrical test signals through wafer probe chuck 194 and raised portions 190b of surface 190 extending through openings 216 to provide electrical stimulation to different areas of conductive layer 172. The semiconductor die 104 responds to the electrical stimulus, which is measured by the computer test system 220 and compared to an expected response to test the functionality of the semiconductor die.

In one implementation, as shown in fig. 3k, semiconductor wafer 100 is tested from active surface 110, see fig. 3h, where an electrical connection from ground reference node 221 to conductive layer 172 is made through opening 216 in stripe portion 212. Portions of conductive layer 172 may be electrically connected to an external ground reference node 221 through openings 216. A sample portion of the semiconductor wafer 100 may be tested from the active surface 110.

Alternatively, a wafer ring holder 222 with a clamp ring 224, as shown in fig. 3l, may be used to mount the semiconductor wafer 100. The wafer ring holder 222 is typically plastic or other lightweight material for low cost and ease of handling. The clip ring 224 fixes and holds a tape portion 225 for mounting the semiconductor wafer 100. Openings 226 may be formed in band portion 225, as described above. Other tape holders may be used to secure the tape portion 225 when mounting the semiconductor wafer 100.

Fig. 3m shows the semiconductor wafer 100 mounted on a tape portion 225 on a wafer ring holder 222 with the conductive layer 172 oriented toward the tape portion and the active surface 110 oriented away from the tape portion. Fig. 3n shows the semiconductor wafer 100 mounted on a strip portion 225 on a wafer ring holder 222 with the active surface 110 oriented toward the strip portion and the conductive layer 172 oriented away from the strip portion. By using TSVs, the orientation of the semiconductor wafer 100 is interchangeable. The semiconductor wafer 100 may have bumps 227 on the active surface 110, as shown in fig. 3o, or no bumps, as shown in fig. 3 k. The semiconductor wafer 100 may be tested using the active surface 110 and bumps 227 oriented toward the tape portion 225 or away from the tape portion. The semiconductor wafer 100 may be tested using the active surface 110 and without bumps oriented toward or away from the tape portion 225. A sample portion of the semiconductor wafer 100 may be tested with the active surface 110 of the semiconductor wafer 100 oriented toward the tape portion 225 or away from the tape portion.

In another implementation, the semiconductor wafer 100 is mounted to the tape portion 225 without the openings 226 to avoid stretching, non-uniformity, or other deformation in the tape portion or openings, see fig. 3 p. A tape portion 225 without an opening 226 may also be placed over the semiconductor wafer 100. A plurality of semiconductor wafers 100 may be mounted to a strip sheet or roll while maintaining uniform tension across the strip sheet. Once the semiconductor wafer 100 is mounted, the opening 226 is cut through the tape portion 225 using a laser, a blade, or by simply removing a pre-cut portion of the tape, similar to fig. 3 l. A clamp ring 224 having a band portion 225 of the semiconductor wafer 100 is attached to the wafer ring holder 222 either before or after the cut opening 226.

Fig. 3q shows conductive traces 228 formed on the surface of the strap portion 225 when mounted onto the wafer ring holder 222, where the conductive paths are precisely placed. The strap portion 225 may be laminated to the wafer ring holder 222 to obtain the incoming orientation and alignment of the conductive traces 228, which are then formed by lamination, printing, or shadow mask metal film deposition. In fig. 3r, the semiconductor wafer 100 is mounted to the tape portion 225 and aligned with conductive traces 228 formed on the tape portion 225 to make electrical contact and perform the necessary probe testing. In this case, the test probes 230 contact the conductive traces 228 from the top side outside of the wafer ring holder 222. Test probe signals are routed from test probes 230 along conductive traces 228 to conductive layer 172 in order to test the functionality and electrical parameters of semiconductor wafer 100. Fig. 3s shows the semiconductor wafer 100 with bumps 227 mounted to the tape portion 225 and aligned with conductive traces 228 formed on the tape portion 225 to make electrical contact and perform the necessary probe testing. In this case, the test probes 230 contact the conductive traces 228 from the top side outside of the wafer ring holder 222. Test probe signals are routed from the test probes 230 along the conductive traces 228 to the bumps 227 in order to test the functionality and electrical parameters of the semiconductor wafer 100.

In another implementation, similar to fig. 3i-3j, the film frame or wafer ring holder may have a plurality of openings and conductive traces or channels formed in the ribbon portion of the wafer ring holder to provide access to different areas of the conductive layer. Fig. 4a shows a top view of a wafer ring holder 240 comprising a band portion 242, a clamp ring 244, and a plurality of openings 246. Conductive traces 248 are formed on the surface of or through the tape portion 242. Alternatively, the strip portion 242 may be made of a channel of conductive carbon 240, as shown in fig. 4 b. Tape portion 242 has as many openings 246 and conductive traces 248 or vias 250 as necessary to perform probe testing on the necessary areas of conductive layer 172. In another implementation, any portion or the entire strip portion 242 may be conductive to perform testing on necessary areas of the conductive layer 172. The tape portion 242 and semiconductor wafer 100 are held securely in place by a press fit or vacuum assist, with the surface 134 and a first portion of the conductive layer 172 held flat against and in contact with the tape portion 242, the tape portion 242 held flat against and in contact with a lower portion 190a of the surface 190, and a second portion of the conductive layer 172 held flat against and in contact with a raised portion 190b of the surface 190. The semiconductor wafer 100 and wafer ring holder 240 are held flat by press-fitting or vacuum-assisted against the lower portion 190a and raised portion 190b of the surface 190, thereby keeping the wafer stable and flat during probe testing.

In fig. 4c, a plurality of raised portions 190b of surface 190 of wafer probe chuck 194 are in electrical contact with corresponding regions of conductive layer 172 through openings 246 and wire traces 248 or vias 250. Computer controlled test system 254 sends electrical test signals through wafer probe chuck 194 and raised portions 190b of surface 190 extending through openings 246 to provide electrical stimulation to different areas of conductive layer 172 through conductive traces 248 or vias 250. The semiconductor die 104 responds to the electrical stimulus, which is measured by the computer test system 254 and compared to an expected response to test the functionality of the semiconductor die.

The wafer ring holder and semiconductor wafer 100 are moved from the wafer probe chuck 194 and the thinned semiconductor wafer 100 is diced into individual semiconductor die 104 by saw streets 106 using a saw blade or laser cutting tool or plasma etching. Individual semiconductor die 104 from the thinned semiconductor wafer 100 have been probe tested in their final configuration.

Referring to fig. 5, a side view of an implementation of a semiconductor substrate is shown. As shown, the substrate 256 includes a first side 258 and a second side 260. In various implementations, by way of non-limiting example, the second side 260 includes a plurality of semiconductor dies formed therein/thereon. As shown, baseplate 265 also includes an edge 262. In this implementation, the edge 262 includes an edge ring. In various implementations, by way of non-limiting example, the substrate 256 may have a thickness of less than 39 microns or less than 10 microns. However, in other implementations, the wafer may be thicker than about 39 microns.

Referring to fig. 6, a side view of an implementation of a semiconductor substrate with an applied backgrinding tape is shown. As shown, the substrate 256 includes a first side 258 and a second side 260. As shown, a back-grind strip 264 is applied to the second side 260. In various implementations, by way of non-limiting example, the second side 260 may include a plurality of semiconductor dies. As shown, the substrate 256 also includes an edge 262 that includes an edge ring. In the implementation shown in fig. 6, the use of a backgrinding belt is shown in other substrate and method implementations disclosed herein, in which a backgrinding belt may not be used during backgrinding. Further, in various implementations, various polishing processes may be used to polish and/or thin the substrate. In particular, in substrate and method implementations in which the wafer has a thickness of less than about 25 microns, the use of a backgrinding tape may be omitted.

Referring to fig. 7, a side view of an implementation of the semiconductor substrate of fig. 6 after it has been background to a first thickness is shown. As shown, the substrate 256 includes a first side 258 and a second side 260. As shown, a back-grind strip 264 is applied to the second side 260. As shown, the first side 258 of the substrate 256 is background. In various implementations, by way of non-limiting example, the substrate 256 may be background to a first thickness 266 of 355 microns.

Referring to fig. 8, a side view of an implementation of a substrate 256 that is partially encapsulated by a substrate carrier implementation 270 after it is background to a second thickness is shown. As shown, the top ring 268 of the substrate carrier 270 encloses the edge 262 of the first side 258 of the substrate 256 and serves to maintain the edge 262 (including the edge ring) within the dimensions of the top ring 268. As shown, the bottom support 272 of the substrate carrier 270 also encapsulates the second side 260 of the substrate 256 and at least a portion of the edge 262. In various implementations, by way of non-limiting example, the substrate carrier 270 is not bonded to the substrate 256, but is held against the substrate using only mechanical force. In various implementations, the substrate carrier 270 may be reused with one or more semiconductor processing operations and/or two or more semiconductor substrates. In various implementations, by way of non-limiting example, the edge 262 of the substrate 256 includes an edge ring 274 of the substrate 256. As shown, the first side 258 of the substrate 256 is background. In various implementations, by way of non-limiting example, the substrate 256 may be backlit to a second thickness 276 of 50 microns or less. As shown, the top ring 268 of the substrate carrier 270 is coupled to the bottom support 272 of the substrate carrier 272. As shown, the top ring 268 may be coupled to the bottom support 272 by a locking mechanism 275. In various implementations, by way of non-limiting example, the locking mechanism 275 may be a hinge, a friction fit, a clamp, a snap, or any other form of locking or coupling mechanism capable of retaining the top ring 268 onto/over the bottom support 272.

Referring to fig. 9, a side view of the substrate implementation of fig. 8 is shown, which is partially encapsulated by the substrate carrier after being etched to a third thickness. In various implementations, by way of non-limiting example, the substrate 256 may be etched to a third thickness 278 of 25 microns or less. In various implementations, the etch process may be a stress relief etch and/or etch designed to reduce/eliminate backgrind damage on the substrate. As shown, the top ring 268 of the substrate carrier 270 is coupled to the bottom support 272 of the substrate carrier 270 above the edge 262 and the edge ring 274 of the substrate 256. As shown, the top ring 268 may be coupled to the bottom support 272 by a locking mechanism 275, which may be any of those disclosed in this document.

Referring to fig. 10, a side view of a substrate partially encapsulated by a substrate carrier having a locking mechanism after a lithographic pattern is applied is shown. The lithographic pattern may be used for various subsequent semiconductor processing operations such as, by way of non-limiting example, ion implantation, etching, deposition, die cutting, or any other operation requiring patterning. The implementation in fig. 10 illustrates how, in various semiconductor process implementations, the substrate carrier 270 is designed to support the substrate 256 through one or more subsequent semiconductor process operations after the carrier 270 has been mechanically coupled with the substrate.

Referring to fig. 11, a side view of a substrate partially encapsulated by a substrate carrier implementation is shown. As shown, the substrate 280 includes a first side 282 and a second side 284. In various implementations, by way of non-limiting example, second side 284 includes a plurality of semiconductor dies formed therein/thereon. As shown, the substrate 280 also includes an edge 286. As shown, the top ring 288 of the substrate carrier 290 encapsulates the edge 286 of the first side 282 of the substrate 280. As shown, the bottom support 292 of the substrate carrier 290 encapsulates the second side 284 and the edge 286 of the substrate 280. In various implementations, by way of non-limiting example, substrate carrier 290 is only mechanically coupled to substrate 280. As with other substrate carriers disclosed in this document, the carrier may be reusable. As shown, the bottom support 292 includes a cavity 294 therein. In various implementations, by way of non-limiting example, the cavity 294 is sized to receive a back grind strip 296 applied into the second side 284 of the substrate 280 into the cavity 294 so that the substrate 280 may lie flat against the bottom support 292. As shown, the top ring 288 of the substrate carrier 290 is coupled to the bottom support 292 of the substrate carrier 290. As shown, the top ring 288 may be coupled to the bottom support 292 by a locking mechanism 298, which may be any of those disclosed in this document.

Referring to fig. 12, a top view of the substrate of fig. 7 partially encapsulated by a substrate carrier is shown. As shown, the top ring 288 may include an alignment notch opening 300 in the ring to allow the substrate alignment notch to be used with various semiconductor processing tools, such as, by way of non-limiting example, notch aligners, optical character readers, and other devices that use notches during operation. For substrates having a flat surface, the top ring 288 may also include a corresponding flat surface entry section therein, or may follow the shape of the flat surface, such that the processing equipment may be adjusted to still recognize the location of the flat surface on the substrate. In various implementations, the bottom portion of the carrier may also be sized to correspond to the size of the plane of the substrate.

Referring to fig. 13, a side view of a substrate including an edge ring partially encapsulated by a substrate carrier implementation is shown. As shown, the substrate 302 includes a first side 304 and a second side 306. In various implementations, by way of non-limiting example, the second side 306 includes a plurality of semiconductor dies. As shown, the substrate 302 also includes an edge 308 having an edge ring. As shown, the top ring 310 of the substrate carrier 312 encapsulates the edge 308 of the first side 304 of the substrate 302. As shown, the bottom support 314 of the substrate carrier 312 encapsulates the second side 306 and the edge 308 of the substrate 302. As shown, the bottom support 314 includes a cavity 316 therein. In various implementations, by way of non-limiting example, the cavity 316 (similar to the cavity in fig. 11) is sized to accommodate the thickness of the backgrinding strip 318 applied to the second side 306 of the substrate 302. As shown, the top ring 310 of the substrate carrier 312 is coupled to the bottom support 314 of the substrate carrier 312. As shown, the top ring 310 may be coupled to the bottom support 314 by a locking mechanism 320, which may be any of those disclosed in this document.

Referring to fig. 14, a top view of the substrate of fig. 13 partially encapsulated by a substrate carrier is shown. As shown, the substrate 302 includes a first side 304. As shown, the substrate 302 also includes an edge 308 having an edge ring 322. As shown, the top ring 310 of the substrate carrier 312 encapsulates the edge 308 of the first side 304 of the substrate 302 and also extends inward toward the center of the substrate beyond at least a portion of the edge ring 274. As shown, the top ring 310 may include an alignment notch 324 similar to the implementation in fig. 12. For those substrates that include a flat surface, the top ring 310 and the bottom portion of the substrate carrier may also correspondingly include one or more flat surfaces that correspond to the flat surfaces in the substrate.

Referring to fig. 6-10, a substrate 256 is shown at various steps in a method of thinning the substrate to a desired thickness. As shown, in the method implementation, the back-grind strip 264 is first applied to the second side 260 of the substrate 256. The substrate 256 is then background to a first thickness 266. Next, the substrate 256 is disposed in the bottom support 272 of the substrate carrier 270. Next, the top ring 268 of the substrate carrier 270 is coupled over the edge 262 of the substrate 256. The substrate 256 is then background to a second thickness 276. The substrate 256 is then etched to a third thickness 278. In various implementations, by way of non-limiting example, the substrate 256 may be subsequently removed from the substrate carrier 270 and the substrate 256 may be cut. In various method implementations, the process of etching to the third thickness may be omitted after the substrate carrier 270 is coupled to the substrate.

In various implementations described herein, the substrate may be made of silicon, silicon dioxide, ruby, sapphire, single crystal silicon, polysilicon, glass, silicon on insulator, gallium arsenide, metals, metal alloys, or any other semiconductor substrate type, by way of non-limiting example. In various implementations, by way of non-limiting example, the substrate carrier may be made of a polymer, plastic, metal, or metal alloy, or any combination thereof, designed to withstand the various semiconductor processing steps (etching, photoresist processing, ion implantation, etc.) through which the carrier will pass. By way of non-limiting example, examples of polymeric materials that may be used in substrate carrier implementations such as those disclosed herein may include perfluoroalkoxyalkanes, perfluoroethers, polytetrafluoroethylene, fluorinated ethylene propylene, or any combination thereof. One of ordinary skill will be readily able to select a suitable material for the substrate carrier using the principles disclosed herein.

Referring to fig. 15, another implementation of a substrate carrier 326 is shown. The substrate carrier 326 may be formed of a hard material such as, by way of non-limiting example, a metal such as steel, a metal coated with another low resistance metal such as gold, or a plastic coated with a metal or any other carrier material disclosed herein. In various implementations, the carrier may be conductive or non-conductive. The substrate carrier 326 may be used with a semiconductor wafer 327 that does not have an edge ring as shown. As previously described, other implementations of the carrier may be used with a substrate including an edge ring, and may include corresponding structures for processing/coupling on/around the edge ring, such as those disclosed in this document. In various implementations, the substrate carrier may be reusable. The substrate carrier may include a top ring 328 that may be coupled to a bottom support 330 by a locking mechanism 332. In various implementations, by way of non-limiting example, the locking mechanism 332 may be a hinge, a friction fit, a clamp, a snap, or any other form of locking or coupling mechanism capable of retaining the top ring 328 on/over the bottom support 330.

As shown, the substrate carrier 326 includes one or more openings 334 in the bottom support of the carrier 326. By way of non-limiting example, the one or more openings may be circular, rectangular, square, oval, or any closed shape. The one or more openings may be used to test various dies in the substrate during or after wafer processing. The substrate may be tested by providing electrical connections to the semiconductor substrate through one or more openings 334 in the substrate carrier. In various implementations, this may be accomplished by extending one or more probes/pins from an electrical tester through one or more openings to contact the structure of the wafer. During electrical testing operations, any of the electrical tester implementations, probe types, pin types, and electrical test structures disclosed in this document may be employed. In various implementations, the electrical test may be a structural test, or may be a functional test, or a combination of both structural and functional tests. In various implementations, a local portion of a semiconductor wafer or substrate may be included in a substrate carrier and used for testing in the substrate carrier. In various implementations, a localized portion of a substrate may be processed for testing using any of the carriers shown in this document. The ability to process localized portions of a substrate/wafer may help reduce localized wafer waste, thereby reducing the cost of manufacturing semiconductor devices.

In various implementations in which the substrate carrier 334 is formed of an electrically conductive material, one or more openings in the bottom support 336 of the substrate carrier 334 may not be necessary for testing the substrate. Referring to fig. 16, an example of a substrate carrier 334 formed at least in part from an electrically conductive material is shown. The conductive portion 338 of the wafer 340 is disposed on the bottom support 336 of the carrier 334, which contacts the conductive portion of the carrier. The substrate may then be tested by contacting the test probes/pins to the surface of the bottom support to provide electrical connection to the substrate through the conductive material of the carrier. In some implementations, the entire bottom support 336 can be made of an electrically conductive material. However, in other implementations, only a portion of the bottom support 336 may be electrically conductive. In some implementations, none of the bottom supports 336 may be electrically conductive, and one or more traces/structures/vias formed from an electrically conductive material may be coupled with or through the structure of the bottom support 336 to allow the probes/pins to establish electrical connections with the substrate.

In various implementations, a vacuum may be applied to the bottom of the substrate carrier to increase the physical contact/retention force between the substrate and the bottom of the carrier. In some implementations, a reusable adhesive may be used on the inside of the bottom of the carrier as an aid to secure the substrate within the carrier during processing to prevent the substrate from moving in the carrier during testing and/or processing steps. The use of a reusable adhesive may be particularly useful when the carrier is used to treat one or more partial substrate portions. An example of a reusable binder that can be employed in various carrier implementations is manufactured by Delphon (Hayward, Calif.) under the trade name GEL-PAK.

In various substrate carrier implementations disclosed herein, the first side of the substrate may be the background.

In various substrate carrier implementations disclosed herein, the second side of the substrate can include a plurality of semiconductor dies therein.

In various substrate carrier implementations disclosed herein, the substrate carrier may not be bonded to the substrate.

In various substrate carrier implementations disclosed herein, the edge may be an edge ring of the substrate.

In various substrate carrier implementations disclosed herein, the substrate carrier may be formed of metal, plastic coated in metal, or metal coated in a secondary metal.

Where in the above description reference has been made to specific implementations of substrate carriers and to the implementation components, sub-components, methods and sub-methods, it should be apparent that various modifications can be made without departing from the spirit thereof, and that these implementations, implementation components, sub-components, methods and sub-methods can be applied to other substrate carriers.

Claims

1. A substrate carrier comprising:

a top ring configured to encapsulate an edge of a first side of a substrate; and

a bottom support configured to encapsulate an entire second side of the substrate and an edge of the second side.

2. The substrate carrier of claim 1, wherein the edge is an edge ring of the substrate.

3. The substrate carrier of claim 1, wherein the substrate has a thickness of less than 39 microns or less than 10 microns.

4. The substrate carrier of claim 1, wherein the top ring is configured to be coupled to the bottom support with one of a clamp, a friction fit, a snap, or a hinge.

5. A substrate carrier comprising:

a bottom support configured to encapsulate an entirety of the second side of the substrate and an edge of the second side, wherein the bottom support further comprises a cavity therein configured to receive a backgrinding tape applied to the second side of the substrate.

6. The substrate carrier of claim 5, wherein the substrate has a thickness of one of less than 39 microns or less than 10 microns.

7. The substrate carrier of claim 5, wherein the top ring is configured to be coupled to the bottom support with one of a clamp, a friction fit, a snap, or a hinge.

8. An apparatus for testing semiconductor substrates, comprising:

a substrate carrier comprising:

a bottom support configured to encapsulate an entirety of the second side of the substrate and an edge of the second side, wherein the bottom support is configured to allow electrical testing of a semiconductor substrate coupled with the substrate carrier using a probe.

9. The apparatus of claim 8, further comprising one or more openings in the bottom support configured to allow the probes to directly contact the substrate during electrical testing.

10. The apparatus of claim 8, wherein the substrate carrier is a substrate carrier formed of, or includes, an electrically conductive material coupled thereto.