CN111796142A - Wireless sensor device for current detection of opening and closing coil of circuit breaker - Google Patents
Wireless sensor device for current detection of opening and closing coil of circuit breaker Download PDFInfo
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Abstract
A wireless sensor device for detecting the current of a switching-on and switching-off coil of a circuit breaker comprises an FPGA (field programmable gate array) embedded with an ARM9 core, a memory, an RTC (real time clock), a USB (universal serial bus) interface, an Ethernet interface, an AD (analog-to-digital) converter, an IO (input/output) input interface, a wireless communication module and a power management module; the FPGA bidirectional communication memory embedded with the ARM9 core, the RTC real-time clock, the USB interface and the Ethernet interface; the current sensor is communicated with the AD converter; the AD converter is communicated with the FPGA embedded with the ARM9 core; the IO input interface is communicated with the FPGA embedded with the ARM9 core; the FPGA embedded with the ARM9 core is interconnected with the wireless communication module; the wireless communication module is communicated with the monitoring platform; the power management module supplies power to the FPGA embedded with the ARM9 core, the memory, the RTC real-time clock, the USB interface, the Ethernet interface, the AD converter, the IO input interface and the wireless communication module; the wireless sensor device realizes the acquisition, storage and analysis of the current of the opening and closing coil of the circuit breaker and the wireless transmission of real-time data.
Description
Technical Field
The invention belongs to the technical field of wireless sensors, and particularly relates to a wireless sensor device for detecting current of a switching-on and switching-off coil of a circuit breaker.
Background
The current waveform of the opening and closing coil of the circuit breaker is an important monitoring parameter for intellectualization of the high-voltage switch, a monitoring device is generally arranged in a secondary chamber of the high-voltage switch cabinet, monitoring data are stored locally, data are exported through a USB memory, and then the data are imported into a monitoring platform for analysis; the high-voltage switch cabinets of the transformer substation are large in number, monitoring data are required to be exported from switch to switch by staff at regular intervals, and time and labor are wasted; data cannot be uploaded to the monitoring platform in real time, and the running state of the high-voltage switch cannot be reflected in time.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a wireless sensor device for detecting the current of a switching-on and switching-off coil of a circuit breaker, which is used for realizing the acquisition, storage and analysis of the current of the switching-on and switching-off coil of the circuit breaker and the wireless transmission of real-time data.
In order to achieve the purpose, the invention adopts the technical scheme that:
a wireless sensor device for detecting the current of a switching-on and switching-off coil of a circuit breaker comprises an FPGA (field programmable gate array) embedded with an ARM9 core, a memory, an RTC (real time clock), a USB (universal serial bus) interface, an Ethernet interface, an AD (analog-to-digital) converter, an IO (input/output) input interface, a wireless communication module and a power management module; the FPGA embedded with the ARM9 core is characterized by comprising an FPGA two-way communication memory, an RTC real-time clock, a USB interface and an Ethernet interface; the current sensor is communicated with the AD converter; the AD converter is communicated with the FPGA embedded with the ARM9 core; the IO input interface is communicated with the FPGA embedded with the ARM9 core; the FPGA embedded with the ARM9 core is interconnected with the wireless communication module; the wireless communication module is communicated with the monitoring platform; the power management module supplies power to the FPGA embedded with the ARM9 core, the memory, the RTC real-time clock, the USB interface, the Ethernet interface, the AD converter, the IO input interface and the wireless communication module;
the current sensor converts the current of the opening and closing coil of the circuit breaker and the current of the energy storage motor into analog voltage signals and outputs the analog voltage signals to the AD converter;
the AD converter synchronously converts the input multi-channel analog current/voltage signals into digital signals and outputs the digital signals to an FPGA port embedded with an ARM9 core;
the IO input interface acquires the opening and closing state of the auxiliary switch of the circuit breaker and outputs the opening and closing state to an FPGA port embedded with an ARM9 core;
the FPGA embedded with the ARM9 core periodically acquires input data, writes the acquired switching-on/off current data into a memory in a file form during the action of the circuit breaker, and outputs the data to the wireless communication module through a serial port;
the wireless communication module encrypts the received data and sends the encrypted data to the monitoring platform in real time; the wireless communication protocol can be a Modbus RTU or a proprietary protocol;
the RTC provides a real-time clock for the wireless sensor device as time data stored in the monitoring data file; receiving the timing of the monitoring platform through the wireless communication module;
the wireless sensor device is provided with a large-capacity memory which comprises a Flash memory, an SD card and a DDR memory and can store at least 10000 groups of monitoring data;
monitoring data files stored in the wireless sensor device can also be exported to a USB memory through a USB interface, and import and data analysis are carried out on a monitoring platform;
the wireless sensor device can also send the monitoring data file to the monitoring platform in a wired connection mode of the Ethernet interface;
the power management module realizes the conversion of a direct current 24V power supply to +/-12V, 5V, 3.3V, 1.8V, 1.5V, 1.0V and 0.75V direct current low voltage and provides a working power supply for each functional module in the wireless sensor device;
the current sensor can be an open-close type or a through type Hall current sensor;
the wireless sensor device can communicate in a LoRa, NBiot and other wireless interfaces;
the wireless sensor device can also acquire the secondary current of the main loop CT and the current of the energy storage motor of the circuit breaker and wirelessly transmit data.
The FPGA circuit with the embedded ARM9 core is composed of a resistor R87, a resistor R88, a resistor R89, a resistor R90, a resistor R91, a resistor R92, a capacitor C78, a capacitor C79, a capacitor C80, a magnetic bead FB5, a self-reset switch SW1, a crystal oscillator Y3, a resistor R68, a resistor R69, a resistor R70, a resistor R71, a resistor R72, a resistor R73, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a resistor R79, a resistor R80, a resistor R81, a light emitting diode D6, a magnetic bead FB4, a chip U16, a socket J3, a socket J4, a socket P3, a resistor R82, a resistor R83, a resistor R84, a resistor R85 and an FPGA chip U15; the chip comprises a resistor R87 and a resistor R88 of 4.7K, a resistor R89 and a resistor R90 of 1K, a resistor R91 of 24R, a resistor R92 of 33R, a capacitor C78 of 10uF, a capacitor C79 and a capacitor C80 of 0.1uF, a magnetic bead FB5 of BLM18PG331SN1, a crystal oscillator Y3 of 33.333MHz, a resistor R68 of 330R, a resistor R69, a resistor R70 and a resistor R71 of 4.7K, a resistor R72 of 0R, a resistor R73 of 27R, a resistor R74 of 100R, a resistor R75, a resistor R76, a resistor R77, a resistor R78 of 20K, a magnetic bead REF 18PG331SN 72, a chip U78 of 363012, a J socket 72, a socket J socket of 363, a pin R78 of 20K, a double-row resistor R78, a pin of 367R 78, a double-row resistor R78 and a pin of 367R 78 of 3, a double-pin of 3, a double-pin of 3-7R 36010.
The circuit of the Flash memory and the SD card in the memory consists of a resistor R17, a resistor R18, a resistor R19, a TF card slot P2 and a NAND Flash memory chip U5; the resistor R17 is 4.7K, the resistors R18 and R19 are 499R, and the NAND flash memory chip U5 is MT29F2G 08.
The DDR memory circuit in the memory consists of a resistor R1, a resistor R2, a DDR memory chip U1 and a chip U2; the resistor R1 and the resistor R2 are 240R, and the DDR memory chip U1 and the chip U2 are K4B4G 1646B.
The Ethernet interface circuit consists of a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a crystal Y2, a magnetic bead FB1, a built-in interface transformer, an LED indicator RJ45 socket U8 and an Ethernet interface chip U7; the resistor R22 and the resistor R23 are 470R, the resistor R24 is 4.99K, the resistor R25 and the resistor R26 are 49.9R, the resistor R27 is 4.7K, the capacitor C8 is 0.1uF, the capacitor C9 and the capacitor C10 are 27pF, the capacitor C11 is 0.1uF, the crystal Y2 is 25MHz, the magnetic bead FB1 is BLM18PG331SN1, the socket U8 is HY911130A, and the Ethernet interface chip U7 is 88E 1512.
The USB interface circuit consists of a resistor R20, a resistor R21, a diode D1, a capacitor C5, a capacitor C6, a capacitor C7, a crystal oscillator Y1, a socket USB1 and a USB interface chip U6; the resistor R20 is 2K, the resistor R21 is 0R, the diode D1 is LL4148, the capacitor C5 is 2.2uF, the capacitor C6 is 0.1uF, the capacitor C7 is 2.2uF, the crystal oscillator Y1 is 26MHz, and the USB interface chip U6 is PTUSB 1210.
The AD converter circuit consists of a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a socket J1 and an AD converter chip U3; the high-voltage power supply comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9 and a resistor R10 which are 100R, a capacitor C1 which is 10uF, a capacitor C2, a capacitor C3 and a capacitor C4 which are 1uF, a socket J1 which is ECH762V-15, and an AD converter chip U3 which is AD 7606.
The IO input interface circuit consists of a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a capacitor C76, a socket J2 and an optocoupler OP 1; the resistor R11 is 10K, the resistors R12 and R13 are 1K, the resistor R14 is 470K, the resistor R15 is 10K, the resistor R16 is 470K, the socket J2 is ECH762V-15, and the optical coupler OP1 is HCPL 0731.
The LoRa wireless communication circuit in the wireless communication module consists of an SMA radio frequency antenna socket P1 and a LoRa chip U4; wherein, the SMA radio frequency antenna socket P1 is SMA-KWE, and the LoRa chip U4 is E22-400T 22S.
The RTC real-time clock circuit consists of a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C76, a battery BT1 and an RTC real-time clock chip U14; the resistor R64, the resistor R65, the resistor R66 and the resistor R67 are 10K, the capacitor C76 is 0.1uF, the battery BT1 is CR1220, and the RTC real-time clock chip U14 is DS 3231.
The power management module circuit comprises a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R34, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R41, a capacitor CD1, a capacitor CD2, a capacitor CD3, a capacitor CT1, a capacitor CT2, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36, a capacitor C37, a capacitor C38, a capacitor C39, a capacitor C40, an inductor L1, an inductor L2, an inductor L4, a magnetic bead FB3, a diode D2, a diode D3, a switching power supply U9, a switching power supply chip U9, a resistor R36363672, a resistor R9, a resistor R36363672, a capacitor C9, a capacitor C363636363672, a capacitor C, a capacitor C, an inductor L, a diode D, a switching power chip U, a resistor R, a capacitor CD, a capacitor CT, a capacitor C, an inductor L, a power tube Q, and a switching power chip U; wherein, the resistor R28 and the resistor R29 are 0R, the resistor R30 and the resistor R31 are 10.2K, the resistor R32 and the resistor R34 are 10R, the resistor R36 is 0R, the resistor R37 is 8.06K, the resistor R38 is 40.2K, the resistor R39 and the resistor R41 are 0R, the capacitor CD1 is 120uF, the capacitor CD2 and the capacitor CD3 are 270uF, the capacitor CT3 and the capacitor CT3 are 10uF, the capacitor C3 is 0.1uF, the capacitor C3 and the capacitor C3 are 0.047uF, the capacitor C3 and the capacitor C3 are 470pF, the capacitor C3 is 0.1uF, the capacitor C3 is 150pF, the capacitor C3 is 150 uF, the capacitor C3 is 0.72, the inductor C3 is 3 ul, the inductor h is 3 h, the inductor 20 ul, the inductor h is 3 h, the inductor 20 ul, the inductor h is the inductor h 72 h is 3 h14 ul, the inductor h is 3 h, the inductor ul 3 h is 3 h, the inductor ul 72 h is 3 h, the inductor ul 3 h is 3 h, the inductor ul 72 h is 3, the switching power supply chip U11 is LT1763, the resistors R42 and R44 are 0R, the resistor R46 is 10R, the resistor R47 is 10K, the resistor R48 is 20K, the resistor R50 is 10R, the resistor R52 is 0R, the resistor R53 is 1.4K, the resistor R54 is 6.34K, the capacitor CD4 is 120uF, the capacitor CD5 and the capacitor CD6 are 270uF, the capacitor CT3 and the capacitor CT5 are 10uF, the capacitor CT8 is 100uF, the capacitor C8 is 0.1uF, the capacitor C8 is 0.047uF, the capacitor C8 is 470pF, the capacitor C8 is 100pF, the capacitor C8 is 0.1uF, the capacitor C8 is 0.72, the capacitor C8 is 8, the inductor ul 72 is 8, the inductor ul 72 is 0 ul, the inductor ul 72 is the inductor ul 72, the inductor ul 8 ul 72 is the inductor ul 72, the inductor ul 72 ul 8 ul 72 ul, the inductor ul 72 ul 8 is the inductor ul 72 ul, the power supply comprises a switching power supply chip U, a resistor R and a resistor R of 5.1R, a resistor R and a resistor R of 0R, a resistor R of 82R, a resistor R and a resistor R of 75K, a resistor R of 3R, a resistor R of 4.99K, a resistor R of 0.01R, a capacitor CD of 120uF, a capacitor CD of 270uF, a capacitor CT of 10uF, a capacitor CT of 47uF, a capacitor C of 22uF, a capacitor C of 0.1uF, a capacitor C and a capacitor C of 4.7uF, a capacitor C of 1uF, a capacitor C of 4.7uF, a capacitor C of 10uF, a capacitor C of 0.1uF, a capacitor C of 10uF, a capacitor C of 0.1uF, a capacitor C of 0.033uF, a capacitor C of 10uF, a capacitor C of 1000pF, a capacitor C of 4700, an inductor C of 782.782 uF, a power supply chip U, a power supply tube of TPS and TPS of 116Q.
The invention has the beneficial effects that:
under the operating state of the high-voltage switch, the current signals of the opening and closing coils of the circuit breaker are collected and analyzed in an online mode, the characteristic information such as the action time, the coil current magnitude, the action speed and the like of each stage of the opening and closing of the switch can be quickly and accurately analyzed from the current of the opening and closing coils, the real-time monitoring of the operating state of the high-voltage switch and the early effective early warning of faults are realized, the requirements of quick, safe, convenient and effective detection of the high-voltage switch are met, the defects of the existing monitoring device of the high-voltage switch are overcome, and the safe and stable operation of the high-. The device adopts a wireless communication mode, is convenient to install, does not need to lead wires out of the high-voltage switch cabinet, and reduces the installation risk of wired connection; the wireless data encryption improves the data security and effectively prevents falsification.
Drawings
FIG. 1 is a schematic diagram of the overall composition of the present invention;
FIG. 2 is a working schematic diagram of the invention applied to current monitoring of the opening and closing coils of the circuit breaker;
FIG. 3 is a general schematic of the circuit of the present invention;
FIG. 4 is a circuit diagram of an FPGA with an ARM9 embedded core according to the present invention, which includes FIG. 4a, FIG. 4b, FIG. 4c, and FIG. 4 d;
FIG. 5 is a circuit diagram of a portion of a Flash memory & SD card in the memory of the present invention;
FIG. 6 is a circuit diagram of a DDR memory part in the memory of the invention;
FIG. 7 is a circuit diagram of an Ethernet interface of the present invention;
FIG. 8 is a circuit diagram of a USB interface according to the present invention;
FIG. 9 is a circuit diagram of an AD converter of the present invention;
FIG. 10 is a circuit diagram of an IO input interface of the present invention;
fig. 11 is a circuit diagram of a LoRa wireless communication module according to the present invention;
FIG. 12 is a circuit diagram of an RTC real time clock of the present invention;
FIG. 13 is a circuit diagram of a power management module of the present invention, which includes FIG. 13a, FIG. 13b, and FIG. 13 c.
Detailed Description
The invention is further described with reference to the accompanying drawings and examples.
As shown in fig. 1, a wireless sensor device for detecting current of a switching-on/off coil of a circuit breaker includes an FPGA with an embedded ARM9 core, a memory, an RTC real-time clock, a USB interface, an ethernet interface, an AD converter, an IO input interface, a wireless communication module, and a power management module; the FPGA bidirectional communication memory embedded with the ARM9 core, the RTC real-time clock, the USB interface and the Ethernet interface; the current sensor is communicated with the AD converter; the AD converter is communicated with the FPGA embedded with the ARM9 core; the IO input interface is communicated with the FPGA embedded with the ARM9 core; the FPGA embedded with the ARM9 core is interconnected with the wireless communication module; the wireless communication module is communicated with the monitoring platform; the power management module supplies power to the FPGA embedded with the ARM9 core, the memory, the RTC real-time clock, the USB interface, the Ethernet interface, the AD converter, the IO input interface and the wireless communication module;
the current sensor converts the current of the opening and closing coil of the circuit breaker and the current of the energy storage motor into analog voltage signals and outputs the analog voltage signals to the AD converter;
the AD converter synchronously converts the input multi-channel analog current/voltage signals into digital signals and outputs the digital signals to an FPGA port embedded with an ARM9 core;
the IO input interface acquires the opening and closing state of the auxiliary switch of the circuit breaker and outputs the opening and closing state to an FPGA port embedded with an ARM9 core;
the FPGA embedded with the ARM9 core periodically acquires input data, writes the acquired switching-on/off current data into a memory in a file form during the action of the circuit breaker, and outputs the data to the wireless communication module through a serial port;
the wireless communication module encrypts the received data and sends the encrypted data to the monitoring platform in real time; the wireless communication protocol can be a Modbus RTU or a proprietary protocol;
the RTC provides a real-time clock for the wireless sensor device as time data stored in the monitoring data file; receiving the timing of the monitoring platform through the wireless communication module;
the wireless sensor device is provided with a large-capacity memory which comprises a Flash memory, an SD card and a DDR memory and can store at least 10000 groups of monitoring data;
monitoring data files stored in the wireless sensor device can also be exported to a USB memory through a USB interface, and import and data analysis are carried out on a monitoring platform;
the wireless sensor device can also send the monitoring data file to the monitoring platform in a wired connection mode of the Ethernet interface;
the power management module realizes the conversion of a direct current 24V power supply to +/-12V, 5V, 3.3V, 1.8V, 1.5V, 1.0V and 0.75V direct current low voltage and provides a working power supply for each functional module in the wireless sensor device;
the current sensor can be an open-close type or a through type Hall current sensor;
the wireless sensor device can communicate in a LoRa, NBiot and other wireless interfaces;
the wireless sensor device can also acquire the secondary current of the main loop CT and the current of the energy storage motor of the circuit breaker and wirelessly transmit data.
The general schematic diagram of the wireless sensor device circuit is shown in fig. 3, and the wireless sensor device circuit is composed of a module1, a module2, a module3, a module4, a module5, a module6, a module7, a module8, a module9 and a module 10; the module1 is an FPGA circuit diagram with an ARM9 core embedded, and comprises FIG. 4a, FIG. 4b, FIG. 4c and FIG. 4 d; the module2 is a circuit diagram of Flash memory & SD card in memory, including FIG. 5; module3 is a DDR in memory circuit diagram, including FIG. 6; module4 is an Ethernet interface circuit diagram, including FIG. 7; module5 is a USB interface circuit diagram, including FIG. 8; module6 is an AD converter circuit diagram, including fig. 9; module7 is an IO input interface circuit diagram, including FIG. 10; module8 is a LoRa wireless communication circuit diagram of a wireless communication module, including FIG. 11; module9 is a RTC real time clock circuit diagram, including FIG. 12; the module10 is a power management module circuit diagram, including FIG. 13a, FIG. 13b and FIG. 13 c. Module1 and module2 adopt NAND Flash interface and SDIO interface connection, module1 and module3 adopt DDR3 interface connection, module1 and module4 adopt MII interface connection, module1 and module5 adopt ULPI interface connection, module1 and module6 adopt SPI interface and IO interface connection, module1 and module7 adopt IO interface connection, module1 and module8 adopt asynchronous serial interface and IO interface connection, module1 and module9 adopt IIC interface and IO interface connection.
The FPGA circuit diagram embedded with the ARM9 core comprises the parts shown in FIGS. 4a, 4b, 4c and 4d, and the FPGA chip U15 consists of 9 parts including U15A, U15B, U15C, U15D, U15E, U15F, U15G, U15H and U15I;
as shown in fig. 4a, the FPGA circuit diagram a part embedded with the ARM9 core is composed of FPGA chip U15A, U15B and U15C; pin C of chip U15 is connected with AD _ CONVST, pin B of chip U15 is connected with AD _ RESET, pin B of chip U15 is connected with AD _ SCLK, pin A of chip U15 is connected with AD _ CS, pin E of chip U15 is connected with AD _ BUSY, pin D of chip U15 is connected with AD _ DOUTA, pin D of chip U15 is connected with AD _ DOUTB, pin T of chip U15 is connected with INPUT, pin U of chip U15 is connected with _ SDA, pin V of chip U15 is connected with RTC _ SCL, pin V of chip U15 is connected with E _ TXD, pin W of chip U15 is connected with E _ RXD, pin T of chip U15 is connected with E _ M, pin N of chip U15 is connected with PHY _ RESETN, pin P of chip U15 is connected with PHY _ CONFIG, pin T of chip U15 is connected with PHY _ RESET, pin T of chip U15 is connected with PHY _ RESET, pin D, DVR 15, pin C of chip U, Pin V14, pin W17, and pin Y20 are connected to DVDD3V3, and pin T8, pin U11, pin W7, and pin Y10 of the chip U15C are connected to DVDD3V 3.
As shown in fig. 4b, the FPGA circuit b with embedded ARM9 core is composed of a resistor R87, a resistor R88, a resistor R89, a resistor R90, a resistor R91, a resistor R92, a capacitor C78, a capacitor C79, a capacitor C80, a magnetic bead FB5, a self-reset switch SW1, a crystal oscillator Y3, an FPGA chip U15D and a FPGA chip U15H; the pin 3 of the crystal oscillator Y is connected with a pin E of a chip U15 after being connected with a resistor R in series, the pin 3 of the crystal oscillator Y provides a clock for the FPGA chip U, the pin 4 of the crystal oscillator Y is connected with a capacitor C and a magnetic bead FB in parallel, one end of the capacitor C is grounded, the magnetic bead FB is connected with the capacitor C and the capacitor C in parallel, the capacitor C and the capacitor C are grounded in parallel, the pin 2 of the crystal oscillator Y is grounded, the pin A of the chip U15 is connected with a PHY _ TX _ CLK, the pin E of the chip U15 is connected with a PHY _ TXD, the pin B of the chip U15 is connected with a PHY _ TXD, the pin A of the chip U15 is connected with a PHY _ TXD, the pin F of the chip U15 is connected with a PHY _ TX _ CTL, the pin B of the chip U15 is connected with a RX _ CLK, the pin D of the chip U15 is connected with a PHY _ RXDD, the pin A of the chip U15 is connected with a PHY _ RXDD, chip U15 pin C is connected with OTG _ DIR, chip U15 pin C is connected with OTG _ STP, chip U15 pin E is connected with OTG _ NXT, chip U15 pin A is connected with OTG _ DATA, chip U15 pin D is connected with OTG _ DATA, chip U15 pin A is connected with OTG _ DATA, chip U15 pin F is connected with OTG _ DATA, chip U15 pin A is connected with OTG _ CLK, chip U15 pin A is connected with OTG _ DATA, chip U15 pin E is connected with OTG _ DATA, chip U15 pin C is connected with OTG _ DATA, chip U15 pin D is connected with SD _ CLK after being connected with resistor R in series, chip U15 pin C is connected with SD _ CMD, chip U15 pin E is connected with SD _ DATA, chip U15 pin A is connected with SD _ DATA, chip U15 pin F is connected with SD _ DATA, chip U15 pin B is connected with SD _ DATA, chip U15 pin D is connected with SD _ wp, chip U15 pin D is connected with CD, chip U15 pin C is connected with PHY _ IO _ PHY is connected with MDU 15 pin C, a chip U15 pin B is connected with a resistor R in series and then connected with DVDD3V, a chip U15 pin E is connected with a resistor R and a resistor R in parallel, the resistor R is connected with the DVDD3V, the resistor R is grounded, the chip U15 pin B, a pin D, a pin E and a pin A are connected with the DVDD3V, the chip U15 pin B and the pin D are connected with the DVDD3V, the chip U15 pin C is connected with the resistor R and the self-reset switch SW in parallel, one end of the resistor R is connected with the DVDD3V, one end of the self-reset switch SW is grounded, the chip U15 pin C is connected with the NAND _ Flash _ busy, the chip U15 pin E is connected with the NAND _ Flash _ data, the chip U15 pin D is connected with the NAND _ Flash _ data, the chip U15 pin C is connected with the NAND _ Flash _ data, the chip U15 pin E is connected with the NAND _ Flash _ data, the chip U15 pin B is connected with the NAND _ Flash _ data, the chip U15 pin D is connected with the NAND _ Flash _ data, the NAND _ Flash _ re is connected with the, pin B7 of the chip U15H is connected to NAND _ Flash _ data2, pin D6 of the chip U15H is connected to NAND _ Flash _ we _ B, pin D8 of the chip U15H is connected to NAND _ Flash _ ale, and pin E6 of the chip U15H is connected to NAND _ Flash _ cs.
As shown in fig. 4c, the FPGA circuit diagram c with the ARM9 embedded therein is composed of a resistor R68, a resistor R69, a resistor R70, a resistor R71, a resistor R72, a resistor R73, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a resistor R79, a resistor R80, a resistor R81, a light emitting diode D6, a magnetic bead FB4, a chip U16, a socket J3, a socket J4, a socket P3, and a FPGA chip U15E; a chip U15 pin R is connected with a resistor R and a light emitting diode D in parallel, one end of the resistor R is connected with a DVDD3V, one end of the light emitting diode D is connected with a resistor R, one end of the resistor R is grounded, a chip U15 pin R is connected with a resistor R in series and then connected with a DVDD3V, a chip U15 pin L is connected with a resistor R in series and then connected with a DVDD3V, a chip U15 pin J is connected with a socket P pin 4, a chip U15 pin F is connected with a socket P pin 6, a chip U15 pin G is connected with a socket P pin 10, a chip U15 pin F is connected with a socket P pin 8, a chip U15 pin L is connected with a chip U pin 2 to obtain an FPGA (field programmable gate array) built-in ADC reference voltage, a chip U15 pin M is connected with a resistor R in series and then connected with a DVDD3V, a chip U15 pin T, a pin R, a pin N, a pin K is connected with a DVDD3V, a chip U15 pin F is grounded, a chip U15 pin K, a pin K is connected with an AGND, pin 14 of socket P3 is connected in series with resistor R74 and then connected with PS _ SRST _ B, pin 2 of socket P3 is connected with DVDD3V3, pin 1 of socket P3, pin 3, pin 5, pin 7, pin 9, pin 11, and pin 13 are grounded, pin 1 of chip U16 is connected with AVDD1V8, pin 3 of chip U16 is connected with AGND1, pin 2 of socket J3 is connected in series with resistor R75 and then connected with NAND _ Flash _ data2, pin 2 of socket J4 is connected in series with resistor R79 and then connected with NAND _ Flash _ data0, pin 1 of socket J3 is connected with dd dvd 3V3, pin 3 of socket J3 is grounded, pin 1 of socket J3 is connected with DVDD3V3, pin 3 of socket J3 is grounded, pin NAND _ Flash _ we _ B is connected in series with resistor R3 and then grounded, and then connected with NAND _ Flash _ R3 and then connected with NAND 3 and then grounded.
As shown in fig. 4d, the FPGA circuit diagram d with the embedded ARM9 core is composed of a resistor R82, a resistor R83, a resistor R84, a resistor R85, and FPGA chips U15F, U15G, and U15I; a pin B4 of a chip U15I, a parallel resistor R85 is connected with a DDR3_ RST _ N, one end of a resistor R85 is grounded, a pin C3 of a chip U15I is connected with a DDR3_ DQ0, a pin B3 of the chip U15I is connected with a DDR3_ DQ3, a pin A3 of the chip U15 3 is connected with a DDR3, a pin A3 of the chip U3 is connected with a DDR3_ DQ3, a pin D3 of the chip U3 is connected with a DQ 3_ DQ3, a pin D3 is connected with a DQ3, a chip 3 is connected with a DQ3, a chip 3, a pin D3 of the DDR3, a DQ3, a chip 3 is connected with a DQ3, a chip 3 is connected with a DQ3, a chip 3, a DQ3 is connected with a DQ3, a chip 3 is connected with a DQ3, a chip 3, a pin J1 of a chip U15I is connected to a DDR3_ DQ15, a pin F4 of a chip U15I is connected to a DDR3_ a14, a pin D4 of a chip U15I is connected to a DDR3_ a13, a pin E4 of the chip U15I is connected to a DDR3_ a12, a pin G15I of the chip U15I is connected to a DDR I _ a I, a pin F I of the chip U15I is connected to a DDR I _ a I, a pin J I of the chip U15I is connected to a DDR I _ a I, a pin K I of the chip U15 is connected to a DDR I, a pin M I is connected to a I a pin K I of the DDR I, a pin L I of the chip U15I is connected to a DDR I a I, a pin L I of the DDR I is connected to a DDR I, a I H I, a I is connected to a I, a I is connected in series with a chip U72, a I, a, pin R4 of chip U15I is connected with DDR3_ BA1, pin L5 of chip U15I is connected with DDR3_ BA0, pin N5 of chip U15I is connected with DDR3_ ODT, pin N1 of chip U15I is connected with DDR3_ CS _ N, pin N3 of chip U15 3 is connected with DDR3_ CKE, pin M3 of chip U15 3 is connected with DDR3_ WE _ N, pin P3 of chip U15 3 is connected with DDR3_ CAS _ N, pin P3 of chip U15 3 is connected with DDR3_ DQ3, pin P3 of chip U3 is connected with DDR3_ DQ3, pin P3 is connected with DQ 3_ DQ3, pin DQ3 is connected with DQ U3 _ DQ 3_ DQ, pin DQ3 is connected with DQ _ 3_ DQ _ 3, pin DQ _ 3 is connected with DQ _ 3, chip U3 _ DQ _ 3, chip 3_ DQ _ 3, chip 3 is connected with DDR3_ DQ _ 3, chip 3_ DQ _ 3, chip 3 is connected with DQ _ 3, chip 3_ DQ _ 3, chip 3_ DQ _, pin Y of chip U15 is connected with DDR _ DQ, pin Y of chip U15 is connected with DDR _ DM, pin W of chip U15 is connected with DDR _ DQS _ P, pin W of chip U15 is connected with DDR _ DQS _ N, pin Y of chip U15 is connected with DDR _ DQ, pin W of chip U15 is connected with DDR _ DQ, pin V of chip U15 is connected with DDR _ DQ, pin A of chip U15, pin A, pin B, pin C, pin K, pin D, pin E, pin F, pin G, pin H, pin J, pin K, pin C, pin K, pin L, pin M, pin N, pin P, Pin P, pin R, pin T, pin U, pin V, pin W, pin Y, and pin Y are grounded, pin G, pin H, pin J, pin K, pin L, pin M, pin N, pin P, pin R, pin J, pin L, pin N, pin P, pin R, pin G, pin H, and pin G of chip U15 are connected to DVDD1V, pin G, pin F, pin H, pin K, pin M, pin J, pin L, pin N, pin P, pin R, pin N, and pin G are connected to DVDD 1V.
As shown in fig. 5, the Flash memory & SD card circuit in the memory is composed of a resistor R17, a resistor R18, a resistor R19, a TF card slot P2 and a NAND Flash memory chip U5; pin 1 of TF card slot P2 is connected with SD _ data2, pin 2 of TF card slot P2 is connected with SD _ data3, pin 3 of TF card slot P2 is connected with SD _ cmd after being connected with resistor R17 in parallel, one end of resistor R17 is connected with DVDD3V 17, pin 4 of TF card slot P17 is connected with DVDD3V 17, pin 5 of TF card slot P17 is connected with SD _ clk, pin 6 of TF card slot P17 is grounded, pin 7 of TF card slot P17 is connected with SD _ data 17, pin 8 of TF card slot P17 is connected with SD _ data 17, pin CD of TF card slot P17 is connected with SD _ CD after being connected with resistor R17 in series, pin 9, pin 10, pin 11, pin 12 is grounded, SD _ wp is connected with resistor R17, one end of resistor R17 is grounded, pin 17 of chip U17 is connected with NAND Flash _ 17, pin 16 of chip U17 is connected with NAND _ cs _ cle, pin 8 of NAND chip 17 is connected with NAND chip U17, pin 8 b is connected with Flash _ data of Flash _ 17, pin 72 is connected with Flash _ 17, and chip U17 is connected with NAND chip 17, and NAND chip 17 is connected with NAND chip, the pin 31 of the chip U5 is connected with NAND _ Flash _ data2, the pin 32 of the chip U5 is connected with NAND _ Flash _ data3, the pin 41 of the chip U5 is connected with NAND _ Flash _ data4, the pin 42 of the chip U5 is connected with NAND _ Flash _ data5, the pin 43 of the chip U5 is connected with NAND _ Flash _ data6, the pin 44 of the chip U5 is connected with NAND _ Flash _ data7, the pin 7 of the chip U5 is connected with NAND _ Flash _ busy, the pin 12, the pin 37, the pin 34, the pin 39 and the pin 19 of the chip U5 are connected with DVDD3V3, and the pin 13, the pin 36, the pin 25 and the pin 48 of the chip U5 are grounded.
As shown in fig. 6, the DDR memory circuit in the memory consists of a resistor R1, a resistor R2, a DDR memory chip U1 and a chip U2; chip U1 pin T7 is connected with DDR3_ A14, chip U1 pin T3 is connected with DDR3_ A13, chip U1 pin N7 is connected with DDR3_ A12, chip U1 pin R1 is connected with DDR 1_ A1, chip U1 pin L1 is connected with DDR 1_ A1, chip U1 pin R1 is connected with DDR 1_ A1, chip U1 pin T1 is connected with DDR 1 pin DDR 1, chip U1 pin T1 is connected with DDR 1_ A1, chip U1 pin R1 is connected with DDR 1_ A1, chip U1 pin P1 is connected with DDR 1 pin K1, chip U1 is connected with DDR 1_ A1, chip U1 pin DDR 1P 1 is connected with DDR 1 pin DDR 1, chip U1K 1 and DDR 1 pin DDR 1, chip K1 is connected with DDR 1, chip K1 pin DDR 1, chip K1 is connected with DDR 1K 1, chip K1 and chip K1, chip K1 is connected with DDR 1, chip K1, chip K1 and K1, chip K1 and K1, DDR 1K 1, chip K1 and K1, DDR 1K 1, DDR 1K 1, pin J3 of chip U1 is connected with DDR3_ RAS _ N, pin L3 of chip U1 is connected with DDR3_ WE _ N, pin A3 of chip U1 is connected with DDR3_ DQ15, pin B15 of chip U15 is connected with DDR 15 _ DQ15, pin A15 of chip U15 is connected with DDR 15 _ DQ15, pin C15 of chip U15 is connected with DDR 15 _ DQ15, pin D15 of chip U15 is connected with DDR 15 _ DQ15, pin H15 of chip U15 is connected with DDR DQ15 _ DQ15, pin D15 is connected with DDR DQ15 _ DQ15, pin D15 is connected with DDR U15 _ DQ15, pin D15 is connected with DDR 15, pin DQ15 is connected with DDR 15, pin D15, chip U15 is connected with DDR 15, DDR 15 is connected with DDR 15, chip U15, chip 15 is connected with DDR 15, DDR 15 is connected with DDR 15, chip DQ15, chip 15-DQ 15 is connected with DDR 15, DDR 15-DQ 15, DDR 15 is connected with DDR 15-DQ 15, chip 15-, pin D3 of chip U1 is connected to DDR3_ UDM0, pin K1 of chip U1 is connected to DDR3_ ODT, pin L8 of chip U1 is connected in series with resistor R1 and then grounded, pin T2 of chip U1 is connected to DDR3_ RSTn, pin a1 of chip U1, pin a8, pin C1, pin D2, pin C9, pin E9, pin F1, pin H2, pin H9, pin B2, pin R9, pin R1, pin N9, pin N1, pin D9, pin G7, pin K8, and pin K2 are connected to DVDDDDR, pin M8 of chip U1 and pin H1 are connected to DVDDVREF. A pin B1 of a chip U1, a pin B9, a pin D1, a pin D8, a pin E2, a pin G9, a pin E8, a pin F9, a pin G1, a pin G8, a pin E1, a pin M9, a pin B3, a pin A3, a pin T3, a pin P3, a pin J3, a pin M3, a pin J3, and a pin J3 are grounded, a pin T3 of the chip U3 is connected with the DDR3_ A3, a pin T3 of the chip U3 is connected with the DDR 3A 3, a pin T3 is connected with the DDR 3A 3, a pin N3 is connected with the pin B3A 3, a pin L3 of the chip U3 is connected with the DDR 3A 3, a pin B3, a pin L3 is connected with the DDR 3A 3, a pin B3, a pin, a pin N8 of a chip U2 is connected with a DDR3_ BA1, a pin M2 of the chip U2 is connected with a DDR3_ BA0, a pin K7 of the chip U2 is connected with a DDR3_ CLK _ N, a pin J7 of the chip U2 is connected with a DDR3_ CLK _ p, a pin K2 of the chip U2 is connected with a DDR 2_ CKE, a pin L2 of the chip U2 is connected with a DDR 2_ CS _ N, a pin K2 of the chip U2 is connected with a DDR 2_ CAS _ N, a pin J2 of the chip U2 is connected with a DDR 2_ RAS _ N, a pin L2 of the chip U2 is connected with a DDR 2_ WD _ WE _ N, a pin A2 of the chip U2 is connected with a DDR 2 DQ 2_ DQ2, a pin DQ U2 is connected with a pin DQ2, a pin DQ U2, a pin DQ2 is connected with a DDR 2, a pin DQ U2 is connected with a DDR 2_ DQ2, a pin DQ2 is connected with a chip 2, a DQ2, a chip U2, a chip 2 is connected with a chip 2_ DQ2, a chip 2_ DQ2 and a chip 2 is connected with a DDR 2, a chip 2 and a DDR 2, a DDR 2 is connected with a DDR 2_ DQ2, a DDR 2 and a DDR 2, a DDR 36, pin F of chip U is connected with DDR _ DQ, pin E of chip U is connected with DDR _ DQ, pin C of chip U is connected with DDR _ DQSU _ P, pin B of chip U is connected with DDR _ DQSU _ N, pin F of chip U is connected with DDR _ DQSL _ P, pin G of chip U is connected with DDR _ DQSL _ N, pin E of chip U is connected with DDR _ LDM, pin D of chip U is connected with DDR _ UDM, pin K of chip U is connected with DDR _ ODT, pin L of chip U is connected with resistor R in series and then is grounded, pin T of chip U is connected with DDR _ RSTn, pin A of chip U, pin A, pin C, pin D, pin C, pin E, pin F, pin H, pin B, pin R, pin N, pin D, pin G, pin K is connected with DVDDR DDD, pin M of chip U and pin H is connected with DVVREF. The chip U2 is grounded with a pin B1, a pin B9, a pin D1, a pin D8, a pin E2, a pin G9, a pin E8, a pin F9, a pin G1, a pin G8, a pin E1, a pin M9, a pin B3, a pin a9, a pin T9, a pin T1, a pin P9, a pin P1, a pin J2, a pin M1, and a pin J8.
As shown in fig. 7, the ethernet interface circuit is composed of a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a crystal Y2, a magnetic bead FB1, a plug U8 with an interface transformer and an LED indicator RJ45, and an ethernet interface chip U7; pin 3, pin 19, pin 26, pin 35, pin 38, pin 39 of chip U7 are shorted, pin 6, pin 40, pin 42 of chip U7 are shorted, pin 7 of chip U7 is connected with PHY _ MDC, pin 8 of chip U7 is connected with PHY _ MDIO, pin 10 of chip U7 is grounded, pin 13 of chip U7 is connected with pin 12 of chip U8, pin 14 of chip U8 is connected with pin 13 of chip U8, pin 15 of chip U8 is connected with PHY _ CONFIG, pin 16 of chip U8 is connected with resistor R8 in parallel and connected with PHY _ RESETn, one end of resistor R8 is connected with DVDD3V 8, pin 17 of chip U8 is connected with pin 9 of chip U8, pin 18 of chip U8 is connected with pin 8 of chip U8, pin 20, pin 25 of chip U8 is shorted, then connected with pin DVDD3V 8, pin 21 of chip U8 is connected with pin 6 of chip U8, pin 22 of chip U8 is connected with pin 5 of chip U8, pin 72 is connected with pin 23, pin 8 is connected with pin 8, pin 8 is connected with chip U8 and connected with chip U, pin 22 of chip U7 is connected to pin 2 of chip U8, pin 30 of chip U7 is connected to ground after being connected to resistor R24, pin 31 of chip U7 is connected to ground after being connected to resistor R25, pin 32 of chip U7 is connected to ground after being connected to resistor R26, pin 33 of chip U7 is connected to crystal Y2, capacitor C10, one end of capacitor C10 is connected to ground, pin 34 of chip U7 is connected to crystal Y2, capacitor C19, one end of capacitor C9 is connected to ground, pin 36 of chip U7 is connected to DVDD3V3, pin 37 of chip U7 is connected to pin C8 after being connected to pin 41 of chip U7, pin 43 of chip U7 is connected to PHY _ RX _ CTRL, pin 44 of chip U7 is connected to pin RXD0, pin 45 of chip U0 is connected to RXD0, pin 46 of chip U0 is connected to PHY _ RX _ CLK, pin 0 is connected to chip TX _ chip 0, pin 0 is connected to chip TX _ chip TX _ 0, chip TX _ 0 is connected to chip TX _ chip 0, chip TX _ chip 0 is connected to chip 0, chip TX _ chip 0, pin 55 of chip U7 is connected with PHY _ TXD3, pin 56 of chip U7 is connected with PHY _ TX _ CTRL, pin 11 of chip U7, pin 36, pin 49 and pin 52 are connected with DVDD3V3, pin 1 of chip U8 is connected with capacitor C11 in series and then grounded, pin 11 of chip U8 is connected with resistor R22 in series and then connected with DVDD3V3, pin 14 of chip U8 is connected with resistor R23 in series and then connected with DVDD3V3, and pin 10, pin 15 and pin 16 of chip U8 are connected with protective ground.
As shown in fig. 8, the USB interface circuit is composed of a resistor R20, a resistor R21, a diode D1, a capacitor C5, a capacitor C6, a capacitor C7, a crystal oscillator Y1, a socket USB1, and a USB interface chip U6; chip U pin 12 is grounded after being connected in series with C, chip U pin 3 is connected with OTG _ DATA, chip U pin 4 is connected with OTG _ DATA, chip U pin 5 is connected with OTG _ DATA, chip U pin 6 is connected with OTG _ DATA, chip U pin 7 is connected with OTG _ DATA, chip U pin 9 is connected with OTG _ DATA, chip U pin 10 is connected with OTG _ DATA, chip U pin 13 is connected with OTG _ DATA, chip U pin 26 is connected with OTG _ CLK, chip U pin 31 is connected with OTG _ DIR, chip U pin 29 is connected with OTG _ STP, chip U pin 2 is connected with OTG _ NXT, chip U pin 11 is connected with DVDD1V, chip U pin 27 is connected with resistor R and diode D in parallel, one end of resistor R is connected with DVDD1V, one end of diode D is connected with resistor R and then connected with OTG _ RESETG, chip U pin 23 is grounded, chip U pin 18 is connected with socket pin 3, chip U pin 19 is connected with USB pin 2, chip U pin 22 is connected with USB socket 5, pin 1 of a chip U6 is connected with pin 3 of a crystal oscillator Y1 to obtain a working clock, pin 14 of a chip U6 is connected with DVDD1V8, pin 20 and pin 21 of the chip U6 are short-circuited and connected with a parallel capacitor C6 and a capacitor C7 in parallel, the capacitors C6 and C7 are grounded in parallel, pin 33 of a chip U6 is grounded, pin 28, pin 30 and pin 32 of the chip U6 are short-circuited and then connected with DVDD1V8, pin 4 of the crystal oscillator Y1 is connected with DVDD3V3, pin 2 of the crystal oscillator Y1 is grounded, pin 1 of a socket USB1 is grounded, and pin 5 and pin 6 of a socket USB1 are connected with a protective.
As shown in fig. 9, the AD converter circuit is composed of a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a socket J1, and an AD converter chip U3; pin 9 and pin 10 of chip U3 are short-circuited to connect to AD _ CONVST, pin 11 of chip U3 is connected to AD _ RESET, pin 12 of chip U3 is connected to AD _ SCLK, pin 13 of chip U3 is connected to AD _ CS, pin 14 of chip U3 is connected to AD _ BUSY, pin 24 of chip U3 is connected to AD _ DOUTA, pin 25 of chip U3 is connected to AD _ DOUTB, pin 36 of chip U3 is connected to capacitor C4 in series and then to ADC _ AGND, pin 39 of chip U3 is connected to capacitor C3 in series and then to ADC _ AGND, pin 42 of chip U3 is connected to ADC _ AGND in series and to capacitor C2 in series, pin 44 of chip U3 and pin 45 are short-circuited and then to ADC _ AGND, pin 49 of chip U3 is connected to pin 3 in parallel and to resistor R3 and then to pin 15 of socket J3, pin 50 of chip U3 is connected to ADC _ AGND 3 and pin 3 is connected to socket 3 in parallel to chip U3 and to pin 3 and then to pin 3 and to chip U3 and pin 3 and then to connect to chip J3 and to chip 3, a pin 54 of a chip U3 is connected with a resistor R5 and then connected with an ADC _ AGND, a pin 55 of a chip U3 is connected with a resistor R6 and then connected with a pin 12 of a socket J1, a pin 56 of a chip U3 is connected with a resistor R6 and then connected with an ADC _ AGND, a pin 57 of a chip U3 is connected with a resistor R7 and then connected with a pin 5 of a socket J1, a pin 58 of a chip U3 is connected with a resistor R7 and then connected with an ADC _ AGND, a pin 59 of a chip U3 is connected with a resistor R8 and then connected with a pin 4 of a socket J1, a pin 60 of a chip U3 is connected with a resistor R3 and then connected with an ADC _ AGND, a pin 61 of a chip U3 is connected with a pin 3 of a resistor R3 and then connected with a pin 62 of a resistor R3 and then connected with a pin 4, a pin 63 of the ADC _ AGND, a pin 3 of the chip U3, a pin 37, a pin 38 and an AVV 8, pin 2, pin 16, pin 17, pin 18, pin 19, pin 20, pin 21, pin 22, pin 26, pin 27, pin 28, pin 29, pin 30, pin 31, pin 32, pin 33, pin 35, pin 40, pin 41, pin 43, pin 46, and pin 47 of the chip U3 are connected to ADC _ AGND, pin 11, pin 10, and pin 1 of socket J1 are connected to ADC _ AGND, pin 9 and pin 8 of socket J1 are connected to AVDD +12V, and pin 7 and pin 6 of socket J1 are connected to AVDD-12V.
As shown in fig. 10, the IO input interface circuit is composed of a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a capacitor C76, a socket J2, and an optocoupler OP 1; optical coupling OP pin 1, pin 4 connects DC220, optical coupling OP pin 2 parallel resistance R, resistance R termination DC220, resistance R one end socket J pin 5, optical coupling OP pin 3 parallel resistance R, resistance R one end connects DC220, resistance R one end socket J pin 6, optical coupling OP pin 5 ground connection, optical coupling OP pin 6 output keeps apart IO signal parallel resistance R and connects INPUT, resistance R one end connects DVDD3V, optical coupling OP pin 7 output keeps apart IO signal parallel resistance R and connects INPUT, resistance R one end connects DVDD3V, optical coupling OP pin 8 connects DVDD3V, socket J pin 4 connects DC220, socket J pin 3 connects DVDD24, socket J pin 2 ground connection, J pin 1 connects the guard ground.
As shown in fig. 11, the LoRa wireless communication circuit in the wireless communication module is composed of an SMA radio frequency antenna socket P1 and an LoRa chip U4; pin 5 of chip U4 is connected to E22_ M0, pin 6 of chip U4 is connected to E22_ M1, pin 7 of chip U4 is connected to E22_ TXD, pin 8 of chip U4 is connected to E22_ RXD, pin 10 of chip U4 is connected to DVDD3V3, pin 21 of chip U4 is connected to SMA radio frequency antenna socket P1 pin 1, pin 2, pin 3, pin 4, pin 11, pin 13, pin 19, pin 20, pin 22 are grounded, and pin 2, pin 3, pin 4, pin 5 of SMA radio frequency antenna socket P1 are grounded.
As shown in fig. 12, the RTC real-time clock circuit is composed of a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C76, a battery BT1, and an RTC real-time clock chip U14; pin 1 of chip U14 is connected in series with resistor R66 and then connected with DVDD3V3, pin 2 of chip U14 is connected in parallel with capacitor C76 and then connected with DVDD3V3, one end of capacitor C76 is grounded, pin 3 of chip U14 is connected in series with resistor R67 and then connected with DVDD3V3, pin 4 of chip U14 is connected with PS _ POR _ B to provide power-on reset signal for FPGA chip, pin 5 of chip U14 is grounded, pin 6 of chip U14 is connected with battery BT1 to obtain standby working power supply, one end of battery BT1 is grounded, pin 7 of chip U14 is connected in parallel with resistor R64 and then connected with RTC _ SDA, one end of resistor R64 is connected with dd3V3, pin 8 of chip U14 is connected in parallel with resistor R65 and then connected with RTC _ SCL, and one end of.
The power management module circuit diagram includes fig. 13a, fig. 13b, and fig. 13 c.
As shown in fig. 13a, a power management module circuit diagram a is partially composed of a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R34, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R41, a capacitor CD1, a capacitor CD2, a capacitor CD3, a capacitor CT1, a capacitor CT2, a capacitor C2, an inductor L2, a magnetic bead FB 72, a diode D2, a switch U2, and a power chip U2; DVDD24V is connected with a capacitor C14, a capacitor CD1 and a capacitor CT1 in parallel and then connected with a pin 1 and a pin 14 of a chip U9, the capacitor C14, the capacitor CD1 and the capacitor CT1 are connected with the ground in parallel, a pin 2 of the chip U9 is connected with a resistor R28, one end of a resistor R28 is connected with a capacitor C15, one end of a capacitor C15 is connected with an inductor L1, a diode D2 and a capacitor C17 in parallel and then connected with a pin 3 of the chip U17, the capacitor C17 is connected with a resistor R17 in series and then connected with the ground, one end of the diode D17 is connected with the ground, one end of the inductor L17 is connected with a capacitor CD 17, a capacitor C17, a resistor R17 in parallel and then connected with a power supply DVDD1V 17, one end of the capacitor CD 17 is connected with the ground, one end of the capacitor C17 is connected with the pin 17 in parallel and then connected with the pin 7 of the chip U17, one end of the resistor R17 is connected with the chip U, one end of a resistor R29 is connected with a capacitor C16, one end of a capacitor C16 is connected with an inductor L2, a diode D3 and a capacitor C18 in parallel and then connected with a pin 12 of a chip U9, a capacitor C18 is connected with a resistor R32 in series and then connected with the ground, one end of a diode D3 is connected with the ground, one end of an inductor L2 is connected with a capacitor C19, a capacitor CD2, a capacitor C22 and a resistor R22 in parallel and then output a power supply DVDD1V 22, one end of the capacitor C22 is connected with the ground, one end of the capacitor CD 22 is connected with the ground, the capacitor C22 is connected with a resistor R22 in parallel and then connected with a pin 8 and a pin 5 of the chip U22, one end of the resistor R22 is connected with the ground, the capacitor C22 is connected with the pin 8 and the pin 5 of the chip U22 in parallel and then connected with the short circuit FB 22, the pin 1, the pin 2 of the chip U22 and the capacitor C22 are connected with the pin 72 in parallel and the capacitor C22 in parallel and the short circuit, one end of the capacitor C22 and the capacitor C22, The capacitor C40 and the resistor R39 output a power supply DVDD5V, the capacitor C36, the capacitor C37, the capacitor C38, the capacitor C39 and the capacitor C40 are grounded in parallel, one end of the resistor R39 outputs a power supply AVDD _5V, and the ADC _ AGND is connected in series with the resistor R41 and grounded.
As shown in fig. 13b, the power management module circuit diagram b is partially composed of a resistor R42, a resistor R44, a resistor R46, a resistor R47, a resistor R48, a resistor R50, a resistor R52, a resistor R53, a resistor R54, a capacitor CD4, a capacitor CD5, a capacitor CD6, a capacitor CT3, a capacitor CT5, a capacitor CT8, a capacitor CT9, a capacitor C9, a capacitor L9, an inductor L9, a diode D9, a switch U9, and a power supply chip U9; DVDD24V is connected with a capacitor C41, a capacitor CD4 and a capacitor CT3 in parallel and then connected with a pin 1 and a pin 14 of a chip U12, the capacitor C41, the capacitor CD4 and the capacitor CT3 are connected with the ground in parallel, a pin 2 of the chip U12 is connected with a resistor R42, one end of a resistor R42 is connected with a capacitor C44, one end of a capacitor C44 is connected with an inductor L5, a diode D4 and a capacitor C49 in parallel and then connected with a pin 3 of the chip U49, the capacitor C49 is connected with a resistor R49 in series and then connected with the ground, one end of the diode D49 is connected with the ground, one end of the inductor L49 is connected with a capacitor CD 49, a capacitor C49, one end of the capacitor C49 and a resistor R49 in parallel and then connected with a pin 3 of the resistor R49 in parallel and then connected with the ground, one end of the capacitor C49, one end of the resistor R49 is connected with the chip U49, one end of the capacitor C49 and the pin 49 is connected with the ground, one end of a resistor R44 is connected with a capacitor C45, one end of a capacitor C45 is connected with an inductor L6, a diode D5 and a capacitor C50 in parallel and then connected with a pin 12 of a chip U12, a capacitor C50 is connected with a resistor R46 in series and then connected with the ground, one end of a diode D5 is connected with the ground, one end of an inductor L6 is connected with a capacitor C56, a capacitor CD6, a capacitor C57 and a resistor R48 in parallel and then output power DVDD3V3, one end of a capacitor C56 is connected with the ground, one end of a capacitor CD6 is connected with the ground, one end of a capacitor C57 is connected with a resistor R48 and. DVDD24V is connected in parallel with a capacitor CT9 and an inductor L9, one end of the capacitor CT9 is grounded, one end of the inductor L9 is connected in parallel with a capacitor C9 and then connected with a pin 2 of a chip U9, one end of the capacitor C9 is grounded, a pin 1 of the chip U9 is grounded, a pin 6 of the chip U9 is connected with the inductor L9, one end of the inductor L9 is connected in parallel with the capacitor CT9, a capacitor C9 and then output a power supply AVDD +12V, the capacitor CT9, the capacitor C9 and the capacitor C9 are connected in parallel and then connected with an ADC _ AGND, a pin 7 of the chip U9 is connected with the ADC _ AGND, a pin 8 of the chip U9 is connected with the inductor L9, one end of the inductor L9 is connected in parallel with the capacitor CT9, the capacitor C9 and then output the power supply AVDD-12V, the capacitor CT.
As shown in fig. 13C, the power management module circuit diagram C is partially composed of a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61, a resistor R62, a resistor R63, a capacitor CD7, a capacitor CD8, a capacitor CT6, a capacitor CT7, a capacitor C59, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C67, a capacitor C68, a capacitor C69, a capacitor C70, a capacitor C71, a capacitor C72, a capacitor C74, a capacitor C75, an inductor L7, a power transistor Q1, a power transistor Q2, and a switching power chip U13; DVDD24V is connected with a capacitor CT6, a capacitor CD7 and a capacitor C59 in parallel and then connected with a pin 5, a pin 6, a pin 7 and a pin 8 of a power tube Q1, a capacitor CT6, a capacitor CD7 and a capacitor C59 are connected with the ground in parallel, a pin 4 of the power tube Q1 is connected with a pin 21 of a chip U13, a pin 1, a pin 2 and a pin 3 of the power tube Q1 are connected with a short-circuit parallel inductor L1, C68 and R61 in parallel and then connected with a pin 20 of the chip U13 and a pin 5, a pin 6, a pin 7 and a pin 8 of the power tube Q2, one end of a capacitor C68 is connected with a pin 22 of the chip U13, a pin 4 of the power tube Q2 is connected with a pin 19 of the U13, a pin 1, a pin 2 and a pin 3 of the power tube Q2 are connected with a resistor R63, a resistor R61, a capacitor C74 in parallel and then connected with a pin 16 of the chip U13, a capacitor C74 and a resistor R63 and a resistor R2 are connected with the ground in parallel and a power tube U2, one end of the capacitor, a resistor R is connected with a resistor R in parallel and then connected with a chip U pin 9, one end of the resistor R is grounded, a DVDD5 is connected with a capacitor C, a capacitor C and a resistor R in parallel and then connected with a chip U pin 15, the capacitor C and the capacitor C are grounded in parallel, one end of the resistor R is connected with the capacitor C in parallel and then connected with a chip U pin 14, the capacitor C and the capacitor C are grounded in parallel, a chip U pin 24 is connected with the resistor R, the capacitor C and the resistor R in parallel and then connected with a chip U pin 2, the capacitor C and the capacitor C are grounded in parallel, one end of the resistor R is connected with a capacitor CT in parallel and then outputs a power supply DVDDVTT, one end of the capacitor CT is grounded, the chip U pin 5 is connected with the capacitor C, the capacitor C and the capacitor C in parallel and then outputs a power supply DDVREF, the capacitor C and, the chip U13 pins 1, 3, 25, 17 and 18 are grounded, and the chip U13 pins 4, 10 and 11 are connected to DVDD 5V.
The working principle of the invention is as follows:
the connection between the wireless sensor device and the circuit breaker operating mechanism is shown in fig. 2, the wireless sensor device adopts a synchronous sampling technology, the current of a switching-off coil, the current of a switching-on coil, the current of an energy storage motor and the secondary current of a main loop CT of the circuit breaker are collected through a Hall current sensor, and the state signal of an auxiliary switch of the circuit breaker is collected through an IO port. The collected current signals of the opening/closing coil and the energy storage motor are analyzed through wave recording to identify the operation time and the current magnitude of each stage in the action process of the circuit breaker; and evaluating the health condition of the circuit breaker by analyzing the recording curve and combining comparison of a standard curve library. The breaker action current recording curve and the analysis result are encrypted and then sent to the monitoring platform in real time in a wireless mode.
Claims (2)
1. A wireless sensor device for detecting the current of a switching-on and switching-off coil of a circuit breaker comprises an FPGA (field programmable gate array) embedded with an ARM9 core, a memory, an RTC (real time clock), a USB (universal serial bus) interface, an Ethernet interface, an AD (analog-to-digital) converter, an IO (input/output) input interface, a wireless communication module and a power management module; the FPGA bidirectional communication memory embedded with the ARM9 core, the RTC real-time clock, the USB interface and the Ethernet interface; the current sensor is communicated with the AD converter; the AD converter is communicated with the FPGA embedded with the ARM9 core; the IO input interface is communicated with the FPGA embedded with the ARM9 core; the FPGA embedded with the ARM9 core is interconnected with the wireless communication module; the wireless communication module is communicated with the monitoring platform; the power management module supplies power to the FPGA embedded with the ARM9 core, the memory, the RTC real-time clock, the USB interface, the Ethernet interface, the AD converter, the IO input interface and the wireless communication module;
the current sensor converts the current of the opening and closing coil of the circuit breaker and the current of the energy storage motor into analog voltage signals and outputs the analog voltage signals to the AD converter;
the AD converter synchronously converts input multi-channel analog current/voltage signals into digital signals and outputs the digital signals to an FPGA port embedded with an ARM9 core;
the IO input interface acquires the opening and closing state of the auxiliary switch of the circuit breaker and outputs the opening and closing state to an FPGA port embedded with an ARM9 core;
the FPGA embedded with the ARM9 core periodically acquires input data, writes the acquired opening and closing current data into a memory in a file form during the opening and closing action of the circuit breaker, and outputs the data to the wireless communication module through a serial port;
the wireless communication module encrypts the received data and sends the encrypted data to the monitoring platform in real time; the wireless communication protocol can be a Modbus RTU or a proprietary protocol;
the RTC provides a real-time clock for the wireless sensor device, and the real-time clock is used as time data stored in the monitoring data file; receiving the timing of the monitoring platform through the wireless communication module;
the wireless sensor device is provided with a large-capacity memory which comprises a Flash memory, an SD card and a DDR memory and can store at least 10000 groups of monitoring data;
monitoring data files stored by the wireless sensor device can be exported to a USB memory through a USB interface, and import and data analysis are carried out on a monitoring platform;
the wireless sensor device can also send a monitoring data file to the monitoring platform in a wired connection mode of an Ethernet interface;
the power management module realizes the conversion of a direct current 24V power supply to +/-12V, 5V, 3.3V, 1.8V, 1.5V, 1.0V and 0.75V direct current low voltage and provides a working power supply for each functional module in the wireless sensor device;
the current sensor can be an open-close type or a through type Hall current sensor;
the communication mode of the wireless sensor device can be LoRa, NBiot and other wireless interfaces;
the wireless sensor device can also acquire the secondary current of the main loop CT and the current of the energy storage motor of the circuit breaker and wirelessly transmit data.
2. The wireless sensor device for detecting the current of the switching-on and switching-off coils of the circuit breaker according to claim 1, wherein the FPGA circuit embedded with the ARM9 core is composed of a resistor R87, a resistor R88, a resistor R89, a resistor R90, a resistor R91, a resistor R92, a capacitor C78, a capacitor C79, a capacitor C80, a magnetic bead FB5, a self-reset switch SW1, a crystal oscillator Y3, a resistor R68, a resistor R69, a resistor R70, a resistor R71, a resistor R72, a resistor R73, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a light emitting diode D78, a magnetic bead FB 78, a chip U78, a J78, a P78, a resistor R78 and an FPGA U78;
the circuit of the Flash memory and the SD card in the memory consists of a resistor R17, a resistor R18, a resistor R19, a TF card slot P2 and a NAND Flash memory chip U5;
the DDR memory circuit in the memory consists of a resistor R1, a resistor R2, a DDR memory chip U1 and a chip U2;
the Ethernet interface circuit consists of a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a crystal Y2, a magnetic bead FB1, a built-in interface transformer, an LED indicator RJ45 socket U8 and an Ethernet interface chip U7;
the USB interface circuit consists of a resistor R20, a resistor R21, a diode D1, a capacitor C5, a capacitor C6, a capacitor C7, a crystal oscillator Y1, a socket USB1 and a USB interface chip U6;
the AD converter circuit consists of a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a socket J1 and an AD converter chip U3;
the IO input interface circuit consists of a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a capacitor C76, a socket J2 and an optocoupler OP 1;
the LoRa wireless communication circuit in the wireless communication module consists of an SMA radio frequency antenna socket P1 and a LoRa chip U4;
the RTC real-time clock circuit consists of a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C76, a battery BT1 and an RTC real-time clock chip U14;
the power management module circuit comprises a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R34, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R41, a capacitor CD1, a capacitor CD2, a capacitor CD3, a capacitor CT1, a capacitor CT2, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36, a capacitor C37, a capacitor C38, a capacitor C39, a capacitor C40, an inductor L1, an inductor L2, an inductor L4, a magnetic bead FB3, a diode D2, a diode D3, a switching power supply U9, a switching power supply chip U9, a resistor R36363672, a resistor R9, a resistor R36363672, a capacitor C9, a capacitor C363636363672, a capacitor C, the power supply comprises a capacitor C41, a capacitor C44, a capacitor C45, a capacitor C49, a capacitor C50, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a capacitor C81, a capacitor C82, a capacitor C83, a capacitor C84, a capacitor C85, a capacitor C86, a capacitor C87, an inductor L5, an inductor L6, an inductor L8, an inductor L9, an inductor L10, a diode D4, a diode D5, a switching power supply chip U10, a switching power supply chip U12, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61, a resistor R62, a resistor R63, a capacitor CD7, a capacitor CD8, a capacitor CT6, a capacitor C7, a capacitor C59, a capacitor C60, a capacitor C61, a capacitor C62, a power supply chip, a capacitor C62, a power supply chip, a.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485655A (en) * | 2020-10-29 | 2021-03-12 | 国网湖北省电力有限公司电力科学研究院 | Accurate monitoring device and method for tripping and closing loop of substation circuit breaker |
| CN114019336A (en) * | 2021-09-23 | 2022-02-08 | 北京无线电计量测试研究所 | Detection transistor temperature correction device and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261192A (en) * | 2008-04-24 | 2008-09-10 | 南京因泰莱配电自动化设备有限公司 | 24KV high-voltage vacuum breaker mechanical features on-line monitoring method and monitoring device |
| CN204215545U (en) * | 2014-11-17 | 2015-03-18 | 中环天仪股份有限公司 | Long-range calorimeter concentrator |
| CN105974305A (en) * | 2016-06-12 | 2016-09-28 | 河南森源电气股份有限公司 | Online monitoring system for mechanical characteristic of circuit breaker |
| CN107202954A (en) * | 2017-05-31 | 2017-09-26 | 东南大学 | Embedded breaker on-line monitoring system based on three core platforms |
| CN107631863A (en) * | 2017-08-21 | 2018-01-26 | 西安工程大学 | Mechanical characteristic of high-voltage circuit breaker monitoring system and its monitoring method |
-
2020
- 2020-08-07 CN CN202010789693.2A patent/CN111796142A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261192A (en) * | 2008-04-24 | 2008-09-10 | 南京因泰莱配电自动化设备有限公司 | 24KV high-voltage vacuum breaker mechanical features on-line monitoring method and monitoring device |
| CN204215545U (en) * | 2014-11-17 | 2015-03-18 | 中环天仪股份有限公司 | Long-range calorimeter concentrator |
| CN105974305A (en) * | 2016-06-12 | 2016-09-28 | 河南森源电气股份有限公司 | Online monitoring system for mechanical characteristic of circuit breaker |
| CN107202954A (en) * | 2017-05-31 | 2017-09-26 | 东南大学 | Embedded breaker on-line monitoring system based on three core platforms |
| CN107631863A (en) * | 2017-08-21 | 2018-01-26 | 西安工程大学 | Mechanical characteristic of high-voltage circuit breaker monitoring system and its monitoring method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485655A (en) * | 2020-10-29 | 2021-03-12 | 国网湖北省电力有限公司电力科学研究院 | Accurate monitoring device and method for tripping and closing loop of substation circuit breaker |
| CN112485655B (en) * | 2020-10-29 | 2022-05-31 | 国网湖北省电力有限公司电力科学研究院 | Accurate monitoring device and method for tripping and closing loop of substation breaker |
| CN114019336A (en) * | 2021-09-23 | 2022-02-08 | 北京无线电计量测试研究所 | Detection transistor temperature correction device and method |
| CN114019336B (en) * | 2021-09-23 | 2023-10-03 | 北京无线电计量测试研究所 | Temperature correction device and method for detection transistor |
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