CN111785717A - SCR electrostatic protection structure and forming method thereof - Google Patents

SCR electrostatic protection structure and forming method thereof Download PDF

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Publication number
CN111785717A
CN111785717A CN201910272299.9A CN201910272299A CN111785717A CN 111785717 A CN111785717 A CN 111785717A CN 201910272299 A CN201910272299 A CN 201910272299A CN 111785717 A CN111785717 A CN 111785717A
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type
doped region
well
type doped
type well
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CN111785717B (en
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杜飞波
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An SCR electrostatic protection structure and a forming method thereof are disclosed, the structure comprises: a first unit and a second unit; the first unit includes: a first P-type doped region located on top of the first N-type well; a first N-type doped region located on top of the first P-type well; the second unit includes: the second P-type doped region and the third N-type doped region are positioned at the top part in the second N-type well; the second N-type doped region and the third P-type doped region are positioned at the top part in the second P-type well; bridging the doped group; the cross-over doping group comprises: a plurality of fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is vertical to the first direction; a fourth N-type doped region between adjacent fourth P-type doped regions; and the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region. The performance of the SCR electrostatic protection structure is improved.

Description

SCR electrostatic protection structure and forming method thereof
Technical Field
The invention relates to the field of electrostatic protection, in particular to an SCR electrostatic protection structure and a forming method thereof.
Background
In the manufacture and application of integrated circuit chips, with the continuous improvement of super-large-scale integrated circuit process technology, the current CMOS integrated circuit manufacturing technology has entered the deep submicron stage, the size of MOS devices has been continuously reduced, the thickness of gate oxide layer is thinner and thinner, the voltage withstanding capability of MOS devices is significantly reduced, and the damage of Electrostatic Discharge (ESD) to integrated circuits has become more and more significant. Therefore, ESD protection of integrated circuits becomes particularly important.
In order to enhance the protection capability against static electricity, an electrostatic protection circuit is usually connected to an input/output interface (I/O pad) of the chip, and the electrostatic protection circuit provides a discharge path for electrostatic current for internal circuits in the chip to prevent the static electricity from breaking down the internal circuits of the chip.
However, the performance of the conventional electrostatic protection structure is poor.
Disclosure of Invention
The invention provides an SCR electrostatic protection structure and a forming method thereof, which aim to improve the performance of the SCR electrostatic protection structure.
In order to solve the above problems, the present invention provides an SCR electrostatic protection structure, including: a semiconductor substrate; a first unit and a second unit which are separated and located in a semiconductor substrate; the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located along a first direction at a side of the first N-type well and adjacent to the first N-type well; a first P-type doped region located on top of the first N-type well; a first N-type doped region located on top of the first P-type well; the second unit includes: a second N-type well and a second P-type well in the semiconductor substrate, the second P-type well being located along a first direction at a side of the second N-type well and adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are positioned on the top of the second N-type well and are mutually separated; the second N-type doped region and the third P-type doped region are positioned on the top of the second P-type well and are separated from each other; bridging the doped group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the cross-over doping group comprises: a plurality of discrete fourth P-type doped regions arranged along a second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; a fourth N-type doped region located between adjacent fourth P-type doped regions and adjacent to the fourth P-type doped region, the fourth N-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well; and the conductive structure is positioned on the semiconductor substrate and is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
Optionally, the number of the second units is one; and the second N-type doped region and the third P-type doped region are both connected with a cathode potential.
Optionally, the number of the second units is multiple; the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region and the third P-type doped region in the ith-level second unit are electrically connected with the second P-type doped region and the third N-type doped region in the (i + 1) th-level second unit, i is an integer which is more than or equal to 1 and less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the Q-level second unit are connected with a cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region and the third N-type doped region in the first-level second unit.
Optionally, the first P-type doped region is connected to an anode potential.
Optionally, the first unit further includes: and the fifth N-type doped region is positioned at the top in the first N-type well, the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region.
Optionally, the first unit further includes: and the fifth P-type doped region is positioned at the top in the first P-type well, the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
Optionally, the first unit further includes: a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
Optionally, the first isolation group layer includes a sixth P-type doped region and first isolation insulation layers respectively located at two sides of the sixth P-type doped region along the first direction, the sixth P-type doped region is located at the top of a portion of the first N-type well and extends to the top of a portion of the first P-type well, the first isolation insulation layer at one side of the sixth P-type doped region is located in the first N-type well, and the first isolation insulation layer at the other side of the sixth P-type doped region is located in the first P-type well.
Optionally, the first isolation group layer is a single-layer structure, and the material of the first isolation group layer includes silicon oxide.
Optionally, the first unit further includes: the first side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the first P-type well along the first direction and is adjacent to the first P-type well, the first P-type well is positioned between the first side isolation well and the first N-type well, and the conductivity type of the first side isolation well is N-type; and the first bottom isolation well is positioned at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is also respectively connected with the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is an N type.
Optionally, the second unit further includes: the second side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the second P-type well along the first direction and is adjacent to the second P-type well, is positioned between the second side isolation well and the second N-type well, and has an N-type conductivity type; and the second bottom isolation well is positioned at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is also respectively connected with the bottom of the second N-type well and the bottom of the second side isolation well, and the conductivity type of the second bottom isolation well is an N type.
Optionally, the method further includes: and the seventh P-type doped region is positioned at the top part of the semiconductor substrate, is respectively positioned between the adjacent first unit and the second unit and on two sides of the second unit along the first direction, and is grounded.
Optionally, the conductive structure is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the conductive structure is made of metal silicide.
Optionally, the semiconductor substrate has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
The invention also provides a method for forming the SCR electrostatic protection structure, which comprises the following steps: providing a semiconductor substrate; forming a first unit and a second unit which are separated in a semiconductor substrate; the method of forming the first cell includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at a side portion of the first N-type well in a first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well; the method of forming the second cell includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at a side portion of the second N-type well in the first direction; forming a second P-type doped region and a third N-type doped region which are separated from each other on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are separated from each other on the top in the second P-type well; forming a cross-over doping group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the method for forming the cross-over doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is vertical to the first direction; forming a fourth N-type doped region adjacent to the fourth P-type doped region between the adjacent fourth P-type doped regions, wherein the fourth N-type doped region is positioned on the top of part of the second N-type well and extends to the top of part of the second P-type well; and forming a conductive structure on the semiconductor substrate, wherein the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
Optionally, the method of forming the first unit further includes: forming a fifth N-type doped region on the top of the first N-type well, wherein the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region; and forming a fifth P-type doped region on the top of the first P-type well, wherein the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
Optionally, the method of forming the first unit further includes: a first isolation group layer is formed in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located on top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.
Optionally, the method of forming the first unit further includes: before a first P-type doped region and a first N-type doped region are formed, a first side isolation well and a first bottom isolation well are formed in a semiconductor substrate, the first side isolation well is located on the side portion of the first P-type well along a first direction and is abutted to the first P-type well, the first P-type well is located between the first side isolation well and the first N-type well, the first bottom isolation well is located at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is further connected with the bottom of the first N-type well and the bottom of the first side isolation well respectively, and the conductivity types of the first side isolation well and the first bottom isolation well are both N-type.
Optionally, the method of forming the second unit further includes: before forming a second P-type doped region, a second N-type doped region, a third N-type doped region and a third P-type doped region, a second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located on the side portion of the second P-type well along the first direction and is abutted to the second P-type well, the second P-type well is located between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is further connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity types of the second side isolation well and the second bottom isolation well are both N-type.
Optionally, the method further includes: and forming seventh P-type doped regions on the top of part of the semiconductor substrate, wherein the seventh P-type doped regions are respectively positioned between the adjacent first unit and second unit and on two sides of the second unit along the first direction, and all the seventh P-type doped regions are grounded.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the SCR electrostatic protection structure provided by the technical scheme of the present invention, the SCR electrostatic protection structure includes a first current leakage structure and a second current leakage structure. The first current leakage structure is a PNPN structure and comprises a first PNP tube and a first NPN tube, the first P-type doped region serves as an emitting electrode of the first PNP tube, a first N-type well at the bottom of the first P-type doped region serves as a base electrode of the first PNP tube, a first P-type well at the bottom of the first N-type doped region serves as a collector electrode of the first PNP tube, a first N-type well at the bottom of the first P-type doped region serves as a collector electrode of the first NPN tube, a first P-type well at the bottom of the first N-type doped region serves as a base electrode of the first NPN tube, and a first N-type doped region serves as an emitting electrode of the first NPN tube. The second current leakage structure is a PNPN structure and comprises a second PNP tube and a second NPN tube, the second P-type doped region is used as an emitting electrode of the second PNP tube, a second N-type well at the bottom of the second P-type doped region is used as a base electrode of the second PNP tube, a second P-type well at the bottom of the second N-type doped region is used as a collector electrode of the second PNP tube, a second N-type well at the bottom of the second P-type doped region is used as a collector electrode of the second NPN tube, a second P-type well at the bottom of the second N-type doped region is used as a base electrode of the second NPN tube, and a second N-type doped region is used as an emitting electrode of the second NPN tube. The second current leakage structures in the second units of each stage are connected in series. SCR electrostatic protection structure still includes resistance water conservancy diversion structure, and resistance water conservancy diversion structure includes: the third N-type doped region, the second N-type well, the cross-over doped group, the second P-type well and the third P-type doped region. The first current leakage path corresponds to the first current leakage structure, and the second current leakage path corresponds to the second current leakage structure. The resistive flow directing structure has a resistive flow directing path that includes: from the third N-type doped region to the second N-type well, from the second N-type well to a fourth N-type doped region bridging the doped group, from the fourth N-type doped region to a fourth P-type doped region through the conductive structure, from the fourth P-type doped region to the second P-type well, from the second P-type well to the third P-type doped region. The resistance diversion paths in the second units of each stage are connected in series. The first current leakage path and the second current leakage path are superposed in series, so that the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the sum of the holding voltage of the first current leakage structure and the holding voltage of the second current leakage structure, so that the holding voltage of the SCR electrostatic protection structure is increased. Because the holding voltage of the SCR electrostatic protection structure is improved, the range of the normal working voltage of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure. Applying trigger voltage on the cathode and the anode, wherein in an initial stage, a second current discharge path in the second unit is not conducted, a resistance flow guide structure in the second unit is conducted, the voltage drop on the second unit is small, most of the trigger voltage is applied on the first unit to enable a first current discharge path in the first unit to be conducted, and therefore the first current discharge path is triggered to perform current discharge, and then, as the conduction of the first current discharge path triggers the conduction of the second current discharge path, the first current discharge path is triggered to perform current discharge. Therefore, the trigger voltage required by the conduction of the first current leakage path in the SCR electrostatic protection structure to trigger the conduction of the second current leakage path is reduced. In conclusion, the performance of the SCR electrostatic protection structure is improved.
Drawings
Fig. 1 to 4 are schematic structural diagrams illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
There are two important parameters in the SCR electrostatic protection architecture, the holding voltage and the trigger voltage, respectively. Higher holding voltage and lower trigger voltage are the process direction that SCR electrostatic protection structures are continuously pursuing.
The existing SCR electrostatic protection structure includes: a P-type semiconductor substrate; an SCR unit located in the semiconductor substrate; the SCR unit includes: a first N-type well in the semiconductor substrate; a first P-type well in the first N-type well, the first P-type well being located at a side of the first N-type well and adjoining the first N-type well; a second N-type well surrounding the first P-type well and the first N-type well; the P-type doped region is positioned at the top part in the first N-type well; and an N-type doped region located on top of the first P-type well.
In order to increase the holding voltage of the SCR electrostatic protection structure, the SCR electrostatic protection structure generally has a plurality of SCR units, and the plurality of SCR units are connected in series, specifically, the plurality of SCR units are respectively a first-stage SCR unit to a W-th-stage SCR unit, W is an integer greater than or equal to 2, an N-type doped region in the j-th-stage SCR unit is electrically connected to a P-type doped region in the j + 1-th-stage SCR unit, j is an integer greater than or equal to 1 and less than or equal to W-1, the P-type doped region in the first-stage SCR unit is connected to an anode potential, and the N-type doped region in the W-th-stage SCR unit is connected to a cathode potential.
However, the above structure increases the trigger voltage of the SCR electrostatic protection structure while increasing the holding voltage.
On this basis, the invention provides an SCR electrostatic protection structure, which includes: a first unit and a second unit in the semiconductor substrate; the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located along a first direction at a side of the first N-type well and adjacent to the first N-type well; a first P-type doped region located on top of the first N-type well; a first N-type doped region located on top of the first P-type well; the second unit includes: a second N-type well and a second P-type well in the semiconductor substrate, the second P-type well being located along a first direction at a side of the second N-type well and adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are positioned on the top of the second N-type well and are mutually separated; the second N-type doped region and the third P-type doped region are positioned on the top of the second P-type well and are separated from each other; bridging the doped group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the cross-over doping group comprises: a plurality of discrete fourth P-type doped regions arranged along a second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; the fourth N-type doped region is positioned between the adjacent fourth P-type doped regions and is adjacent to the fourth P-type doped region; and the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region. The performance of the SCR electrostatic protection structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 4 are schematic structural diagrams illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Referring to fig. 1, a semiconductor substrate 200 is provided.
The semiconductor substrate 200 has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
The semiconductor substrate 200 is made of monocrystalline silicon, monocrystalline germanium or monocrystalline silicon germanium.
The semiconductor substrate 200 includes a first unit region a and a second unit region B, which are separated from each other.
The number of the second unit areas B is one or more, in this embodiment, the number of the second unit areas B is taken as a plurality for illustration, and when the number of the second unit areas B is a plurality, the plurality of second unit areas B are separated from each other.
The first and second unit regions a and B are arranged in the first direction X, and the plurality of second unit regions B are arranged in the first direction X.
Next, a discrete first unit and a discrete second unit are formed in the semiconductor substrate 200. Specifically, a first cell is formed in the first cell region a, and a second cell is formed in the second cell region B.
In this embodiment, the number of the second unit areas B is plural, and correspondingly, the number of the second units is plural. In other embodiments, the number of second cells is one.
The method of forming the first cell includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at a side portion of the first N-type well in a first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well;
the method of forming the second cell includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at a side portion of the second N-type well in the first direction; forming a second P-type doped region and a third N-type doped region which are separated from each other on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are separated from each other on the top in the second P-type well; forming a cross-over doping group; the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected for adjacent first and second cells.
Referring to fig. 2, a first N-type well 201 is formed in a semiconductor substrate 200; forming a first P-type well 202 adjoining the first N-type well 201 at a side portion of the first N-type well 201 in the first direction X; forming a second N-type well 301 in the semiconductor substrate 200; a second P-type well 302 adjoining the second N-type well 301 is formed at a side portion of the second N-type well 301 in the first direction X.
The surface of the semiconductor substrate 200 is exposed out of the first N-type well 201, the first P-type well 202, the second N-type well 301 and the second P-type well 302, that is, the top surface of the first N-type well 201 is flush with the surface of the semiconductor substrate 200, the top surface of the first P-type well 202 is flush with the surface of the semiconductor substrate 200, the top surface of the second N-type well 301 is flush with the surface of the semiconductor substrate 200, and the top surface of the second P-type well 302 is flush with the surface of the semiconductor substrate 200.
In this embodiment, referring to fig. 2, the method of forming the first unit further includes: a first side isolation well 203 and a first bottom isolation well 204 are formed in the semiconductor substrate 200, the first side isolation well 203 is located on a lateral portion of the first P-type well 202 along the first direction X and is adjacent to the first P-type well 202, the first P-type well 202 is located between the first side isolation well 203 and the first N-type well 201, the first bottom isolation well 204 is located at a bottom of the first P-type well 202 and is adjacent to the first P-type well 202, and the first bottom isolation well 204 is further connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203 respectively.
The conductivity type of the first side isolation well 203 is N type, and the conductivity type of the first bottom isolation well 204 is N type.
The first bottom isolation well 204 is located at the bottom of the first P-type well 202 and is adjacent to the first P-type well 202, the first bottom isolation well 204 is further connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203, respectively, so that the first bottom isolation well 204, the first N-type well 201 and the first side isolation well 203 surround the first P-type well 202, the first P-type well 202 is isolated from the semiconductor substrate 200 at the bottom of the first bottom isolation well 204, and the first P-type well 202 is isolated from the semiconductor substrate 200 at the side of the first side isolation well 203.
In this embodiment, referring to fig. 2, the method for forming the second unit further includes: a second side isolation well 303 and a second bottom isolation well 304 are formed in the semiconductor substrate 200, the second side isolation well 303 is located at a side portion of the second P-well 302 along the first direction and is adjacent to the second P-well 302, the second P-well 302 is located between the second side isolation well 303 and the second N-well 301, the second bottom isolation well 304 is located at a bottom portion of the second P-well 302 and is adjacent to the second P-well 302, and the second bottom isolation well 304 is further connected to a bottom portion of the second N-well 301 and a bottom portion of the second side isolation well 303 respectively.
The conductivity type of the second side isolation well 303 is N-type, and the conductivity type of the second bottom isolation well 304 is N-type.
The second bottom isolation well 304 is located at the bottom of the second P-well 302 and is adjacent to the second P-well 302, the second bottom isolation well 304 is further connected to the bottom of the second N-well 301 and the bottom of the second side isolation well 303, respectively, so that the second bottom isolation well 304, the second N-well 301 and the second side isolation well 303 surround the second P-well 302, the second P-well 302 is isolated from the semiconductor substrate 200 at the bottom of the second bottom isolation well 304, and the second P-well 302 is isolated from the semiconductor substrate 200 at the side of the second side isolation well 303.
In this embodiment, the method of forming the first unit further includes: a first isolation insulating layer 510 and a second isolation insulating layer 520 are formed in the first cell region of the semiconductor substrate 200. In this embodiment, the first isolation insulating layer 510 is used to form a portion of a subsequent first isolation group layer.
A portion of second isolation insulating layer 520 is in first N-well 201, a portion of second isolation insulating layer 520 is in first P-well 202, and a portion of second isolation insulating layer 520 is on top of first side isolation well 203 and extends into a portion of first P-well 202.
In this embodiment, the method of forming the second unit further includes: a third isolation insulating layer 530 is formed in the second cell region of the semiconductor substrate 200.
A portion of third isolation insulating layer 530 is in second N-well 301, a portion of third isolation insulating layer 530 is in second P-well 302, and a portion of third isolation insulating layer 530 is on top of second side isolation well 303 and extends into a portion of second P-well 302.
The material of the first isolation insulating layer 510 includes silicon oxide. The material of the second isolation insulating layer 520 includes silicon oxide. The material of the third isolation insulating layer 530 includes silicon oxide.
Referring to fig. 3, a first P-type doped region 210 is formed on top in the first N-type well 201; forming a first N-type doped region 220 on top in the first P-type well 202; forming a second P-type doped region 310 and a third N-type doped region 330 separated from each other on top in the second N-type well 301; forming a second N-type doped region 320 and a third P-type doped region 340 separated from each other on top in the second P-type well 302; a cross-over doping group is formed.
The first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected for adjacent first and second cells.
The method for forming the cross-over doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions 350 arranged along a second direction Y, each fourth P-type doped region 350 being located on top of a portion of the second N-well 301 and extending to top of a portion of the second P-well 302, the second direction Y being perpendicular to the first direction X; a fourth N-doped region 360 is formed between adjacent fourth P-doped regions 350, adjacent to the fourth P-doped regions 350, the fourth N-doped region 360 being located on top of a portion of the second N-well 301 and extending to top of a portion of the second P-well 302.
The method of forming the first cell further comprises: a fifth N-type doped region 230 is formed on the top of the first N-well 201, the fifth N-type doped region 230 is separated from the first P-type doped region 210, and the fifth N-type doped region 230 is electrically connected to the first P-type doped region 210.
In this embodiment, the first P-type doped region 210 and the fifth N-type doped region 230 are both connected to the anode potential.
The method of forming the first cell further comprises: a fifth P-type doped region 240 is formed on top of the first P-well 202, the fifth P-type doped region 240 is separated from the first N-type doped region 220, and the fifth P-type doped region 240 is electrically connected to the first N-type doped region 220.
In this embodiment, the method of forming the first unit further includes: a sixth P-type doped region 250 is formed in the semiconductor substrate 200, the sixth P-type doped region 250 being located on top of a portion of the first N-type well 201 and extending to top of a portion of the first P-type well 202.
In this embodiment, the first isolation insulation layers are respectively located on two sides of the sixth P-type doped region 250 in the first direction X, the first isolation insulation layer on one side of the sixth P-type doped region 250 is located in the first N-type well 201, and the first isolation insulation layer on the other side of the sixth P-type doped region 250 is located in the first P-type well 202.
In this embodiment, the first isolation insulating layer and the sixth P-type doped region 250 constitute a first isolation group layer, the first isolation group layer is located in the semiconductor substrate 200 between the first P-type doped region 210 and the first N-type doped region 220, the first isolation group layer is located on top of a portion of the first N-type well 201 and extends to the top of a portion of the first P-type well 202.
The concentration of P-type ions in the sixth P-type doped region 250 is much greater than the concentration of P-type ions in the first P-type well 202.
In other embodiments, the first isolation group layer is a single layer structure, the material of the first isolation group layer includes silicon oxide, the first isolation group layer is located in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located on top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.
In this embodiment, the first P-type doped region 210, the first N-type doped region 220, the fifth N-type doped region 230, the fifth P-type doped region 240 and the sixth P-type doped region 250 are separated from each other, and the fifth P-type doped region 240, the first P-type doped region 210, the sixth P-type doped region 250, the first N-type doped region 220 and the fifth N-type doped region 230 are arranged along the first direction X.
In a specific embodiment, the first P-type doped region 210 is located between the fifth N-type doped region 230 and the first isolation set layer, and the first N-type doped region 220 is located between the fifth P-type doped region 240 and the first isolation set layer.
There are second isolation insulation layers 520 between the first P-type doped region 210 and the fifth N-type doped region 230, and between the first N-type doped region 220 and the fifth P-type doped region 240.
The second P-type doped region 310, the second N-type doped region 320, the third N-type doped region 330, the third P-type doped region 340 and the cross-over doping group are separated from each other.
In a specific embodiment, the second P-type doped region 310 is located between the cross-over doped group and the third N-type doped region 330, and the second N-type doped region 320 is located between the cross-over doped group and the third P-type doped region 340.
Third isolation insulation layers 530 are disposed between the second P-type doped region 310 and the third N-type doped region 330, between the second P-type doped region 310 and the cross-over doping group, between the second N-type doped region 320 and the third P-type doped region 340, and between the second N-type doped region 320 and the cross-over doping group.
The concentration of P-type ions in the fourth P-type doped region 350 is greater than the concentration of P-type ions in the second P-type well 302. The concentration of N-type ions in the fourth N-type doped region 360 is greater than the concentration of N-type ions in the second N-type well 301.
The first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected for adjacent first and second cells.
In this embodiment, taking the number of the second units as a plurality as an example, the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region 320 and the third P-type doped region 340 in the ith-level second unit are electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the (i + 1) -level second unit, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the Q-level second unit are connected with a cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the first-level second unit.
In this embodiment, an example in which Q is equal to 2 is described, the number of the second units is two, and the plurality of second units are the first-stage second unit to the second-stage second unit, respectively.
In other embodiments, Q may be 3, 4, 5, 6, or an integer greater than or equal to 7.
In other embodiments, the number of the second cells is one, and the second N-type doped region and the third P-type doped region are both connected to a cathode potential.
The forming method of the SCR electrostatic protection structure further comprises the following steps: seventh P-type doped regions 400 are formed on the top of a portion of the semiconductor substrate 200, the seventh P-type doped regions 400 are respectively located between the adjacent first unit and second unit and on two sides of the second unit along the first direction X, and each of the seventh P-type doped regions 400 is grounded.
Each of the seventh P-type doped regions 400 is grounded to ground the semiconductor substrate 200, thereby avoiding latch-up.
In this embodiment, a second isolation insulating layer 520 is disposed between the seventh P-type doped region 400 and the fifth P-type doped region 240, and specifically, a second isolation insulating layer 520 is disposed between the seventh P-type doped region 400 between the first cell and the first-level second cell and the fifth P-type doped region 240 in the first cell.
In this embodiment, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 and the third N-type doped region 330. Specifically, a third isolation insulating layer 530 is arranged between the seventh P-type doped region 400 between the first cell and the first-level second cell and the third N-type doped region 330 in the first-level second cell; a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 between the ith-level second cell and the (i + 1) -level second cell and the third N-type doped region 330 in the (i + 1) -level second cell.
In this embodiment, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 and the third P-type doped region 340, and specifically, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 between the ith-level second cell and the (i + 1) th-level second cell and the third P-type doped region 340 in the ith-level second cell.
Referring to fig. 4, a conductive structure 500 is formed on the semiconductor substrate 200, the conductive structure 500 electrically connecting the fourth N-type doped region and the fourth P-type doped region.
In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the conductive structure 500 is made of metal silicide.
In other embodiments, the conductive structure comprises: the first metal silicide layer is positioned on the surface of the fourth N-type doped region; the second metal silicide layer is positioned on the surface of the fourth P-type doped region, and the first metal silicide layer and the second metal silicide layer are mutually separated; and the metal connecting layers are positioned on the first metal silicide layer and the second metal silicide layer and are respectively connected with the first metal silicide layer and the second metal silicide layer.
When the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region, and the material of the conductive structure 500 is a metal silicide, the structure of the conductive structure 500 is simpler, and the manufacturing cost is reduced.
In this embodiment, the method further includes: and a first connection layer on the semiconductor substrate, the first connection layer being connected to the first P-type doped region 210 and the fifth N-type doped region 230, respectively, the first connection layer being connected to an anode potential. The material of the first connection layer comprises a metal, such as copper or aluminum.
In this embodiment, the method further includes: and a second connection layer located on the semiconductor substrate, the second connection layer being connected to the fifth P-type doped region 240, the first N-type doped region 220, the second P-type doped region 310 in the first-level second unit, and the third N-type doped region 330, respectively, and a material of the second connection layer being referred to a material of the first connection layer.
In this embodiment, the method further includes: and an ith-level connecting layer located on the semiconductor substrate, wherein the ith-level connecting layer is connected with the second N-type doped region 320 and the third P-type doped region 340 in the ith-level second unit and the second P-type doped region 310 and the third N-type doped region 330 in the (i + 1) -level second unit, and i is an integer greater than or equal to 1 and less than or equal to Q-1. The material of the ith-level connection layer is referenced to the material of the first connection layer.
In this embodiment, the method further includes: and a third connection layer on the semiconductor substrate, the third connection layer connecting the second N-type doped region 320 and the third P-type doped region 340 in the Q-th level second cell, the third connection layer being connected to a cathode potential. The material of the third connection layer is referenced to the material of the first connection layer.
In this embodiment, the method further includes: and a fourth connection layer on the semiconductor substrate 200, the fourth connection layer connecting the seventh P-type doped regions 400, and the material of the fourth connection layer being referred to the material of the first connection layer.
The SCR electrostatic protection structure of this embodiment includes a first current bleeding structure and a second current bleeding structure.
The first current leakage structure is a PNPN structure and comprises a first PNP transistor and a first NPN transistor, the first P-type doped region 210 serves as an emitter of the first PNP transistor, the first N-type well 201 at the bottom of the first P-type doped region 210 serves as a base of the first PNP transistor, the first P-type well 202 at the bottom of the first N-type doped region 220 serves as a collector of the first PNP transistor, the first N-type well 201 at the bottom of the first P-type doped region 210 serves as a collector of the first NPN transistor, the first P-type well 202 at the bottom of the first N-type doped region 220 serves as a base of the first NPN transistor, and the first N-type doped region 220 serves as an emitter of the first NPN transistor.
The second current leakage structure is a PNPN structure and includes a second PNP transistor and a second NPN transistor, the second P-type doped region 310 serves as an emitter of the second PNP transistor, the second N-type well 301 at the bottom of the second P-type doped region 310 serves as a base of the second PNP transistor, the second P-type well 302 at the bottom of the second N-type doped region 320 serves as a collector of the second PNP transistor, the second N-type well 301 at the bottom of the second P-type doped region 310 serves as a collector of the second NPN transistor, the second P-type well 302 at the bottom of the second N-type doped region 320 serves as a base of the second NPN transistor, and the second N-type doped region 320 serves as an emitter of the second NPN transistor. The second current leakage structures in the second units of each stage are connected in series.
The SCR electrostatic protection structure of this embodiment still includes resistance water conservancy diversion structure, and resistance water conservancy diversion structure includes: a third N-doped region 330, a second N-well 301, a cross-over doped group, a second P-well 302, and a third P-doped region 340.
The SCR electrostatic protection structure of this embodiment has a first current leakage path L1 and a second current leakage path L2, where the first current leakage path L1 corresponds to the first current leakage structure, and the second current leakage path L2 corresponds to the second current leakage structure. The resistive current guiding structure has a resistive current guiding path L3, the resistive current guiding path L3 includes: from the third N-well 330 to the second N-well, from the second N-well to a fourth N-doped region 360 across the doped group, from the fourth N-doped region 360 through the conductive structure 500 to the fourth P-doped region 350, from the fourth P-doped region 350 to the second P-well 302, from the second P-well 302 to the third P-doped region 340. The resistance diversion paths in the second units of each stage are connected in series.
In this embodiment, since the first current leakage path L1 and the second current leakage path L2 are superimposed in series, the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the sum of the holding voltage of the first current leakage structure and the holding voltage of the second current leakage structure, so that the holding voltage of the SCR electrostatic protection structure is increased. Because the holding voltage of the SCR electrostatic protection structure is improved, the range of the normal working voltage of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure.
In this embodiment, a trigger voltage is applied to the cathode and the anode, at an initial stage, the second current leakage path in the second unit is not conducted, the resistor-conducting structure in the second unit is conducted, the voltage drop across the second unit is small, most of the trigger voltage is applied to the first unit, so that the first current leakage path in the first unit is conducted, and thus the first current leakage path is triggered to perform leakage, and then, as the conduction of the first current leakage path triggers the conduction of the second current leakage path, the first current leakage path is triggered to perform leakage. Therefore, the trigger voltage required by the conduction of the first current leakage path in the SCR electrostatic protection structure to trigger the conduction of the second current leakage path is reduced.
Further, the concentration of P-type ions in the sixth P-type doped region 250 is much greater than that in the first P-type well 202, so that the breakdown voltage between the sixth P-type doped region 250 and the first N-type well 201 is lower, and the trigger voltage required for turning on the first current bleeding path L1 in the first cell is further reduced.
Accordingly, the present embodiment further provides an SCR electrostatic protection structure, please refer to fig. 3 and fig. 4 in combination, which includes:
a semiconductor substrate 200;
a first unit and a second unit separately located in the semiconductor substrate 200;
the first unit includes: a first N-type well 201 and a first P-type well 202 in the semiconductor substrate 200, the first P-type well 202 being located laterally to the first N-type well 201 and abutting the first N-type well 201 along the first direction X; a first P-type doped region 210 located on top in the first N-well 201; a first N-type doped region 220 located at the top in the first P-well 202;
the second unit includes: a second N-type well 301 and a second P-type well 302 in the semiconductor substrate 200, the second P-type well 302 being located laterally to the second N-type well 301 along the first direction X and adjoining the second N-type well 301; a second P-type doped region 310 and a third N-type doped region 330 located on top of and separated from each other in the second N-well 301; a second N-type doped region 320 and a third P-type doped region 340 located on top of the second P-type well 302 and separated from each other; bridging the doped group; the first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected for adjacent first and second cells;
the cross-over doping group comprises: a plurality of discrete fourth P-type doped regions 350 arranged along a second direction Y, each fourth P-type doped region 350 being located on top of a portion of the second N-well 301 and extending to top of a portion of the second P-well 302, the second direction Y being perpendicular to the first direction X; a fourth N-type doped region 360 located between adjacent fourth P-type doped regions 350 and adjacent to the fourth P-type doped regions 350, the fourth N-type doped region 360 being located on top of a portion of the second N-type well 301 and extending to top of a portion of the second P-type well 302;
a conductive structure 500 located on the semiconductor substrate 200, the conductive structure 500 electrically connecting the fourth N-type doped region 360 and the fourth P-type doped region 350.
The semiconductor substrate 200 has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
In this embodiment, taking the number of the second units as a plurality as an example, the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region 320 and the third P-type doped region 340 in the ith-level second unit are electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the (i + 1) -level second unit, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the Q-level second unit are connected with a cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the first-level second unit.
In other embodiments, the number of the second cells is one, and the second N-type doped region and the third P-type doped region are both connected to a cathode potential.
The first P-type doped region 210 and the fifth N-type doped region 230 are both connected to an anode potential.
The first unit further comprises: a fifth N-type doped region 230 located on the top of the first N-well 201, the fifth N-type doped region 230 and the first P-type doped region 210 being separated from each other, and the fifth N-type doped region 230 being electrically connected to the first P-type doped region 210.
The first unit further comprises: a fifth P-type doped region 240 located at the top of the first P-well 202, the fifth P-type doped region 240 and the first N-type doped region 220 are separated from each other, and the fifth P-type doped region 240 is electrically connected to the first N-type doped region 220.
The first unit further comprises: a first isolation group layer in the semiconductor substrate 200 between the first P-doped region 210 and the first N-doped region 220, the first isolation group layer being on top of a portion of the first N-well 201 and extending to top of a portion of the first P-well 202.
In this embodiment, the first isolation group layer includes a sixth P-type doped region 250 and first isolation insulation layers 510 respectively located at two sides of the sixth P-type doped region 250 along the first direction X, the sixth P-type doped region 250 is located at the top of a portion of the first N-well 201 and extends to the top of a portion of the first P-well 202, the first isolation insulation layer 510 at one side of the sixth P-type doped region 250 is located in the first N-well 201, and the first isolation insulation layer 510 at the other side of the sixth P-type doped region is located in the first P-well 202.
In other embodiments, the first isolation group layer is a single layer structure, and the material of the first isolation group layer includes silicon oxide.
The first unit further comprises: a first side isolation well 203 located in the semiconductor substrate 200, wherein the first side isolation well 203 is located at a side portion of the first P-type well 202 along the first direction X and is adjacent to the first P-type well 202, the first P-type well 202 is located between the first side isolation well 203 and the first N-type well 201, and the conductivity type of the first side isolation well is N-type; and the first bottom isolation well 204 is positioned at the bottom of the first P-type well 202 and is adjacent to the first P-type well 202, the first bottom isolation well 204 is also respectively connected with the bottom of the first N-type well 201 and the bottom of the first side isolation well 203, and the conductivity type of the first bottom isolation well is an N type.
The second unit further includes: a second side isolation well 303 located in the semiconductor substrate 200, wherein the second side isolation well 303 is located at a side portion of the second P-well 302 along the first direction X and is adjacent to the second P-well 302, the second P-well 302 is located between the second side isolation well 303 and the second N-well 301, and a conductivity type of the second side isolation well 303 is an N type; and a second bottom isolation well 304, the second bottom isolation well 304 is located at the bottom of the second P-well 302 and is adjacent to the second P-well 302, the second bottom isolation well 304 is further connected to the bottom of the second N-well 301 and the bottom of the second side isolation well 303, respectively, and the conductivity type of the second bottom isolation well 304 is N-type.
The SCR electrostatic protection structure further comprises: the seventh P-type doped region 400 is located at the top of a portion of the semiconductor substrate 200, the seventh P-type doped region 400 is located between the adjacent first unit and the adjacent second unit, and the seventh P-type doped region 400 is located at two sides of the second unit along the first direction, and each seventh P-type doped region 400 is grounded.
In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the conductive structure 500 is made of metal silicide.
In other embodiments, the conductive structure comprises: the first metal silicide layer is positioned on the surface of the fourth N-type doped region; the second metal silicide layer is positioned on the surface of the fourth P-type doped region, and the first metal silicide layer and the second metal silicide layer are mutually separated; and the metal connecting layers are positioned on the first metal silicide layer and the second metal silicide layer and are respectively connected with the first metal silicide layer and the second metal silicide layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. An SCR electrostatic protection structure, comprising:
a semiconductor substrate;
a first unit and a second unit which are separated and located in a semiconductor substrate;
the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located along a first direction at a side of the first N-type well and adjacent to the first N-type well; a first P-type doped region located on top of the first N-type well; a first N-type doped region located on top of the first P-type well;
the second unit includes: a second N-type well and a second P-type well in the semiconductor substrate, the second P-type well being located along a first direction at a side of the second N-type well and adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are positioned on the top of the second N-type well and are mutually separated; the second N-type doped region and the third P-type doped region are positioned on the top of the second P-type well and are separated from each other; bridging the doped group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;
the cross-over doping group comprises: a plurality of discrete fourth P-type doped regions arranged along a second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; a fourth N-type doped region located between adjacent fourth P-type doped regions and adjacent to the fourth P-type doped region, the fourth N-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well;
and the conductive structure is positioned on the semiconductor substrate and is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
2. The SCR electrostatic protection structure of claim 1, wherein the number of the second cells is one; and the second N-type doped region and the third P-type doped region are both connected with a cathode potential.
3. The SCR electrostatic protection structure of claim 1, wherein the number of the second cells is plural; the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region and the third P-type doped region in the ith-level second unit are electrically connected with the second P-type doped region and the third N-type doped region in the (i + 1) th-level second unit, i is an integer which is more than or equal to 1 and less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the Q-level second unit are connected with a cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region and the third N-type doped region in the first-level second unit.
4. The SCR electrostatic protection structure of claim 1, wherein said first P-type doped region is connected to an anode potential.
5. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: and the fifth N-type doped region is positioned at the top in the first N-type well, the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region.
6. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: and the fifth P-type doped region is positioned at the top in the first P-type well, the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
7. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
8. The SCR electrostatic protection structure of claim 7, wherein the first isolation group layer comprises a sixth P-type doped region and first isolation insulation layers respectively located at two sides of the sixth P-type doped region along the first direction, the sixth P-type doped region is located at the top of a portion of the first N-type well and extends to the top of a portion of the first P-type well, the first isolation insulation layer at one side of the sixth P-type doped region is located in the first N-type well, and the first isolation insulation layer at the other side of the sixth P-type doped region is located in the first P-type well.
9. The SCR electrostatic protection structure of claim 7, wherein the first isolation group layer is a single layer structure, and the material of the first isolation group layer comprises silicon oxide.
10. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: the first side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the first P-type well along the first direction and is adjacent to the first P-type well, the first P-type well is positioned between the first side isolation well and the first N-type well, and the conductivity type of the first side isolation well is N-type; and the first bottom isolation well is positioned at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is also respectively connected with the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is an N type.
11. The SCR electrostatic protection structure of claim 1, wherein the second unit further comprises: the second side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the second P-type well along the first direction and is adjacent to the second P-type well, is positioned between the second side isolation well and the second N-type well, and has an N-type conductivity type; and the second bottom isolation well is positioned at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is also respectively connected with the bottom of the second N-type well and the bottom of the second side isolation well, and the conductivity type of the second bottom isolation well is an N type.
12. The SCR electrostatic protection structure of claim 1, further comprising: and the seventh P-type doped region is positioned at the top part of the semiconductor substrate, is respectively positioned between the adjacent first unit and the second unit and on two sides of the second unit along the first direction, and is grounded.
13. The SCR electrostatic protection structure of claim 1, wherein the conductive structure is located on a surface of the fourth N-type doped region and extends to a surface of the fourth P-type doped region; the conductive structure is made of metal silicide.
14. The SCR electrostatic protection structure of claim 1, wherein said semiconductor substrate has substrate trap ions therein, said substrate trap ions being of a P-type conductivity type.
15. A method of forming an SCR electrostatic protection structure according to any one of claims 1 to 14, comprising:
providing a semiconductor substrate;
forming a first unit and a second unit which are separated in a semiconductor substrate;
the method of forming the first cell includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at a side portion of the first N-type well in a first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well;
the method of forming the second cell includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at a side portion of the second N-type well in the first direction; forming a second P-type doped region and a third N-type doped region which are separated from each other on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are separated from each other on the top in the second P-type well; forming a cross-over doping group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;
the method for forming the cross-over doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is vertical to the first direction; forming a fourth N-type doped region adjacent to the fourth P-type doped region between the adjacent fourth P-type doped regions, wherein the fourth N-type doped region is positioned on the top of part of the second N-type well and extends to the top of part of the second P-type well;
and forming a conductive structure on the semiconductor substrate, wherein the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
16. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: forming a fifth N-type doped region on the top of the first N-type well, wherein the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region; and forming a fifth P-type doped region on the top of the first P-type well, wherein the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
17. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: a first isolation group layer is formed in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located on top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.
18. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: before a first P-type doped region and a first N-type doped region are formed, a first side isolation well and a first bottom isolation well are formed in a semiconductor substrate, the first side isolation well is located on the side portion of the first P-type well along a first direction and is abutted to the first P-type well, the first P-type well is located between the first side isolation well and the first N-type well, the first bottom isolation well is located at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is further connected with the bottom of the first N-type well and the bottom of the first side isolation well respectively, and the conductivity types of the first side isolation well and the first bottom isolation well are both N-type.
19. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the second unit further comprises: before forming a second P-type doped region, a second N-type doped region, a third N-type doped region and a third P-type doped region, a second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located on the side portion of the second P-type well along the first direction and is abutted to the second P-type well, the second P-type well is located between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is further connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity types of the second side isolation well and the second bottom isolation well are both N-type.
20. The method for forming an SCR electrostatic protection structure of claim 15, further comprising: and forming seventh P-type doped regions on the top of part of the semiconductor substrate, wherein the seventh P-type doped regions are respectively positioned between the adjacent first unit and second unit and on two sides of the second unit along the first direction, and all the seventh P-type doped regions are grounded.
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