CN111785715B - Chip assembly, chip packaging structure and electronic equipment - Google Patents
Chip assembly, chip packaging structure and electronic equipment Download PDFInfo
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- CN111785715B CN111785715B CN202010700452.6A CN202010700452A CN111785715B CN 111785715 B CN111785715 B CN 111785715B CN 202010700452 A CN202010700452 A CN 202010700452A CN 111785715 B CN111785715 B CN 111785715B
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses a chip assembly, a chip packaging structure and electronic equipment, wherein the chip assembly comprises a first chip and a second chip, and the first chip is provided with a first surface and a second surface which are arranged in an opposite way; the second chip comprises a body part and a connecting part, and the connecting part is connected to the first surface of the first chip; the body part is connected with the connecting part, and a gap is formed between the body part and the first chip; the connecting part is provided with an electric connecting piece, and the body parts of the first chip and the second chip are connected and conducted with the electric connecting piece.
Description
Technical Field
The present invention relates to the field of semiconductor packaging technologies, and in particular, to a chip assembly, a chip packaging structure, and an electronic device.
Background
In recent years, with the rapid development of the electronic industry, electronic packaging is becoming an important direction for the development of the industry. As consumer electronics tend to be miniaturized, packaging technology becomes a hot topic. Flip Chip plays an important role in current Chip packaging, and Flip Chip packaging technology has many significant advantages over conventional wire bonding processes, such as superior electrical and thermal performance, high I/O pin count, reduced package size, etc. In order to advance to higher performance, Chip packaging has adopted the Flip Chip packaging method on a large scale, and shorter contact connection brings smaller parasitic capacitance and smaller packaging volume. In the prior art, two chips are bonded together by adopting silica gel, but the silica gel is soft, so that the situation that a gold Wire is not stable in a subsequent Wire Bonding process (Wire Bonding) is easy to occur, the situations that the Wire floats, the Wire is lapped, the gold Wire touches a shell and the like are caused, and the product performance is reduced or even loses efficacy.
In view of the above, a new technical solution is needed to solve the above technical problems.
Disclosure of Invention
An object of the present invention is to provide a chip assembly, a chip package structure and a new technical solution of an electronic device.
According to a first aspect of the present invention, there is provided a chip assembly comprising:
the first chip is provided with a first surface and a second surface which are arranged oppositely;
a second chip including a body portion and a connection portion connected to a first surface of the first chip; the body part is connected with the connecting part, and a gap is formed between the body part and the first chip; the connecting part is provided with an electric connecting piece, and the body parts of the first chip and the second chip are connected and conducted with the electric connecting piece.
Optionally, the connecting portion is provided in two, and the body portion is connected between the two connecting portions.
Optionally, the first chip and the second chip are both made of silicon-based materials. Optionally, the electrical connector is a conductive through silicon via opened on the connection portion.
Optionally, the first chip and the second chip are integrally formed.
Optionally, the first chip is an IC chip, and the second chip is an MEMS chip.
According to another aspect of the present invention, there is provided a chip packaging structure, including the chip assembly, the PCB board and the housing as described above; the PCB board with the shell is connected and encloses and closes and form and hold the chamber, the chip subassembly is located hold the intracavity, the chip subassembly with PCB board electric connection.
Optionally, the second surface of the first chip is electrically connected to the PCB board through a solder ball.
According to still another aspect of the present invention, there is provided an electronic apparatus having the chip packaging structure as described above provided therein.
In the chip assembly provided by the embodiment of the invention, the body parts of the first chip and the second chip are connected through the connecting part of the second chip, the connecting part of the second chip is provided with the electric connecting piece, and the electric connection between the first chip and the second chip is realized through the electric connecting piece. According to the chip assembly provided by the embodiment of the invention, the use of silica gel is omitted, so that the condition that a gold wire is unstable due to the use of silica gel in a subsequent wire bonding process is avoided.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a chip assembly according to the present invention;
fig. 2 is a schematic structural diagram of a chip package structure according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, according to an embodiment of the present invention, a chip assembly is provided, the chip assembly including a first chip 11, the first chip 11 having a first surface and a second surface opposite to each other; the chip assembly further includes a second chip 12, the second chip 12 includes a body portion 121 and a connecting portion 122, and the connecting portion 122 is connected to the first surface of the first chip 11; the body portion 121 is connected to the connecting portion 122, and a gap is formed between the body portion 121 and the first chip 11; the connecting portion 122 is provided with an electrical connector, and the body portions 121 of the first chip 11 and the second chip 12 are both connected and conducted with the electrical connector.
In the chip assembly provided in the embodiment of the invention, the first chip 11 and the second chip 12 are not bonded by using silicone, but the second chip 12 is provided with the connecting portion 122, the connecting portion 122 is connected to the first surface of the first chip 11, the connecting portion 122 functions as a bridge, the connecting portion 122 connects the body portions 121 of the first chip 11 and the second chip 12, and the connecting portion 122 is provided with an electrical connector, so that the first chip 11 is electrically connected to the second chip 12 through the electrical connector. According to the chip assembly provided by the embodiment of the invention, the use of silica gel is omitted, so that the condition that a gold wire is not stable in a subsequent wire bonding process due to the use of silica gel is avoided.
Referring to fig. 1, in one embodiment, the connecting portion 122 is provided in two, and the body portion 121 is connected between the two connecting portions 122.
In the present embodiment, two connecting portions 122 are oppositely disposed on the main body portion 121, both the connecting portions 122 are connected to the first surface of the first chip 11, and the main body portion 121 of the second chip 12 is connected between the two connecting portions 122, so that the connection is more stable and reliable.
In one embodiment, the first chip 11 and the second chip 12 are both silicon-based materials. Further, in one embodiment, the electrical connection is a conductive through silicon via opened on the connection portion 122.
In this embodiment, the first chip 11 and the second chip 12 are both made of the same silicon-based material, a through silicon via array is prepared on the connection portion 122 of the silicon-based material as a conductive connection member, and further, a conductive metal is filled in the through silicon via, where the conductive metal is generally copper, and may also be other metals such as aluminum, tungsten, titanium, and the like.
In one embodiment, the first chip 11 and the second chip 12 are integrally formed.
In the embodiment where the first chip 11 and the second chip 12 are both made of silicon-based materials, further, the first chip 11 and the second chip 12 are integrally formed; specifically, alternatively, a bulk silicon-based material may be used, and the body portion 121 of the first chip 11 and the second chip 12 and the connection portion 122 of the second chip 12 may be formed by etching.
In one embodiment, the first chip 11 is an IC chip and the second chip 12 is a MEMS chip.
Referring to fig. 2, according to another embodiment of the present invention, there is provided a chip packaging structure including the chip assembly 1, the PCB board 2 and the housing 3 as described above; PCB board 2 with shell 3 is connected and encloses to close and form one and hold the chamber, chip subassembly 1 is located hold the intracavity, chip subassembly 1 with PCB board 2 electricity is connected.
Specifically, optionally, the housing 3 is a metal housing, and the metal housing has the advantage of being firm and stable. For example, the housing 3 may be a copper housing with a middle portion and gold plating treatment is performed on inner and outer surface layers of the copper housing, so that the metal housing has excellent electromagnetic shielding effect to prevent the chip assembly 1 therein from being interfered by external electromagnetic interference. Of course, the housing 3 may also be made of plastic, which has a less excellent electromagnetic shielding effect than a metal housing, but the plastic housing has a simpler manufacturing process, lighter weight and lower cost.
Referring to fig. 2, in one embodiment, the second surface of the first chip 11 and the PCB board 2 are electrically connected through solder balls 4.
Generally, the chip closest to the PCB is connected and conducted to the pad of the PCB by using a solder ball, and the chip farther from the PCB is connected and conducted to the pad of the PCB by using a gold wire. In the chip packaging structure, a plurality of pads are arranged on a PCB (printed circuit board) 2 and are used for being electrically connected with a first chip 11 through solder balls 4, and the solder balls 4 are approximately spherical, so that the pads connected with the solder balls are round, and the connection with the solder balls is convenient; in the chip package structure provided in the embodiment of the present invention, the body portion 121 of the second chip 12 is electrically connected to the first chip 11 through the electrical connector disposed on the connecting portion 122 of the second chip 12, and the first chip 11 is electrically connected to the PCB 2 through the solder ball 4, so that the second chip 12 does not need to be electrically connected to the PCB 2 through a gold wire, and the radian of the gold wire occupies a certain space in height, so that the height of the whole chip package structure can be reduced after the gold wire is omitted, which is helpful for further reducing the size of the product.
According to still another embodiment of the present invention, there is provided an electronic apparatus in which the chip packaging structure as described above is provided. The electronic device can be a barometer, an intelligent wearable device, a portable mobile device and the like.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (6)
1. A chip assembly, comprising:
the chip comprises a first chip (11), wherein the first chip (11) is provided with a first surface and a second surface which are arranged oppositely;
a second chip (12), wherein the second chip (12) comprises a body part (121) and a connecting part (122), and the connecting part (122) is connected to the first surface of the first chip (11); the body part (121) is connected with the connecting part (122), and a gap is formed between the body part (121) and the first chip (11); the connecting part (122) is provided with an electric connecting piece, and the body parts (121) of the first chip (11) and the second chip (12) are connected and conducted with the electric connecting piece;
the number of the connecting parts (122) is two, and the body part (121) is connected between the two connecting parts (122);
the first chip (11) and the second chip (12) are both made of silicon-based materials, and the electric connection piece is a conductive silicon through hole array arranged on the connection part (122).
2. Chip assembly according to claim 1, characterized in that the first chip (11) and the second chip (12) are made in one piece.
3. The chip assembly according to any of claims 1-2, characterized in that the first chip (11) is an IC chip and the second chip (12) is a MEMS chip.
4. A chip packaging structure, characterized in that the chip packaging structure comprises a chip assembly (1) according to any one of claims 1-3, a PCB board (2) and a housing (3); PCB board (2) with shell (3) are connected and are enclosed and close and form one and hold the chamber, chip subassembly (1) is located hold the intracavity, chip subassembly (1) with PCB board (2) electricity is connected.
5. The chip package structure according to claim 4, wherein the second surface of the first chip (11) is electrically connected to the PCB (2) via solder balls (4).
6. An electronic device, wherein the chip packaging structure according to claim 5 is provided in the electronic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010700452.6A CN111785715B (en) | 2020-07-20 | 2020-07-20 | Chip assembly, chip packaging structure and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010700452.6A CN111785715B (en) | 2020-07-20 | 2020-07-20 | Chip assembly, chip packaging structure and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111785715A CN111785715A (en) | 2020-10-16 |
| CN111785715B true CN111785715B (en) | 2022-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010700452.6A Active CN111785715B (en) | 2020-07-20 | 2020-07-20 | Chip assembly, chip packaging structure and electronic equipment |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5388503B2 (en) * | 2007-08-24 | 2014-01-15 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
| KR101143635B1 (en) * | 2010-09-13 | 2012-05-09 | 에스케이하이닉스 주식회사 | Stacked package and method for manufacturing the same |
| KR20120053332A (en) * | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
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