CN111782562B - Data transmission method, DMA controller, NPU chip and computer equipment - Google Patents
Data transmission method, DMA controller, NPU chip and computer equipment Download PDFInfo
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Abstract
The embodiment of the application discloses a data transmission method, a DMA controller, an NPU chip and computer equipment, and belongs to the technical field of chips. The method comprises the following steps: acquiring a first data transmission instruction, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter; sending a first data reading command to the bus according to the first reading address parameter; responding to the received first data returned by the bus, and writing the first data into the destination terminal according to the first write address parameter; and in response to the fact that the first data returned by the bus is not received, writing the first interpolation data into the destination according to the first interpolation address parameter. Compared with the data interpolation after the data transmission is completed, the data interpolation function is integrated to the DMA controller, so that the data interpolation is performed by utilizing the delay time period of sending the command to the data return, the delay time of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a data transmission method, a DMA controller, an NPU chip and computer equipment.
Background
The direct memory access (Direct Memory Access, DMA) controller is a component in a computer system for enabling data transfer that can reduce the performance impact of data transfer on the central processing unit (Central Processing Unit, CPU).
When the DMA controller transmits data, firstly, the control right of the system bus is acquired from the CPU, and then the data is read from the source data address through the system bus, so that the read data is written into the destination address. For example, when it is desired to write a portion of the data in the external memory to the neural network processor (Neural-network Processing Unit, NPU), the DMA controller reads the data from the external memory via the system bus according to the source data address and writes the read data to the internal buffer of the NPU according to the destination address.
Disclosure of Invention
The embodiment of the application provides a data transmission method, a DMA controller, an NPU chip and computer equipment. The technical scheme comprises the following steps:
In one aspect, an embodiment of the present application provides a data transmission method, where the method is used for a direct memory access DMA controller, and the method includes:
Acquiring a first data transmission instruction, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter, the first read address parameter is used for indicating the address of first data in a source end, the first write address parameter is used for indicating the address of the first data in a destination end, and the first interpolation address parameter is used for indicating the address of first interpolation data in the destination end;
sending a first data reading command to a bus according to the first reading address parameter, wherein the bus is used for reading the first data from the source terminal according to the first data reading command;
responding to the received first data returned by the bus, and writing the first data into the destination terminal according to the first write address parameter;
And responding to the first data which is not received and returned by the bus, and writing the first interpolation data into the destination terminal according to the first interpolation address parameter.
In another aspect, an embodiment of the present application provides a DMA controller, including: a command sending module and a data writing module;
the command sending module is configured to obtain a first data transmission command, where the first data transmission command includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, where the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of the first data in a destination end, and the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end;
The command sending module is used for sending a first data reading command to a bus according to the first reading address parameter, and the bus is used for reading the first data from the source end according to the first data reading command;
The data writing module is used for writing the first data to the destination terminal according to the first write address parameter when the first data returned by the bus is received;
and the data writing module is further used for writing the first interpolation data to the destination terminal according to the first interpolation address parameter when the first data returned by the bus is not received.
In another aspect, an embodiment of the present application provides an NPU chip, where a DMA controller as described in the above aspect is disposed in the NPU chip.
On the other hand, the embodiment of the application provides computer equipment, which comprises a CPU chip, an NPU chip and a memory, wherein the CPU chip, the NPU chip and the memory are connected through a bus; the NPU chip includes the DMA controller as described in the above aspect.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
In the embodiment of the application, when the DMA controller performs data transmission and interpolation requirements exist for the transmitted data, the DMA controller sends a data reading command to the bus, instructs the bus to read the data from the source end, writes the interpolation data into the destination end according to the interpolation address in the process of waiting for the bus to return to read the data, and preferentially writes the read data into the destination end when receiving the data returned by the bus; compared with the data interpolation after the data transmission is completed, the data interpolation function is integrated to the DMA controller, so that the data interpolation is performed by utilizing the delay time period of sending the command to the data return, the delay time of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
Drawings
FIG. 1 is a schematic diagram of a related art DMA controller performing a data transfer process;
Fig. 2 is a flowchart illustrating a method of data transmission according to an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of a three-dimensional data block provided by an exemplary embodiment;
FIG. 4 is a schematic diagram of the three-dimensional data block storage of FIG. 3;
Fig. 5 is a flowchart illustrating a data transmission method according to another exemplary embodiment of the present application;
fig. 6 is a flowchart illustrating a data transmission method according to another exemplary embodiment of the present application;
FIG. 7 illustrates a schematic diagram of a DMA controller provided by an exemplary embodiment of the present application;
FIG. 8 is a schematic diagram illustrating the structure of a DMA controller according to another exemplary embodiment of the present application;
fig. 9 is a schematic diagram showing a structure of a computer device according to an exemplary embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the related art, the DMA controller only has a data transfer (or referred to as data movement) function, that is, after the DMA controller transfers data from a source terminal to a destination terminal, further processing of the data needs to be performed by the destination terminal. In one possible scenario, as shown in fig. 1, when data in the memory 11 needs to be transferred to the NPU chip 12, the CPU chip 13 sends a data transfer instruction to the DMA controller 14, and the DMA controller 14 reads the data from the memory 11 through the bus 15 according to the data transfer instruction, and writes the read data into an internal buffer of the NPU chip 12, so that the NPU chip 12 performs an operation on the written data.
Before the NPU chip processes the data, interpolation processing is often required on the data. For example, before the NPU chip convolves the written image data, data padding (padding) is required for the image data, and the data padding operation is required to be performed by the NPU chip after the data transmission is completed.
However, when the DMA controller performs data transmission through the bus, there is a bus delay and a data reading delay, so that the above-mentioned method of performing transmission before interpolation will cause a higher delay, which affects the working efficiency of the destination (such as NPU chip).
In order to reduce delay and improve the working efficiency of the destination end, the DMA controller provided by the embodiment of the application has a data interpolation function in addition to a data transmission function. When the DMA controller is used for data transmission, if the data returned by the bus is not received in the process of reading the data from the destination terminal through the bus, the DMA controller writes the interpolation data into the destination terminal according to the interpolation address, and if the data returned by the bus is received, the DMA controller writes the read data into the destination terminal according to the write data address. The bus delay and the data reading delay period are utilized to conduct data interpolation, rather than conducting data interpolation after completing data transmission, the total time consumption of data transmission and data interpolation can be reduced, and therefore the working efficiency of a destination terminal is improved; in addition, as the DMA controller completes the data interpolation, the destination terminal can omit the data interpolation operation, thereby reducing the complexity of the operation executed by the destination terminal.
Referring to fig. 2, a method flowchart of a data transmission method according to an exemplary embodiment of the present application is shown. This embodiment will be described by taking the method for a DMA controller as an example, and the method may include the following steps.
Step 201, a first data transmission instruction is obtained, where the first data transmission instruction includes a first read address parameter, a first write address parameter and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of first data in a destination end, and the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end.
In some embodiments, the DMA controller receives a data transfer instruction sent by the CPU chip and buffers the data transfer instruction in the instruction storage module, and correspondingly, the DMA controller reads the first data transfer instruction from the instruction storage module.
In the embodiment of the present application, the first data transmission instruction is used to indicate the read address of the first data at the source end and the write address of the first data at the destination end, and further includes the interpolation address of the first data corresponding to the interpolation data at the destination end, where the interpolation data is used to insert the interpolation data into the first data written in the destination end.
In one possible embodiment, the first read address parameter, the first write address parameter, and the first interpolation address parameter each include a data start address and an address offset, so as to reduce the instruction length of the first data transfer instruction.
Step 202, a first data read command is sent to a bus according to a first read address parameter, and the bus is used for reading the first data from a source terminal according to the first data read command.
After the first data transmission instruction is obtained, the DMA controller obtains the control right of the bus, further determines the read address of the first data by the first read address parameter, and further sends a first data read command containing the read address to the bus to instruct the bus to read the first data from the source terminal.
In one possible implementation, before the DMA controller sends the first data read command to the bus, the first data read command is converted into a bus read command interface form, ensuring that the bus is able to recognize the command.
In step 203, in response to receiving the first data returned by the bus, the first data is written into the destination according to the first write address parameter.
When the first data returned by the bus is received, the DMA controller preferentially writes the first data returned by the bus into the destination in order to avoid the first data from blocking the bus. The DMA controller determines the write address of the first data in the destination according to the first write address parameter, and then completes the writing of the first data according to the write address.
And step 204, in response to not receiving the first data returned by the bus, writing the first interpolation data into the destination according to the first interpolation address parameter.
When the first data returned by the bus is not received (due to bus delay or data reading delay and the like), the DMA controller determines an interpolation address of the interpolation data in the destination according to the first interpolation address parameter while waiting for the first data, and writes the interpolation data into the interpolation address, namely, performs data interpolation by utilizing the bus and the data reading delay time.
It should be noted that, when the first data returned by the bus is received during the interpolation process, the DMA controller stops the data interpolation operation and writes the returned first data into the destination, that is, the writing priority of the first data is higher than the writing priority of the interpolation data.
In one possible application scenario, when image data in the memory needs to be transferred to the NPU chip, the CPU chip sends a data transfer instruction (indicating a data read address, a data write address, and a data interpolation address) to the DMA controller, and the DMA controller reads the image data from the memory through the bus according to the data transfer instruction. In the process of waiting for the bus to return the image data, the DMA control writes interpolation data into the NPU chip when the image data returned by the bus is not received, and writes the image data into the NPU chip when the image data returned by the bus is received. By carrying out data interpolation in the data transmission process, the time for the NPU chip to acquire image data and complete data interpolation is shortened, and the efficiency of the subsequent convolution operation of the NPU chip is improved.
In summary, in the embodiment of the present application, when the DMA controller performs data transmission and interpolation requirements exist for the transmitted data, the DMA controller sends a data read command to the bus, instructs the bus to read data from the source, writes the interpolated data into the destination according to the interpolation address in the process of waiting for the bus to return the read data, and preferentially writes the read data into the destination when receiving the data returned from the bus; compared with the data interpolation after the data transmission is completed, the data interpolation function is integrated to the DMA controller, so that the data interpolation is performed by utilizing the delay time period of sending the command to the data return, the delay time of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
In one possible embodiment, the first data to be transferred consists of several data lines, and the DMA controller generates a corresponding first data read command for each data line and sends it to the bus. Optionally, the step 202 includes the following steps.
Step 202A, determining a read data address corresponding to at least one data line in the first data according to the first read address parameter.
In some embodiments, the first read address parameter includes a data start address of a first data line in the first data and an address offset of other data lines relative to the first data line, and the DMA controller determines the read data address of the first data line based on the data start address and the address offset, and determines the read data addresses of the other data lines based on the data start address and the address offset.
In one possible embodiment, the first data is a three-dimensional data block, i.e. the first data is formed by stacking several three-dimensional data lines. As shown in fig. 3, the first data is a three-dimensional data block formed by stacking 6×5 data lines 31 (hatched filled in), and the corresponding three-dimensional data block is stored in the manner shown in fig. 4.
As shown in fig. 4, the data start address (or called the BASE address) of the first data line in the three-dimensional data block is base_addr; d1_num is the data length (e.g., number of bytes) of the data line in the first dimension (D1); d2_num is the number of data lines in the second dimension (D2); d2_offset is the address OFFSET between adjacent rows of data in the second dimension; d3_num is the number of data lines on the third dimension (D3); d3_offset is the address OFFSET between adjacent data lines in the third dimension (i.e., the address OFFSET between two-dimensional data planes).
In some embodiments, the first read address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data lines in a two-dimensional direction, a three-dimensional address offset, and a number of data lines in a three-dimensional direction. Accordingly, in determining the read data address of each data row in the three-dimensional data block, the following manner may be adopted.
1. And determining the read data address of the data row in the first dimension according to the data start address in the first read address parameter.
Illustratively, as shown in FIG. 4, the DMA controller may determine the read data address of the first data line in the first dimension based on the data start address contained in the first read address parameter.
2. And determining the read data address of the data row in the second dimension according to the data start address and the two-dimensional address offset in the first read address parameter, wherein the two-dimensional address offset is the address offset between adjacent data rows in the second dimension.
When the read data address of each data line in the second dimension is determined, the DMA controller calculates the address offset of the data starting address in the second dimension according to the two-dimensional address offset, and calculates the read data address of the data line.
In one possible implementation, the read data address of the ith data row in the second dimension is: BASE_ADDR+ (i-1) x D2_OFFSET, 1.ltoreq.i.ltoreq.D2_NUM.
3. And determining the read data address of the data row in the third dimension according to the data starting address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
When the read data address of each data line in the third dimension is determined, the DMA controller calculates the address offset of the data starting address in the third dimension according to the three-dimensional address offset, and calculates the read data address of the data line.
In one possible implementation, the j-th data plane in the third dimension, and the read data address of the k-th data line is: BASE_ADDR+ (j-1) x D3_OFFSET+ (k-1) x D2_OFFSET, 1.ltoreq.j.ltoreq.D3_NUM, 1.ltoreq.k.ltoreq.D2_NUM.
Step 202B, at least one first data read command is sent to the bus according to the read data address and the data length of the data line.
After determining the read data address corresponding to each data line in each first data, the DMA controller further generates a first data read command corresponding to each data line according to the read data address and the data length of the data line, and sends each first data read command to the bus one by one. After the bus receives the first data reading command, the data is read from the data reading address, and the length of the read data is the data length in the command.
In one illustrative example, as shown in FIG. 3, since the first data consists of 30 data lines, the DMA controller generates 30 first data read commands and sends them to the bus one by one.
In this embodiment, the DMA controller determines the read data address of each data line according to the data start address in the first read address parameter and the address offset of the data line in each dimension, so as to generate a corresponding data read command according to the read data address and the data length, and reduce the data volume of the data transmission command on the premise of ensuring the data read accuracy.
In order to further improve the bandwidth and transmission performance of the DMA controller, in one possible implementation manner, the destination end is provided with n buffers, and the DMA controller is correspondingly provided with an instruction storage module with depth of n, so that the DMA controller can write the read data and the interpolation data into the n buffers according to the data transmission instruction in the instruction storage module, thereby achieving the effect of pipelining the data. The following description uses exemplary embodiments.
Referring to fig. 5, a method flowchart of a data transmission method according to another exemplary embodiment of the present application is shown. This embodiment will be described by taking the method for a DMA controller as an example, and the method may include the following steps.
Step 501, a first data transmission instruction is obtained from the instruction storage module, where the first data transmission instruction includes a first read address parameter, a first write address parameter, and a first interpolation address parameter.
In one possible implementation, the DMA controller is provided with an instruction storage module for storing data transmission instructions issued by the CPU chip. The instruction storage module adopts a first-in first-out (First Input First Output, FIFO) design, and the depth is related to the number of the buffers in the destination end.
For receiving the data transmission instruction, the DMA controller obtains the first data transmission instruction from the instruction storage module according to the FIFO principle.
Step 502, a first data read command is sent to a bus according to the first read address parameter, and the bus is used for reading first data from a source terminal according to the first data read command.
The process of generating and sending the first data read command by the DMA controller may refer to the above steps 202A and 202B, and this embodiment is not described herein again.
Step 503, in response to receiving the first data returned by the bus, determining a write data address of the first data in the first buffer according to the first write address parameter; and writing the first data into the first buffer according to the write data address.
Since the destination end is provided with n buffers, the DMA controller needs to write the data returned by the bus into the corresponding buffer. In one possible implementation manner, the first data transmission instruction further includes a buffer identifier, and the DMA controller determines a buffer to which the first data is to be written according to the buffer identifier.
In some embodiments, the first write address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data rows in a two-dimensional direction, a three-dimensional address offset, and a number of data rows in a three-dimensional direction. Correspondingly, the DMA controller calculates the write data address of each data row according to the data, where the calculating manner of the write data address may refer to the calculating manner of the read data address, and this embodiment is not described herein again.
Step 504, determining an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter in response to not receiving the first data returned by the bus; and writing the first interpolation data into the first buffer according to the interpolation address.
In some embodiments, the first interpolation address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data lines in a two-dimensional direction, a three-dimensional address offset, and a number of data lines in a three-dimensional direction of the interpolation data. Accordingly, the DMA controller calculates the interpolation address of each interpolation data line according to the data, where the calculation mode of the interpolation address may refer to the calculation mode of the read data address, and this embodiment is not described herein again.
Illustratively, as shown in fig. 3, the DMA controller may interpolate the three-dimensional data block in three directions D1, D2, and D3. Wherein the DMA controller determines the interpolation address of each interpolation data line based on the data start address of the first interpolation data line 32 in the first interpolation address parameter and the address offset of the other interpolation data lines relative to the first interpolation data line 32.
For the manner of obtaining the interpolation data, in one possible implementation manner, the destination register stores the interpolation data, and when the DMA controller performs data interpolation, the DMA controller reads the interpolation data from the destination register. For example, the DMA controller reads interpolation data of 0 from the register of the NPU chip.
In other possible embodiments, the interpolation data may also be indicated by the CPU chip in the data transmission instruction, which is not described in detail herein.
Step 505, a second data transmission instruction is obtained from the instruction storage module, where the second data transmission instruction includes a second read address parameter, a second write address parameter, and a second interpolation address parameter.
In one possible implementation manner, after the DMA controller sends the first data read command to the bus, it detects whether there is a second data transmission command in the command storage module, if so, it further obtains the second data transmission command, so as to write data and interpolation data into the second buffer of the destination according to the second data transmission command, and implement parallel writing of the first data and the second data.
The parameters included in the second data transmission instruction are similar to those of the first data transmission instruction, and the embodiment is not described herein again.
In step 506, a second data read command is sent to the bus according to the second read address parameter, and the bus is used for reading the second data from the source terminal according to the second data read command.
The DMA controller in the embodiment of the present application has a synchronous writing function, that is, when the first data is not completely written into the first buffer, if the second data returned by the bus is received, the DMA controller can write the second data into the second buffer, that is, when the writing operation of the first buffer is not completed, the writing operations of the first buffer and the second buffer are synchronously executed, thereby improving the transmission bandwidth of the destination terminal and the external data, and achieving the effect of pipelined reading and writing.
The process of sending the second data read command to the bus by the DMA controller may refer to the process of sending the first data read command to the bus, which is not described herein.
In step 507, in response to receiving the second data returned by the bus, the second data is written into the second buffer according to the second write address parameter.
Similarly to writing the first data into the first buffer, when receiving the second data returned from the bus, the DMA controller writes the second data into the second buffer, avoiding the returned data from blocking the bus.
And step 508, in response to not receiving the second data returned by the bus, writing the second interpolation data into the second buffer according to the second interpolation address parameter.
Similarly to writing the first interpolation data into the first buffer, when the second data returned by the bus is not received, the DMA controller writes the second interpolation data into the second buffer, reducing the influence caused by the bus delay and the read data delay.
In one possible implementation, when the first data is written and the first interpolation data is written, the DMA controller releases the first data transmission instruction in the instruction storage module so as to store the subsequent data transmission instruction sent by the CPU chip, and then performs subsequent data transmission and data interpolation operations.
In this embodiment, when at least two buffers are set at the destination end and an instruction storage module capable of accommodating at least two instructions is set in the DMA controller, the DMA controller is enabled to synchronously execute reading operations of different data when receiving multiple data transmission instructions, so that the read data is written into the corresponding buffers, and data interpolation operation is performed in the process of writing the data, thereby improving transmission bandwidths of the destination end and external data, further improving efficiency of subsequent data processing of the destination end, and improving working efficiency and performance of the destination end.
In an exemplary example, taking a source end as a memory, a destination end as an NPU chip, two buffers are provided in the NPU chip, and the depth of the instruction storage module in the DMA controller is 2, a process of transferring data from the DMA controller to the NPU chip is shown in fig. 6.
Step 601, a data transmission instruction sent by the CPU chip is received and stored in an instruction storage module.
Step 602, executing a first data transmission instruction in an instruction storage module.
In step 603, a first read data address is calculated.
In step 604, a first write data address is calculated.
Step 605, a first interpolation address is calculated.
Step 606, a first data read command is sent to the bus according to the first read data address.
In step 607, whether the first data returned by the bus is received.
In step 608, when the first data returned by the bus is received, the first data is written into the first buffer of the NPU chip.
In step 609, when the first data returned by the bus is not received, the first interpolation data is written into the first buffer of the NPU chip.
Step 610, if all the first data writing operations are completed, step 612 is executed, and if not completed, step 607 is executed.
Step 611, if the writing operation of all the first interpolation data is completed, step 612 is executed, and if not completed, step 607 is executed.
Step 612, if the writing operation of the first data and the first interpolation data is completed, releasing the first data transmission instruction.
In step 613, when the first data read command is sent, a second data transfer instruction in the memory module is executed.
At step 614, a second read data address is calculated.
Step 615, calculate a second write data address.
In step 616, a second interpolation address is calculated.
Step 617 sends a second data read command to the bus according to the second read data address.
Step 618, whether the second data returned by the bus is received.
Step 619, when second data returned by the bus is received, the second data is written into a second buffer of the NPU chip.
And step 620, when the second data returned by the bus is not received, writing the second interpolation data into a second buffer of the NPU chip.
Step 621, if all the second data writing operations are completed, step 618 is executed, and if not completed, step 623 is executed.
Step 622, if all the writing operations of the second interpolation data are completed, step 618 is executed, and if not completed, step 623 is executed.
In step 623, if the writing operation of the second data and the second interpolation data is completed, the second data transmission instruction is released.
In step 624, when the second data read command is sent, it is detected whether the first data transfer instruction has been released.
If the instruction is released, the next data transfer instruction in the instruction storage module is executed 625.
Referring to fig. 7, a schematic diagram of a DMA controller according to an exemplary embodiment of the present application is shown. The DMA controller includes: a command sending module 701 and a data writing module 702.
The command sending module 701 is configured to obtain a first data transmission instruction, where the first data transmission instruction includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of first data in a destination end, and the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end.
The command sending module 701 is configured to send a first data read command to a bus according to a first read address parameter, where the bus is configured to read the first data from a source according to the first data read command.
The data writing module 702 is configured to, when receiving first data returned by the bus, write the first data to the destination according to the first write address parameter;
the data writing module 702 is further configured to write, when the first data returned by the bus is not received, the first interpolation data to the destination according to the first interpolation address parameter.
In a possible implementation manner, the command sending module 701 is configured to determine, according to the first read address parameter, a read data address corresponding to at least one data line in the first data; and sending at least one first data read command to the bus according to the read data address and the data length of the data line.
In one possible implementation, the first data is a three-dimensional data block;
The command sending module 701 is further configured to:
determining a read data address of the data row in a first dimension according to a data start address in the first read address parameter;
Determining the read data address of the data row in the second dimension according to the data start address and the two-dimensional address offset in the first read address parameter, wherein the two-dimensional address offset is the address offset between adjacent data rows in the second dimension;
and determining the read data address of the data row in the third dimension according to the data starting address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
In a possible implementation manner, the destination end is provided with n buffers, and the DMA controller includes an instruction storage module with depth of n, where n is an integer greater than or equal to 2;
a command sending module 701, configured to obtain a first data transmission command from the command storage module;
the data writing module 702 is configured to determine, when first data returned by the bus is received, a write data address of the first data in the first buffer according to the first write address parameter; writing first data into a first buffer according to the write data address;
The data writing module 702 is further configured to determine, when the first data returned by the bus is not received, an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter; and writing the first interpolation data into the first buffer according to the interpolation address.
In a possible implementation manner, the command sending module 701 is further configured to obtain a second data transmission instruction from the instruction storage module, where the second data transmission instruction includes a second read address parameter, a second write address parameter, and a second interpolation address parameter; sending a second data reading command to a bus according to the second reading address parameter, wherein the bus is used for reading second data from a source end according to the second data reading command;
the data writing module 702 is further configured to, when receiving second data returned by the bus, write the second data into the second buffer according to the second write address parameter;
The data writing module 702 is further configured to, when second data returned by the bus is not received, write the second interpolation data into the second buffer according to the second interpolation address parameter;
When the write operation of the first buffer is completed, the write operations of the first buffer and the second buffer are synchronously executed.
In one possible implementation, the instruction storage module is further configured to release the first data transmission instruction when the writing of the first data is completed and the writing of the first interpolation data is completed.
The functional implementation process of each module in the DMA controller may refer to the above method embodiment, and this embodiment is not described herein.
In one illustrative example, as shown in fig. 8, a DMA controller 800 includes: an instruction storage module 801, a read address generation module 802, a read command processing module 803, an interpolation address generation module 804, a write address generation module 805, a write command processing module 806, and a data buffer module 807. The write command processing module 806 corresponds to the data writing module 702 of the DMA controller in fig. 7.
The instruction storage module 801 is configured to store a data transmission instruction issued by the CPU chip, and the instruction storage module 801 stores the instruction in a FIFO manner.
The read address generating module 802 is configured to generate an address of data to be transmitted in the external data memory 820 according to a read address parameter included in the instruction storing module 801.
The read command processing module 803 is configured to send a read command to the bus 830 according to the read address generated by the read address generating module 802, so that the bus 830 reads data to be transmitted from the external data memory 820. The read address generation module 802 and the read command processing module 803 correspond to the command transmission module of the DMA controller in fig. 7.
The interpolation address generating module 804 is configured to generate an interpolation address of interpolation data in the data buffer according to the interpolation address parameter included in the instruction storage module 801.
The write address generating module 805 is configured to generate a data write address of data to be transferred in the data buffer according to a write address parameter included in the instruction storing module 801.
The data buffer module 807 is configured to buffer data to be transmitted returned by the bus 830, and provide control signals for writing data and data interpolation to the write command processing module 806.
The write command processing module 806 may process at least two write instructions simultaneously. When the data buffer module 807 is empty, that is, when the data returned by the bus is not received, the write command processing module 806 writes the interpolated data into the data buffer according to the interpolated address generated by the interpolated address generating module 804; when the data buffer module 807 is not empty, that is, when data returned from the bus is received, the write command processing module 806 writes the data to be transferred into the data buffer according to the write address generated by the write address generating module 805.
When the destination is provided with a plurality of data buffers, as shown in fig. 8, the destination is provided with a data buffer 1 and a data buffer 2, and the write command processing module 806 uses a pipeline operation mode to synchronously write data into the data buffer 1 and the data buffer 2 and perform data interpolation.
The application also provides an NPU chip, and the NPU chip is internally provided with the DMA controller in the embodiment. When the CPU chip needs to write data into the NPU chip, a data transmission instruction is sent to a DMA controller in the NPU chip, the DMA controller reads the data according to the instruction, the read data is written into a buffer of the NPU chip, and data interpolation is carried out by utilizing a bus and data reading delay.
Referring to fig. 9, a schematic diagram of a computer device according to an exemplary embodiment of the present application is shown. The computer device includes a CPU chip 910, an NPU chip 920 and a memory 930, where the CPU chip 910, the NPU chip 920 and the memory 930 are connected by a bus 940, and the NPU chip 920 is provided with a DMA controller 921 provided in the foregoing embodiment.
As shown in fig. 9, at least two buffers 922 are further disposed in the NPU chip 920, and the dma controller 921 writes the read data and the interpolation data into the buffers 922, so that the NPU chip 920 processes (such as convolution operation) the data in the buffers 922.
Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.
Claims (12)
1. A data transfer method, wherein the method is used for a direct memory access DMA controller, the DMA controller includes an instruction memory module with a depth of n, and n is an integer greater than or equal to 2, the method includes:
Acquiring a first data transmission instruction from the instruction storage module, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter, the first read address parameter is used for indicating the address of first data in a source end, the first write address parameter is used for indicating the address of the first data in a destination end, the first interpolation address parameter is used for indicating the address of first interpolation data in the destination end, and the destination end is provided with n buffers;
sending a first data reading command to a bus according to the first reading address parameter, wherein the bus is used for reading the first data from the source terminal according to the first data reading command;
Determining a write data address of the first data in a first buffer according to the first write address parameter in response to receiving the first data returned by the bus; writing the first data into the first buffer according to the write data address;
Determining an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter in response to the first data returned by the bus not being received; and writing the first interpolation data into the first buffer according to the interpolation address.
2. The method of claim 1, wherein the sending a first data read command to a bus according to the first read address parameter comprises:
Determining a read data address corresponding to at least one data line in the first data according to the first read address parameter;
And sending at least one first data read command to the bus according to the read data address and the data length of the data row.
3. The method of claim 2, wherein the first data is a three-dimensional data block;
The determining, according to the first read address parameter, a read data address corresponding to at least one data line in the first data includes at least one of:
Determining the read data address of the data row in a first dimension according to a data start address in the first read address parameter;
Determining the read data addresses of the data rows in a second dimension according to the data start addresses and two-dimensional address offsets in the first read address parameters, wherein the two-dimensional address offsets are address offsets between adjacent data rows in the second dimension;
And determining the read data addresses of the data rows in a third dimension according to the data starting address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
4. A method according to any one of claims 1 to 3, wherein after said sending a first data read command to the bus according to said first read address parameter, the method further comprises:
acquiring a second data transmission instruction from the instruction storage module, wherein the second data transmission instruction comprises a second read address parameter, a second write address parameter and a second interpolation address parameter;
sending a second data reading command to the bus according to the second reading address parameter, wherein the bus is used for reading second data from the source terminal according to the second data reading command;
Writing the second data into a second buffer according to the second write address parameter in response to receiving the second data returned by the bus;
writing second interpolation data into the second buffer according to the second interpolation address parameter in response to the fact that the second data returned by the bus is not received;
Wherein when the write operation to the first buffer is completed, the write operations of the first buffer and the second buffer are synchronously performed.
5. A method according to any one of claims 1 to 3, wherein the method further comprises:
And responding to the first data to complete writing, and the first interpolation data to complete writing, and releasing the first data transmission instruction in the instruction storage module.
6. A DMA controller, the DMA controller comprising: the device comprises a command sending module, a data writing module and an instruction storage module with depth of n, wherein n is an integer greater than or equal to 2;
The command sending module is configured to obtain a first data transmission command from the command storage module, where the first data transmission command includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of the first data in a destination end, the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end, and the destination end is provided with n buffers;
The command sending module is used for sending a first data reading command to a bus according to the first reading address parameter, and the bus is used for reading the first data from the source end according to the first data reading command;
The data writing module is used for determining a write data address of the first data in a first buffer according to the first write address parameter when the first data returned by the bus is received; writing the first data into the first buffer according to the write data address;
The data writing module is further configured to determine, when the first data returned by the bus is not received, an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter; and writing the first interpolation data into the first buffer according to the interpolation address.
7. The DMA controller according to claim 6, wherein,
The command sending module is used for determining a read data address corresponding to at least one data row in the first data according to the first read address parameter; and sending at least one first data read command to the bus according to the read data address and the data length of the data row.
8. The DMA controller of claim 7 wherein the first data is a three-dimensional data block;
The command sending module is further configured to:
Determining the read data address of the data row in a first dimension according to a data start address in the first read address parameter;
Determining the read data addresses of the data rows in a second dimension according to the data start addresses and two-dimensional address offsets in the first read address parameters, wherein the two-dimensional address offsets are address offsets between adjacent data rows in the second dimension;
And determining the read data addresses of the data rows in a third dimension according to the data starting address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
9. A DMA controller according to any one of claims 6 to 8, wherein,
The command sending module is further configured to obtain a second data transmission instruction from the instruction storage module, where the second data transmission instruction includes a second read address parameter, a second write address parameter, and a second interpolation address parameter; sending a second data reading command to the bus according to the second reading address parameter, wherein the bus is used for reading second data from the source terminal according to the second data reading command;
The data writing module is further configured to write the second data into a second buffer according to the second write address parameter when the second data returned by the bus is received;
the data writing module is further configured to write second interpolation data into the second buffer according to the second interpolation address parameter when the second data returned by the bus is not received;
Wherein when the write operation to the first buffer is completed, the write operations of the first buffer and the second buffer are synchronously performed.
10. A DMA controller according to any one of claims 6 to 8, wherein,
The instruction storage module is further configured to release the first data transmission instruction when the first data completes writing and the first interpolation data completes writing.
11. A neural network processor NPU chip, wherein the NPU chip has a DMA controller as claimed in any one of claims 6 to 10 disposed therein.
12. The computer equipment is characterized by comprising a Central Processing Unit (CPU) chip, an NPU chip and a memory, wherein the CPU chip, the NPU chip and the memory are connected through a bus;
The NPU chip comprises a DMA controller as claimed in any of claims 6 to 10.
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