CN111782448A - Chip self-detection method, device, chip, display system and storage medium - Google Patents
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Abstract
The embodiment of the application provides a chip self-detection method, a device, a chip, a display system and a storage medium, wherein the chip self-detection method comprises the following steps: acquiring power-on detection parameters of a chip; loading a hardware initialization program; when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally, detecting the hardware in an initialization state, and drawing a graph according to a preset drawing command; and generating a chip self-detection result according to the detection result of the hardware and the drawing result. The chip self-detection method, the chip self-detection device, the chip, the display system and the storage medium provided by the embodiment of the application can solve the problem that the chip detection efficiency is low in the traditional scheme.
Description
Technical Field
The present disclosure relates to chip detection technologies, and in particular, to a chip self-detection method, device, chip, display system, and storage medium.
Background
A Graphics Processing Unit (GPU) is a processor specially used for Processing images or Graphics, and is applied to a display system to reduce the pressure of a Central Processing Unit (CPU) in image or Graphics Processing and improve the overall Processing efficiency of the display system.
The display system has the function of power-on self-detection, and comprises a processor, a system mainboard, a memory, a keyboard, a mouse, a hard disk and the like. Faults found in self-detection are usually handled in two cases, a prompt alarm is given for general faults, and direct shutdown is performed for important faults. However, the self-test of the display system can only locate the device with a fault, but can not locate the device, and the chip needs to be tested. In the conventional scheme, the chip needs to be detected by combining with external equipment, and an offline detection mode is adopted, for example: the method comprises the steps that an external host and a signal simulation unit are adopted, a simulation test signal is sent to a chip to be detected through the signal simulation unit, the external host collects the running state result of the chip and determines the fault of the chip, and the traditional scheme has the problem of low detection efficiency.
Disclosure of Invention
The embodiment of the application provides a chip self-detection method, a chip self-detection device, a chip, a display system and a storage medium, which are used for solving the problem of low chip detection efficiency in the traditional scheme.
An embodiment of a first aspect of the present application provides a chip self-detection method, including:
acquiring power-on detection parameters of a chip;
loading a hardware initialization program;
when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally, detecting the hardware in an initialization state, and drawing a graph according to a preset drawing command;
and generating a chip self-detection result according to the detection result of the hardware and the drawing result.
An embodiment of a second aspect of the present application provides a chip self-testing apparatus, including:
the power-on detection parameter acquisition module is used for acquiring power-on detection parameters of the chip;
the hardware initialization program loading module is used for loading a hardware initialization program;
the hardware detection module is used for detecting the hardware in an initialization state when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally;
the drawing module is used for drawing a graph according to a preset drawing command when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally;
and the self-detection result generation module is used for generating a chip self-detection result according to the detection result of the hardware and the drawing result.
An embodiment of a third aspect of the present application provides a chip, including: the chip self-detection device is described above.
An embodiment of a fourth aspect of the present application provides a display system, including: a chip and a memory as described above.
An embodiment of a fifth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the chip self-test method as described above.
According to the technical scheme provided by the embodiment of the application, the hardware in the initialized state is detected and the graph is drawn according to the preset drawing command by acquiring the power-on detection parameters of the chip and loading the hardware initialization program when the power-on detection parameters meet the preset parameter conditions and the hardware initialization program operates normally; and then generating a chip self-detection result according to a drawing result of a detection result set of the hardware, wherein the scheme is executed by the chip without matching with external detection equipment, so that on one hand, the detection efficiency is improved, on the other hand, the detection process is on-line detection, the actual operation environment is equivalent to a real environment, and the accuracy is higher.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flowchart of a chip self-testing method according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a chip self-testing method according to a second embodiment of the present application;
fig. 3 is a schematic structural diagram of a chip self-detection apparatus according to a third embodiment of the present application;
fig. 4 is a schematic structural diagram of a chip according to a fourth embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example one
The implementation provides a chip self-detection method, which is used for self-detection of a chip after the chip is powered on. The chip may be a processor, in particular a graphics processor GPU.
Fig. 1 is a flowchart of a chip self-testing method according to an embodiment of the present disclosure. As shown in fig. 1, the chip self-detection method provided in this embodiment includes:
The power-on detection parameters of the chip may be environmental parameters after the chip is powered on, specifically, some parameters that can affect the normal operation of the chip, for example: temperature, voltage, current, etc. may be detected by providing a temperature sensor, a voltage sensor, and a current sensor inside the chip.
And step 102, loading a hardware initialization program.
The hardware initialization procedure may include, for example: port initialization program, memory initialization program, etc.
And 103, when the power-on detection parameters meet preset parameter conditions and the hardware initialization program runs normally, detecting the hardware in the initialization state, and drawing a graph according to a preset drawing command.
In step 101, after the power-on detection parameters of the chip are obtained, whether the power-on detection parameters meet preset parameter conditions or not can be judged, and if yes, the requirement of normal operation of the chip is met; if not, generating an abnormal alarm signal of the power-on detection parameter.
In the process of executing step 102, when the hardware initialization program runs normally, the requirement of normal work of the chip is met; if the hardware initialization program runs abnormally, an alarm signal of the hardware initialization program abnormity can be generated.
When the power-on detection parameters meet preset parameter conditions and the hardware initialization program runs normally, detecting the hardware in the initialization state, wherein the hardware in the initialization state can be hardware such as each port and an internal memory of a chip. If the hardware detection is normal, generating a normal detection result; if the hardware detection is abnormal, an abnormal detection result is generated.
When the power-on detection parameters meet preset parameter conditions and the hardware initialization program operates normally, drawing a graph according to a preset drawing command, for example: drawing a circle according to a preset drawing command. Then, whether the drawn circle is consistent with the known drawing result is judged, for example: judging whether the color of a certain pixel point is consistent with the color of the pixel point corresponding to the known drawing result, and if so, generating a normal drawing result; if not, generating abnormal result of drawing.
And 104, generating a chip self-detection result according to the detection result of the hardware and the drawing result.
And generating a chip self-detection result according to the hardware detection result and the drawing result generated after the step 103 is executed.
When the hardware normal detection result appears and the normal result is drawn, the chip self-detection normal result is generated, and the chip can normally run. When a hardware abnormity detection result or a drawing abnormity result occurs, a chip self-detection abnormity result is generated, the operation can be stopped, and a fault prompt is generated. And subsequently, the reason of the fault or abnormal condition can be known according to the fault prompt.
According to the technical scheme provided by the embodiment, by acquiring the power-on detection parameters of the chip and loading the hardware initialization program, when the power-on detection parameters meet the preset parameter conditions and the hardware initialization program operates normally, the hardware in the initialization state is detected, and a graph is drawn according to the preset drawing command; and then generating a chip self-detection result according to a drawing result of a detection result set of the hardware, wherein the scheme is executed by the chip without matching with external detection equipment, so that on one hand, the detection efficiency is improved, on the other hand, the detection process is on-line detection, the actual operation environment is equivalent to a real environment, and the accuracy is higher.
Example two
The present embodiment is to optimize a chip self-testing method based on the above embodiments, and particularly provides a specific implementation manner of the chip self-testing method. This embodiment takes a General-purpose graphics processing unit (GPGPU for short) as an example to describe the chip self-detection method in detail.
The method provided by the present embodiment may be implemented by a computer program, which is stored in a memory. In the embodiment, the computer program is stored in the FLASH memory FLASH outside the GPGPU, so that the reading speed is high, and the self-detection efficiency can be improved. Or, the real-time restart self-test can be carried out through the software debugging interface, and the corresponding self-test can be completed under the working mode without influencing the normal operation.
Fig. 2 is a flowchart of a chip self-testing method according to a second embodiment of the present application. As shown in fig. 2, the method provided by this embodiment includes:
The parameter initialization operation comprises the operations of resetting and clearing relevant parameters, variables, flag bits and the like, can also execute the operations of pointer release and the like, and can also carry out initialization operation according to chip configuration pins. The specific operation can be set according to the structure and function of the chip. After the initialization of the above parameters is completed, steps 202, 203 and 204 are performed.
Specifically, the power-on detection parameter includes a power-on voltage of the chip. The GPGPU chip has a plurality of voltage domains, and voltage sensors may be provided in the voltage domains, respectively.
And acquiring the voltage detected by each voltage sensor, acquiring and recording the electrifying voltage of each voltage domain in real time, and recording the highest voltage and the lowest voltage.
And step 203, acquiring the internal temperature of the chip.
Specifically, a temperature sensor is arranged in each area in the GPGPU chip, so as to realize distributed detection of each area, for example: a temperature sensor is arranged near the element with larger power consumption, and a temperature sensor is arranged near the core element.
The temperature detected by each temperature sensor is obtained, the temperature value of each area of the chip is obtained and recorded in real time, and the highest temperature and the lowest temperature can be recorded.
The steps of detecting the voltage and the temperature can be executed synchronously. Or the step of detecting the voltage may be executed first, and the step of detecting the temperature may be executed after each voltage value meets the requirement.
And step 204, loading a hardware initialization program.
The specific operation may be loading a Physical (PHY) port layer initialization program, loading a Double Data Rate Synchronous Random Access Memory (DDR SDRAM or DDR) initialization program, and the like.
Step 204 may operate in parallel with step 202 and may be initiated simultaneously.
And step 205, when the power-on detection parameters meet the preset parameter conditions and the hardware initialization program runs normally, detecting the hardware in the initialization state, and drawing a graph according to a preset drawing command.
After the above step 202 is finished, it is determined whether the power-on voltage is within the preset voltage range.
After the end of the above step 203, it is determined whether the internal temperature is within the preset temperature range.
The upper and lower threshold values of the preset voltage range and the preset temperature range can be dynamically adjusted, for example, the upper and lower threshold values can be dynamically adjusted according to the external environment or the working scene of the chip.
And if the electrifying voltage is within the preset voltage range and the internal temperature is within the preset temperature range, the preset parameter condition is met.
When the power-on detection parameters meet the preset parameter conditions and the hardware initialization program runs normally, a Built-in Self Test (BIST) is started. The BIST includes: and detecting the hardware in the initialization state, and drawing the graph according to a preset drawing command. A BIST control module may be employed to execute a BIST test procedure.
Wherein, the hardware in the initialization state comprises: and detecting the hardware circuit in the initialization state, detecting the DDR read-write operation of the memory, and the like to detect whether the hardware circuit is in the operation state or not. And if the abnormal condition occurs, generating abnormal alarm information. The BIST test described above can cover all the paths inside the chip.
The above-mentioned detection method for hardware can be implemented by means commonly used in the art, and the embodiment is not limited.
And starting the drawing unit to draw the graph according to the preset drawing command, and comparing the drawing result with the preset result. When the drawing result is the same as the preset result, generating a normal drawing result; and when the drawing result is different from the preset result, generating an abnormal drawing result.
Specifically, comparing the drawing result with the preset result may adopt a global pixel comparison method: comparing the global pixel point of the rendering result with the global pixel point of the preset result, which is equivalent to comparing all pixels of the rendering result with corresponding pixels of the preset result, for example: compare if their colors are the same. If the colors of part of the pixel points in the drawing result are different from the preset result, counting the number of the pixel points with different colors, and if the number of the pixel points is within a second preset range, indicating that the drawing result is the same as the preset result.
For a simple example, the drawing result and the predetermined result both have 100 pixels, and if the number of pixels with different colors is less than 5, it indicates that the drawing result is the same as the predetermined result. If the number of the pixels with different colors is larger than 5, the drawing result is different from the preset result.
The drawn result is compared with a preset result, and a mode of comparing a local pixel point and a cyclic redundancy check value can also be adopted: and comparing the local pixel points of the drawing result with the local pixel points of the preset result, namely correspondingly comparing a part of pixels in the drawing result with the preset result. And comparing the Cyclic Redundancy Check (CRC) value of each line in the drawing result with a CRC value corresponding to the preset result. And when the number of the pixel points with difference between the local pixel point of the drawing result and the local pixel point of the preset result is within a first preset range, and the CRC value of each row in the drawing result is the same as the CRC value of the preset result, the drawing result is the same as the preset result.
For a simple example, the drawing result and the preset result have 100 pixels, 50 pixels are compared, and if the number of pixels with different colors is less than 3 and the CRC value of each row is the same as the CRC value of the preset result, it indicates that the drawing result is the same as the preset result. If the number of the pixels with different colors is more than 3 or the CRC value of each row is different from the CRC value of the preset result, the drawing result is different from the preset result.
The mode of local pixel point and CRC detection is adopted, the detection speed is higher, and the method can be suitable for a system with higher requirement on response time.
And step 206, generating a normal chip self-detection result when the detection result of the hardware is a normal detection result and the drawing result is a normal drawing result.
Otherwise, if the detection result of the hardware is an abnormal detection result or the drawing result is an abnormal drawing result, a chip abnormal self-detection result is generated.
And step 207, writing the chip self-detection result into a state register.
And step 208, loading the driver.
Before the GPGPU chip is loaded, the state register is polled, and whether a subsequent loading kernel mode is started or not is determined according to the content recorded in the state register.
For example, when the status register records a normal self-test result, the operation of loading the kernel driver is started.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a chip self-detection apparatus according to a third embodiment of the present application. As shown in fig. 3, the chip self-testing apparatus provided in this embodiment includes: a power-on detection parameter acquisition module 31, a hardware initialization program loading module 32, a hardware detection module 33, a drawing graph module 34 and a self-detection result generation module 35.
The power-on detection parameter obtaining module 31 is configured to obtain a power-on detection parameter of the chip. The hardware initialization program loading module 32 is used for loading a hardware initialization program. The hardware detection module 33 is configured to detect the hardware in an initialization state when the power-on detection parameter meets a preset parameter condition and a hardware initialization program operates normally. The drawing graph module 34 is configured to draw a graph according to a preset drawing command when the power-on detection parameter meets a preset parameter condition and the hardware initialization program operates normally. The self-test result generation module 35 is configured to generate a chip self-test result according to the hardware test result and the drawing result.
According to the technical scheme provided by the embodiment, by acquiring the power-on detection parameters of the chip and loading the hardware initialization program, when the power-on detection parameters meet the preset parameter conditions and the hardware initialization program operates normally, the hardware in the initialization state is detected, and a graph is drawn according to the preset drawing command; and then generating a chip self-detection result according to a drawing result of a detection result set of the hardware, wherein the scheme is executed by the chip without matching with external detection equipment, so that on one hand, the detection efficiency is improved, on the other hand, the detection process is on-line detection, the actual operation environment is equivalent to a real environment, and the accuracy is higher.
On the basis of the technical scheme, the power-on detection parameters comprise: the power-on voltage of the chip and the internal temperature of the chip. The power-on detection parameter acquiring module 31 includes: a power-on voltage acquisition unit and an internal temperature acquisition unit. The power-on voltage acquisition unit is used for acquiring power-on voltages of all voltage domains of the chip. The internal temperature acquisition unit is used for acquiring the internal temperature of each area of the chip.
The preset parameter conditions are as follows: the power-on voltage is within a preset voltage range, and the internal temperature is within a preset temperature range.
Further, the hardware initialization program loading module 32 includes: a physical port layer initialization program loading unit and a memory initialization program loading unit. The physical port layer initialization program loading unit is used for loading a physical port layer initialization program. The memory initialization program loading unit is used for loading a memory initialization program.
The hardware detection module 33 includes: hardware circuit detection unit and memory read-write operation detection unit. The hardware circuit detection unit is used for detecting the hardware circuit in the initialization state. The memory read-write operation detection unit is used for detecting the memory read-write operation.
Further, the chip self-detection device further comprises: the device comprises a drawing result comparison module, a normal drawing result generation module and an abnormal drawing result generation module. The drawing result comparison module is used for comparing the drawing result with a preset result. The normal drawing result generating module is used for generating a normal drawing result when the drawing result is the same as the preset result. The abnormal drawing result generating module is used for generating an abnormal drawing result when the drawing result is different from the preset result.
The drawing result comparison module includes: the device comprises a local pixel point comparison unit, a cyclic redundancy check value comparison unit and a drawing result generation unit. The local pixel point comparison unit is used for comparing the local pixel point of the drawing result with the local pixel point of the preset result. And the cyclic redundancy check value comparison unit is used for comparing the cyclic redundancy check value of each row in the drawing result with the cyclic redundancy check value of the preset result. The drawing result generating unit is used for generating a normal drawing result with the same drawing result as the preset result when the number of the pixel points with difference between the local pixel point of the drawing result and the local pixel point of the preset result is within a first preset range and the cyclic redundancy check value of each row in the drawing result is the same as the cyclic redundancy check value of the preset result.
Or, the drawing result comparing module includes: the global pixel point comparison unit and the drawing result generation unit. The global pixel point comparison unit is used for comparing the global pixel point of the drawing result with the global pixel point of the preset result. The drawing result generating unit is used for generating a normal drawing result with the same drawing result as the preset result when the number of the pixel points with difference between the global pixel point of the drawing result and the global pixel point of the preset result is in a second preset range.
The self-detection result generation module is specifically configured to generate a normal self-detection result of the chip when the detection result of the hardware is a normal detection result and the drawing result is a normal drawing result.
Further, the chip self-detection device further comprises: and the status register writing module is used for writing the chip self-detection result into the status register.
Further, the chip self-detection device further comprises: and the parameter initialization operation module is used for executing parameter initialization operation after the chip is powered on and the clock is stable.
Example four
The present embodiment provides a chip, including: a chip self-test device as provided in any of the above.
The chip is a Graphics Processing Unit (GPU) chip, in particular a GPGPU chip.
In addition, the present embodiment also provides a computer-readable storage medium on which a computer program is stored, the computer program being executed by a processor to implement the chip self-detection method provided in any one of the above.
The embodiment also provides a display system. Fig. 4 is a schematic structural diagram of a display system according to a fourth embodiment of the present application, and as shown in fig. 4, the display system includes: any of the chips 41 and computer readable storage media 42 provided above.
The computer readable storage medium 42 is preferably a FLASH memory FLASH.
The chip, the display system and the storage medium provided by the embodiment have the same technical effects as the method.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the description of the present application, it is to be understood that, furthermore, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (27)
1. A chip self-detection method is characterized by comprising the following steps:
acquiring power-on detection parameters of a chip;
loading a hardware initialization program;
when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally, detecting the hardware in an initialization state, and drawing a graph according to a preset drawing command;
and generating a chip self-detection result according to the detection result of the hardware and the drawing result.
2. The method of claim 1, wherein the power-up detection parameters comprise: the power-on voltage of the chip and the internal temperature of the chip;
the method for acquiring the power-on detection parameters of the chip comprises the following steps:
acquiring the power-on voltage of each voltage domain of the chip;
and acquiring the internal temperature of each area of the chip.
3. The method according to claim 2, wherein the preset parameter conditions are: the power-up voltage is within a preset voltage range, and the internal temperature is within a preset temperature range.
4. The method of claim 1, wherein loading a hardware initialization program comprises:
loading a physical port layer initialization program;
and loading a memory initialization program.
5. The method of claim 1, wherein detecting hardware in an initialization state comprises:
detecting a hardware circuit in an initialization state;
and detecting the memory read-write operation.
6. The method of claim 1, further comprising, after drawing the graphic according to the preset drawing command:
comparing the drawing result with a preset result;
when the drawing result is the same as the preset result, generating a normal drawing result;
and when the drawing result is different from the preset result, generating an abnormal drawing result.
7. The method of claim 6, wherein comparing the drawing result with a preset result comprises:
comparing the local pixel points of the drawing result with the local pixel points of the preset result;
comparing the cyclic redundancy check value of each row in the drawing result with the cyclic redundancy check value of the preset result; if the number of the pixel points with difference between the local pixel point of the drawing result and the local pixel point of the preset result is within a first preset range, and the cyclic redundancy check value of each row in the drawing result is the same as the cyclic redundancy check value of the preset result, the drawing result is the same as the preset result.
8. The method of claim 6, wherein comparing the drawing result with a preset result comprises:
comparing the global pixel points of the drawing result with the global pixel points of the preset result; and if the number of the pixel points with difference between the global pixel point of the drawing result and the global pixel point of the preset result is within a second preset range, the drawing result is the same as the preset result.
9. The method of claim 6, wherein generating a chip self-test result according to the hardware test result and the mapping result comprises:
and when the detection result of the hardware is a normal detection result and the drawing result is a normal drawing result, generating a normal chip self-detection result.
10. The method of claim 1, further comprising: and writing the self-detection result of the chip into a state register.
11. The method of claim 1, before obtaining power-on detection parameters of the chip, further comprising:
and after the chip is powered on and the clock is stable, executing parameter initialization operation.
12. A chip self-detection device, comprising:
the power-on detection parameter acquisition module is used for acquiring power-on detection parameters of the chip;
the hardware initialization program loading module is used for loading a hardware initialization program;
the hardware detection module is used for detecting the hardware in an initialization state when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally;
the drawing module is used for drawing a graph according to a preset drawing command when the power-on detection parameters meet preset parameter conditions and a hardware initialization program runs normally;
and the self-detection result generation module is used for generating a chip self-detection result according to the detection result of the hardware and the drawing result.
13. The apparatus of claim 12, wherein the power-up detection parameters comprise: the power-on voltage of the chip and the internal temperature of the chip;
the power-on detection parameter acquisition module comprises:
the power-on voltage acquisition unit is used for acquiring power-on voltages of all voltage domains of the chip;
and the internal temperature acquisition unit is used for acquiring the internal temperature of each area of the chip.
14. The apparatus of claim 13, wherein the preset parameter condition is: the power-up voltage is within a preset voltage range, and the internal temperature is within a preset temperature range.
15. The apparatus of claim 12, wherein the hardware initialization program loading module comprises:
a physical port layer initialization program loading unit for loading a physical port layer initialization program;
and the memory initialization program loading unit is used for loading the memory initialization program.
16. The apparatus of claim 12, wherein the hardware detection module comprises:
the hardware circuit detection unit is used for detecting the hardware circuit in the initialized state;
and the memory read-write operation detection unit is used for detecting the memory read-write operation.
17. The apparatus of claim 12, further comprising:
the drawing result comparison module is used for comparing the drawing result with a preset result;
the normal drawing result generating module is used for generating a normal drawing result when the drawing result is the same as the preset result;
and the abnormal drawing result generating module is used for generating an abnormal drawing result when the drawing result is different from the preset result.
18. The apparatus of claim 17, wherein the plot result comparison module comprises:
the local pixel point comparison unit is used for comparing the local pixel point of the drawing result with the local pixel point of the preset result;
the cyclic redundancy check value comparison unit is used for comparing the cyclic redundancy check value of each row in the drawing result with the cyclic redundancy check value of the preset result;
and the drawing result generating unit is used for generating a normal drawing result with the same drawing result as the preset result when the number of the pixel points with difference between the local pixel point of the drawing result and the local pixel point of the preset result is within a first preset range and the cyclic redundancy check value of each row in the drawing result is the same as the cyclic redundancy check value of the preset result.
19. The apparatus of claim 17, wherein the plot result comparison module comprises:
the global pixel point comparison unit is used for comparing the global pixel points of the drawing result with the global pixel points of the preset result;
and the drawing result generating unit is used for generating a normal drawing result with the same drawing result as the preset result when the number of the pixel points with difference between the global pixel point of the drawing result and the global pixel point of the preset result is in a second preset range.
20. The apparatus of claim 17, wherein the self-test result generation module is specifically configured to generate a normal self-test result of the chip when the test result of the hardware is a normal test result and the drawing result is a normal drawing result.
21. The apparatus of claim 12, further comprising:
and the status register writing module is used for writing the chip self-detection result into a status register.
22. The apparatus of claim 12, further comprising:
and the parameter initialization operation module is used for executing parameter initialization operation after the chip is powered on and the clock is stable.
23. A chip, comprising: the chip self-test device according to any one of claims 12 to 22.
24. The chip of claim 23, wherein the chip is a general purpose graphics processor chip.
25. A computer-readable storage medium, having stored thereon a computer program; the computer program is executed by a processor to implement the chip self-test method of any one of claims 1-11.
26. A display system, comprising: a chip as claimed in claim 23 or 24 and a computer readable storage medium as claimed in claim 25.
27. The display system of claim 26, wherein the computer readable storage medium is a flash memory.
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