CN111781980B - Voltage control circuit and control method thereof - Google Patents
Voltage control circuit and control method thereof Download PDFInfo
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- CN111781980B CN111781980B CN202010541617.XA CN202010541617A CN111781980B CN 111781980 B CN111781980 B CN 111781980B CN 202010541617 A CN202010541617 A CN 202010541617A CN 111781980 B CN111781980 B CN 111781980B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The present application relates to the field of integrated circuit technology, and more particularly, to a voltage control circuit and a voltage control method. The voltage control circuit includes: the device comprises a band gap reference circuit, a voltage stabilizer, a charge pump, an oscillation circuit and an enabling circuit, wherein the enabling circuit is used for collecting a voltage value of a voltage-stabilized signal and a voltage value of a high-voltage signal, judging whether the voltage value of the voltage-stabilized signal is lower than a first threshold voltage, judging whether the voltage value of the high-voltage signal is lower than a second threshold voltage, and outputting a wake-up enabling signal according to a judgment result; if the voltage value of the voltage stabilizing signal is lower than or equal to the first threshold voltage, the awakening enabling signal output by the enabling circuit can awaken the voltage stabilizer; if the voltage value of the high voltage signal is lower than or equal to the first threshold voltage, the wake-up enabling signal output by the enabling circuit can wake up the charge pump. The application provides a voltage control circuit and a control method thereof, which can solve the problem that the recovery response time of an integrated circuit is sacrificed in pursuit of low power consumption in the related art.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to a voltage control circuit and a voltage control method.
Background
At present, the requirement for standby power consumption of circuits in the field of integrated circuit technology has been increasing. The integrated circuit standby state refers to a state in which the integrated circuit has been connected to an external power supply, but does not operate its main function.
In the related art, the voltage control circuit is usually continuously powered down to reduce its power consumption when the integrated circuit is in a standby state. However, when the integrated circuit needs to move its main function, the integrated circuit needs to wait for the voltage control circuit to return to normal state, and then the integrated circuit can return to normal operation state from standby state, which prolongs the response time of the integrated circuit.
Therefore, what kind of voltage control circuit and control method are provided to make the integrated circuit have lower standby power consumption and faster recovery response time has become an urgent technical problem to be solved in the art.
Disclosure of Invention
The application provides a voltage control circuit and a control method thereof, which can solve the problem that the recovery response time of an integrated circuit is sacrificed in pursuit of low power consumption in the related art.
In one aspect, the present application is directed to a voltage control circuit, comprising:
the band-gap reference circuit is characterized in that an enabling end of the band-gap reference circuit is connected with a wake-up enabling signal, and an output end of the band-gap reference circuit is used for outputting reference voltage;
the reference end of the voltage stabilizer is connected with the output end of the band-gap reference circuit, the control end of the voltage stabilizer is connected with the awakening enabling signal, and the output end of the voltage stabilizer can output a voltage stabilizing signal according to the reference voltage and the awakening enabling signal;
the reference end of the charge pump is connected with the output end of the band-gap reference circuit, the control end of the charge pump is connected with the awakening enabling signal, and the output end of the charge pump can output a high-voltage signal according to the reference voltage and the awakening enabling signal;
the enabling end of the oscillating circuit is connected with a wake-up enabling signal, and under the action of the wake-up enabling signal, the oscillating circuit generates a clock signal to the charge pump;
the enabling circuit is used for acquiring a voltage value of a voltage stabilizing signal and a voltage value of a high voltage signal, judging whether the voltage value of the voltage stabilizing signal is lower than a first threshold voltage, judging whether the voltage value of the high voltage signal is lower than a second threshold voltage, and outputting a wake-up enabling signal according to a judgment result; if the voltage value of the voltage stabilizing signal is lower than or equal to a first threshold voltage, the awakening enabling signal output by the enabling circuit can awaken the voltage stabilizer; if the voltage value of the high voltage signal is lower than or equal to the first threshold voltage, the wake-up enabling signal output by the enabling circuit can wake up the charge pump.
Optionally, the enabling circuit comprises:
an OR gate;
the first detector is used for outputting a first enabling signal to an OR gate according to a voltage stabilizing signal at the output end of the voltage stabilizer;
the second detector is used for outputting a second enabling signal to an OR gate according to the voltage signal at the output end of the charge pump;
the OR gate outputs a wake-up enabling signal according to the first enabling signal and the second enabling signal.
Optionally, the first enable signal comprises a high level signal and a low level signal which are alternately appeared.
Optionally, when the voltage value of the regulated voltage signal is less than or equal to a first threshold voltage, the first enable signal is a high level signal, and when the voltage value of the regulated voltage signal is greater than the first threshold voltage, the first enable signal is a low level signal.
Optionally, the second enable signal comprises a high level signal and a low level signal which are alternately appeared.
The voltage control circuit of claim 5, wherein the second enable signal is a high level signal when the voltage value of the high voltage signal output by the charge pump is less than or equal to a second threshold voltage, and the second enable signal is a low level signal when the voltage value of the high voltage signal output by the charge pump is greater than the second threshold voltage.
Optionally, the voltage control circuit further comprises:
the switch is arranged at the output end of the band-gap reference circuit, and the enabling end of the switch is connected with a wake-up enabling signal and used for outputting the reference voltage to the voltage stabilizer and the charge pump under the control of the wake-up enabling signal.
Optionally, the voltage control circuit further comprises:
and one end of the capacitor is connected with the output end of the switch, and the other end of the capacitor is grounded.
Optionally, in a standby state, the regulated voltage signal includes a standby phase and a wake-up phase which alternately occur;
in the standby stage, the voltage value of the voltage stabilizing signal gradually decreases until a first threshold voltage is reached;
in the awakening stage, the voltage value of the voltage stabilizing signal is charged according to the reference voltage control, and gradually rises from the first threshold voltage.
Optionally, in the standby state, the high voltage signal includes a standby phase and a wake-up phase which alternately occur;
in the standby stage, the voltage value of the voltage stabilizing signal gradually decreases until a second threshold voltage is reached;
and in the awakening stage, the voltage value of the voltage-stabilizing signal controls charging according to the reference voltage and the clock signal, so that the voltage value of the voltage-stabilizing signal gradually rises from the second threshold voltage.
Optionally, the wake-up enable signal comprises a high-level signal and a low-level signal which are alternately appeared;
when the first enabling signal and/or the second enabling signal are/is a high-level signal, the awakening enabling signal is a high-level signal; and when the first enabling signal and the second enabling signal are low-level signals, the awakening enabling signal is a low-level signal.
On the other hand, an embodiment of the present application provides a voltage control method, so that the voltage control circuit described in the first aspect of the present application enters a standby state, including at least the following steps:
gradually reducing the voltage value of the voltage-stabilizing signal and the voltage value of the high-voltage signal;
determining that the voltage value of the voltage stabilization signal is reduced to a first threshold voltage, and waking up an enable signal to jump into a high-level signal, so that the voltage value of the voltage stabilization signal is charged and increased under the control of a reference voltage;
the voltage value of the voltage stabilization signal is enabled to continuously decrease;
determining that the voltage value of the high voltage signal is reduced to a second threshold voltage, and enabling a wake-up enabling signal to jump into a high level signal, so that the voltage value of the high voltage signal is charged and increased under the control of a reference voltage;
so that the voltage value of the high voltage signal continues to drop.
Optionally, the determining that the voltage value of the regulated voltage signal is reduced to the first threshold voltage causes the first enable signal to jump to a high level signal.
Optionally, the step of enabling the voltage value of the regulated voltage signal to be charged and raised under the control of the reference voltage until the voltage value of the regulated voltage signal is charged to the first preset wake-up voltage value, the first enable signal is enabled to change to a low-level signal, and the voltage value of the regulated voltage signal continues to decrease.
Optionally, the determining that the voltage value of the high voltage signal is decreased to the second threshold voltage causes the second enable signal to jump to a high level signal.
Optionally, the step of enabling the voltage value of the high voltage signal to be charged and raised under the control of the reference voltage and the clock signal is performed until the voltage value of the high voltage signal is charged to a second preset wake-up voltage value, so that the second enable signal is transitioned to a low level signal, and the voltage value of the high voltage signal continues to drop.
The technical scheme at least comprises the following advantages: according to the embodiment of the application, the voltage control circuit intermittently enters the awakening state when the voltage control circuit is in the standby state, so that the voltage values of the voltage stabilizing signal and the high voltage signal can intermittently rise in the descending process, and the response speed in the normal working state recovery process can be improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a voltage control circuit according to an embodiment of the present disclosure;
FIG. 2 is another voltage control circuit provided in an embodiment of the present application;
FIG. 3 is a sequence diagram of a voltage control circuit provided by an embodiment of the present application during a standby state;
fig. 4 is a flowchart of another voltage control method provided in the embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a voltage control circuit provided in an embodiment of the present application is shown, and the voltage control circuit includes:
the band-gap reference circuit comprises an enabling end and an output end, wherein the enabling end is connected with a wake-up enabling signal REFRESH.
The switch comprises a control end, an input end and an output end, the control end of the switch is connected with a wake-up enabling signal REFRESH.EN, the input end of the switch is connected with the output end of the band-gap reference circuit, and the switch is used for controlling the reference voltage generated by the band-gap reference circuit to be transmitted continuously according to the wake-up enabling signal REFRESH.EN.
The voltage stabilizer comprises a reference end, a control end and an output end; the reference end of the voltage stabilizer is connected with the output end of the switch, the control end of the voltage stabilizer is connected with a wake-up enabling signal REFRESH.EN, and the output end of the voltage stabilizer is used for outputting a voltage stabilizing signal VDD; the switch controls the voltage generated by the band-gap reference circuit to be continuously transmitted to the voltage stabilizer according to the awakening enable signal REFRESH.
In a standby state, the voltage stabilization signal comprises a standby phase and a wake-up phase which alternately appear; in the standby stage, the voltage value of the voltage-stabilizing signal gradually decreases until the voltage value reaches a first threshold voltage; in the wake-up stage, the voltage value of the regulated voltage signal is charged according to the reference voltage control, and gradually rises from the first threshold voltage.
The charge pump comprises a reference end, a control end, a clock end and an output end, wherein the reference end of the charge pump is connected with the output end of the switch, the control end of the charge pump is connected with a wakeup enable signal REFRESH.EN, and the output end of the charge pump is used for outputting a high-voltage signal VCP; the switch controls the voltage generated by the band-gap reference circuit to be continuously transmitted to the charge pump according to the wake-up enable signal REFRESH.
In a standby state, the high voltage signal comprises a standby phase and a wake-up phase which alternately appear; in the standby stage, the voltage value of the voltage-stabilizing signal gradually decreases until reaching a second threshold voltage; and in the awakening stage, the voltage value of the voltage-stabilizing signal controls charging according to the reference voltage and the clock signal, so that the voltage value of the voltage-stabilizing signal gradually rises from the second threshold voltage.
The oscillating circuit comprises an enabling end and an output end, the enabling end of the oscillating circuit is connected with a wake-up enabling signal REFRESH.EN, the output end of the oscillating circuit is connected with a clock end of the charge pump and used for generating a clock signal to the charge pump under the action of the wake-up enabling signal REFRESH.EN, and the charge pump can output a high-voltage signal VCP according to the reference voltage and the wake-up enabling signal REFRESH.EN on the rising edge of the clock signal.
The enabling circuit comprises a first acquisition end, a second acquisition end and an output end, the first acquisition end of the enabling circuit is connected with the output end of the voltage stabilizer, the second acquisition end of the enabling circuit is connected with the output end of the charge pump, and the output end of the enabling circuit is used for outputting a wake-up enabling signal REFRESH. The enabling signal is used for judging whether the voltage value of a voltage stabilizing signal VDD output by the output end of the voltage stabilizer and the voltage value of a high voltage signal VCP output by the output end of the charge pump are smaller than a preset threshold value or not, and if the voltage value is smaller than the preset threshold value, the charge pump and the voltage stabilizer can be powered by the awakening enabling signal REFRESH.
In summary, in the embodiment of the application, when the voltage control circuit is in the standby state, the voltage control circuit intermittently enters the wake-up state, so that the voltage values of the regulated voltage signal and the high voltage signal can intermittently rise in the process of falling, and the response speed when the normal operating state is recovered can be improved.
Referring to fig. 2, another voltage control circuit provided in an embodiment of the present application is shown, and includes:
the switch comprises a control end, an input end and an output end, the control end of the switch is connected with a wake-up enabling signal REFRESH.EN, the input end of the switch is connected with the output end of the band-gap reference circuit, and the switch is used for controlling the reference voltage generated by the band-gap reference circuit to be transmitted continuously according to the wake-up enabling signal REFRESH.EN.
And one end of the capacitor is connected with the output end of the switch, and the other end of the capacitor is grounded.
The voltage stabilizer comprises a reference end, a control end and an output end; the reference end of the voltage stabilizer is connected with the output end of the switch, the control end of the voltage stabilizer is connected with a wake-up enabling signal REFRESH.EN, and the output end of the voltage stabilizer is used for outputting a voltage stabilizing signal VDD; the switch controls the voltage generated by the band-gap reference circuit to be continuously transmitted to the voltage stabilizer according to the awakening enable signal REFRESH.
The charge pump comprises a reference end, a control end, a clock end and an output end, wherein the reference end of the charge pump is connected with the output end of the switch, the control end of the charge pump is connected with a wakeup enable signal REFRESH.EN, and the output end of the charge pump is used for outputting a high-voltage signal VCP; the switch controls the voltage generated by the band-gap reference circuit to be continuously transmitted to the charge pump according to the wake-up enable signal REFRESH.
The oscillating circuit comprises an enabling end and an output end, the enabling end of the oscillating circuit is connected with a wake-up enabling signal REFRESH.EN, the output end of the oscillating circuit is connected with a clock end of the charge pump and used for generating a clock signal to the charge pump under the action of the wake-up enabling signal REFRESH.EN, and the charge pump can output a high-voltage signal VCP according to the reference voltage and the wake-up enabling signal REFRESH.EN on the rising edge of the clock signal.
The first detector comprises a collecting end and an output end, the collecting end of the first detector is connected with the output end of the voltage stabilizer, and the output end of the first detector outputs a first enable signal EN1 to the OR gate.
And the second detector comprises a collecting end and an output end, the collecting end of the second detector is connected with the output end of the charge pump, and the output end of the second detector outputs a second enable signal EN2 to the OR gate.
And the OR gate comprises a first input end, a second input end and an output end, the first input end of the OR gate is connected with the output end of the first detector, the second input end of the OR gate is connected with the output end of the second detector, and the output end of the OR gate is used for outputting a wake-up enable signal REFRESH.
Fig. 3 is a timing diagram of the voltage control circuit during the standby state according to the embodiment of the present application, where the timing diagram includes timing variations of the regulated voltage signal VDD, the high voltage signal VCP, the first enable signal EN1, the second enable signal EN2, and the wake-up enable signal refresh.
In the standby state of the voltage control circuit, the voltage control circuit intermittently enters the wake-up state, so that the first enable signal EN1 and the second enable signal EN2 are alternately high and low signals, namely the first enable signal EN1 comprises alternately high-level signals and low-level signals, and the second enable signal EN2 comprises alternately high-level signals and low-level signals.
The wake-up enable signal refresh.en is a signal in which high and low levels alternately appear, that is, the wake-up enable signal refresh.en includes a high level signal and a low level signal which alternately appear; the wake-up enable signal refresh is high when the first enable signal EN1 is high and/or the second enable signal EN2 is high, and low when the first enable signal EN1 and the second enable signal EN2 are low, the wake-up enable signal refresh is a signal in which high and low levels alternately appear.
From time T1, the voltage control circuit enters a standby state from a normal operating state, the voltage value of the voltage stabilization signal VDD gradually decreases, when the voltage stabilization signal VDD decreases to a first threshold voltage VDDL, the first enable signal EN1 changes from a low level to a high level, the wake-up enable signal refresh _ EN changes from a low level to a high level, so that the voltage control circuit enters a wake-up state, so that the voltage regulator is charged and rises under the control of the reference voltage, and the voltage value gradually rises until reaching a first preset wake-up voltage value VDDH, the voltage control circuit enters the standby state again, the first enable signal EN1 changes from a high level to a low level, the wake-up enable signal refresh _ EN changes from a high level to a low level, and the voltage value of the voltage stabilization signal VDD gradually decreases, so that the voltage value of the voltage stabilization signal VDD alternately rises and falls.
In order to reduce the standby power consumption, the voltage value of the regulated voltage signal VDD gradually rises to a maximum value during the wake-up phase in the standby state, which may be smaller than the first predetermined wake-up voltage value VDDH. As shown in fig. 3, the voltage regulator is awakened in the P1 and P3 periods in the standby state.
From time T1, the voltage control circuit enters a standby state from a normal operation state, and gradually decreases the voltage value of the high-voltage signal VCP, and when the high-voltage signal VCP decreases to the second threshold voltage VCPL, the second enable signal EN2 changes from a low level to a high level, the wake-up enable signal refresh.en changes from a low level to a high level, so that the voltage control circuit enters a wake-up state, so that the charge pump is charged and rises under the control of the reference voltage and the clock signal CLK, and the voltage value gradually rises until reaching the second preset wake-up voltage value VCPH, the voltage control circuit enters the standby state again, the second enable signal EN2 changes from a high level to a low level, the wake-up enable signal refresh.en changes from a high level to a low level, and the voltage value of the high-voltage signal VCP gradually decreases, so that the voltage value of the high-voltage signal VCP alternately rises and falls.
In order to reduce the standby power consumption, in the wake-up phase in the standby state, the voltage value of the high-voltage signal VCP gradually rises to reach a maximum value that may be smaller than the second preset wake-up voltage value VCPH. As shown in fig. 3, the charge pump is awakened in the P2 and P4 periods in the standby state.
In summary, in the embodiment of the application, when the voltage control circuit is in the standby state, the voltage control circuit intermittently enters the wake-up state, so that the voltage values of the regulated voltage signal and the high voltage signal can intermittently rise in the process of falling, and the response speed when the normal operating state is recovered can be improved.
Referring to fig. 4, a voltage control method provided by an embodiment of the present application is illustrated, and the voltage control method is used for implementing low power consumption standby and fast wake-up of a voltage control circuit, where the voltage control circuit includes a bandgap reference circuit, a voltage regulator, a charge pump, an oscillation circuit, and an enable circuit. The method at least comprises the following steps:
In step 402, the enable circuit determines whether the voltage value of the regulated voltage signal is lower than a first threshold voltage, and determines whether the voltage value of the high voltage signal is lower than a second threshold voltage.
Therefore, the normal working state enters the standby state, the voltage value of the voltage stabilizing signal and the high voltage signal are reduced from the normal working state, the relation between the voltage value of the voltage stabilizing signal and the first threshold voltage in the reducing process can be judged through the enabling circuit, and the relation between the voltage value of the high voltage signal and the second threshold voltage in the reducing process can be judged.
in step 404, after the voltage value of the regulated signal is charged and increased under the control of the reference voltage, the first enable signal is changed from the high level signal to the low level signal, so that the voltage value of the regulated signal is continuously decreased.
And charging and rising the voltage value of the voltage stabilizing signal under the control of the reference voltage until the voltage value of the voltage stabilizing signal is charged to a first preset wake-up voltage value, so that the first enable signal is changed into a low-level signal in a jumping way, and the voltage value of the voltage stabilizing signal is continuously reduced.
And charging and rising the voltage value of the high-voltage signal under the control of the reference voltage and the clock signal until the voltage value of the high-voltage signal is charged to a second preset wake-up voltage value, enabling the second enable signal to jump into a low-level signal, and continuing to drop the voltage value of the high-voltage signal.
In summary, in the embodiments of the present application, when the voltage control circuit is in the standby state, the voltage control circuit may intermittently enter the wake-up state, so that the voltage values of the regulated voltage signal and the high voltage signal may intermittently increase in the process of decreasing, and the response speed when the normal operating state is resumed may be increased.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (14)
1. A voltage control circuit, comprising:
the band-gap reference circuit is characterized in that an enabling end of the band-gap reference circuit is connected with a wake-up enabling signal, and an output end of the band-gap reference circuit is used for outputting reference voltage;
the reference end of the voltage stabilizer is connected with the output end of the band-gap reference circuit, the control end of the voltage stabilizer is connected with the awakening enabling signal, and the output end of the voltage stabilizer can output a voltage stabilizing signal according to the reference voltage and the awakening enabling signal;
the reference end of the charge pump is connected with the output end of the band-gap reference circuit, the control end of the charge pump is connected with the awakening enabling signal, and the output end of the charge pump can output a high-voltage signal according to the reference voltage and the awakening enabling signal;
the enabling end of the oscillating circuit is connected with a wake-up enabling signal, and under the action of the wake-up enabling signal, the oscillating circuit generates a clock signal to the charge pump;
the enabling circuit is used for acquiring a voltage value of a voltage stabilizing signal and a voltage value of a high voltage signal, judging whether the voltage value of the voltage stabilizing signal is lower than a first threshold voltage, judging whether the voltage value of the high voltage signal is lower than a second threshold voltage, and outputting a wake-up enabling signal according to a judgment result; if the voltage value of the voltage stabilizing signal is lower than or equal to a first threshold voltage, the awakening enabling signal output by the enabling circuit can awaken the voltage stabilizer; if the voltage value of the high-voltage signal is lower than or equal to a second threshold voltage, the awakening enabling signal output by the enabling circuit can awaken the charge pump;
the enabling circuit includes: an OR gate; the first detector is used for outputting a first enabling signal to an OR gate according to a voltage stabilizing signal at the output end of the voltage stabilizer;
the second detector is used for outputting a second enabling signal to an OR gate according to the voltage signal at the output end of the charge pump;
the OR gate outputs a wakeup enable signal according to the first enable signal and the second enable signal;
the wake-up enabling signal comprises a high level signal and a low level signal which are alternately appeared;
when the first enabling signal and/or the second enabling signal are/is a high-level signal, the awakening enabling signal is a high-level signal; and when the first enabling signal and the second enabling signal are low-level signals, the awakening enabling signal is a low-level signal.
2. The voltage control circuit of claim 1, wherein the first enable signal comprises a high level signal and a low level signal that alternate.
3. The voltage control circuit of claim 2, wherein the first enable signal is a high level signal when the voltage value of the regulated signal is less than or equal to a first threshold voltage, and the first enable signal is a low level signal when the voltage value of the regulated signal is greater than the first threshold voltage.
4. The voltage control circuit of claim 1, wherein the second enable signal comprises a high level signal and a low level signal that alternate.
5. The voltage control circuit of claim 4, wherein the second enable signal is a high level signal when the voltage value of the high voltage signal output by the charge pump is less than or equal to a second threshold voltage, and the second enable signal is a low level signal when the voltage value of the high voltage signal output by the charge pump is greater than the second threshold voltage.
6. The voltage control circuit of claim 1, further comprising:
the switch is arranged at the output end of the band-gap reference circuit, and the enabling end of the switch is connected with a wake-up enabling signal and used for outputting the reference voltage to the voltage stabilizer and the charge pump under the control of the wake-up enabling signal.
7. The voltage control circuit of claim 6, further comprising: and one end of the capacitor is connected with the output end of the switch, and the other end of the capacitor is grounded.
8. The voltage control circuit of claim 1, wherein in a standby state, the regulated signal includes alternating standby and wake-up phases;
in the standby stage, the voltage value of the voltage stabilizing signal gradually decreases until a first threshold voltage is reached;
in the awakening stage, the voltage value of the voltage stabilizing signal is charged according to the reference voltage control, and gradually rises from the first threshold voltage.
9. The voltage control circuit of claim 1, wherein in a standby state, the high voltage signal comprises standby phases and wake-up phases that occur alternately;
in the standby stage, the voltage value of the high-voltage signal gradually decreases until reaching a second threshold voltage;
and in the awakening stage, the voltage value of the high-voltage signal controls charging according to the reference voltage and the clock signal, so that the voltage value of the voltage-stabilizing signal gradually rises from a second threshold voltage.
10. A voltage control method using the voltage control circuit according to any one of claims 1 to 9, comprising at least the steps of:
causing the voltage control circuit of any one of claims 1 to 9 to enter a standby state such that the voltage value of the regulated signal and the voltage value of the high voltage signal are gradually decreased;
determining that the voltage value of the voltage stabilization signal is reduced to a first threshold voltage, and waking up an enable signal to jump into a high-level signal, so that the voltage value of the voltage stabilization signal is charged and increased under the control of a reference voltage;
the voltage value of the voltage stabilization signal is enabled to continuously decrease;
determining that the voltage value of the high voltage signal is reduced to a second threshold voltage, and enabling a wake-up enabling signal to jump into a high level signal, so that the voltage value of the high voltage signal is charged and increased under the control of a reference voltage;
so that the voltage value of the high voltage signal continues to drop.
11. The voltage control method of claim 10, wherein the determining that the voltage value of the regulated signal has decreased to the first threshold voltage causes the first enable signal to transition to a high level signal.
12. The voltage control method of claim 10, wherein the step of causing the voltage value of the regulated signal to be charged up under the control of the reference voltage causes the first enable signal to jump to a low level signal and the voltage value of the regulated signal to continue to decrease until the voltage value of the regulated signal is charged up to the first predetermined wake-up voltage value.
13. The voltage control method of claim 10, wherein the determining that the voltage value of the high voltage signal decreases to the second threshold voltage causes the second enable signal to transition to a high level signal.
14. The voltage control method of claim 10, wherein the step of causing the voltage value of the high voltage signal to be charged up under the control of the reference voltage and the clock signal until the voltage value of the high voltage signal is charged up to a second preset wake-up voltage value causes the second enable signal to jump to a low level signal, and the voltage value of the high voltage signal continues to decrease.
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| CN101944527B (en) * | 2009-07-08 | 2012-11-21 | 炬才微电子（深圳）有限公司 | Integrated circuit and standby controlling method thereof |
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