CN111769158B - 一种具低反向恢复电荷的双沟道超结vdmos器件及制造方法 - Google Patents
一种具低反向恢复电荷的双沟道超结vdmos器件及制造方法 Download PDFInfo
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Abstract
本发明公开了一种具低反向恢复电荷的双沟道超结VDMOS器件及制造方法,分别在栅电极区和JFET区上方建立源电极,JFET上方依次新建立N‑pillar区、P‑body区和N+源区,使得器件的栅电极被分成多区域,新加入的区、源极和栅极将整个栅极分离,形成了一个分离栅极,增加了一个源电极。本发明在保持超结VDMOS击穿电压和开态电流处理能力的同时,降低了体内寄生二极管的储存电荷,提高了器件的反向恢复特性。
Description
技术领域
本发明涉及一种电子器件及制造方法,特别是涉及一种具低反向恢复电荷的双沟道超结VDMOS器件及制造方法。
背景技术
超结VDMOS是中高压领域的一种十分重要的功率器件,如图1所示,其基本结构由交替排列的P柱(P-pillar)和N柱(N-pillar)组成漂移区,且遵循电荷平衡的基本原理,在硅极限限制下突破了传统结构的限制(Ron-BV),降低了导通电阻,这种降低的电阻伴随增强的电流饱和能力,使超级结VDMOS对PWM和电机控制应用特别具有吸引。
然而,和传统的VDMOS器件类似,超结VDMOS器件也存在一个大的寄生体二极管,当在***电路应用出现反向偏压的情况,即源极(source)接高电位,漏极(drain)接低电位,栅极(gate)接零电位时,这个寄生的体二极管就会开始工作,通常把这种工作模式称为超结VDMOS的反向导通状态,如图2(a)所示,当P-body/N-漂移区的电势差大于常规PN结内建电势(约0.7V)时,P-body与P-pillar向漂移区中发射空穴,此时衬底(N+sub)接低电位,空穴在电场作用下流向漏极。为了保持漂移区中的电中性,与此同时N+衬底也开始向漂移区中发射电子,空穴和电子在漂移区内发生电导调制效应,使得漂移区中的电阻迅速下降,也即反向导通压降很低。由于超结P柱区的引入,在发生空穴注入时,发射效率会有所增强,也就是说超结器件反向导通时注入到N-pillar漂移区,即N柱区的空穴远多于传统VDMOS注入到N-pillar漂移区的空穴。
超结VDMOS反向恢复过程实质是体二极管的关断过程,该过程如图3所示,当二极管从反向导通状态向反向截止状态过渡时,需要首先释放存储在漂移区中的剩余载流子(Qrr),这个过程需要一段时间称为放电时间也即反向恢复时间(Trr),如图2(b)所示,在此期间电流反向流过二极管,空穴在漏极高压电场作用下,被排斥到P-body阱区,最后从源极处流出,电子在漏极高压电场作用下,被吸引到N+sub衬底,最后从漏极流出,这个过程直到漂移区中的空穴被抽取完全为止。由于超结VDMOS反向导通时注入器件超结N柱中的空穴电子对远多于传统的VDMOS,超结VDMOS在反向恢复抽取过剩载流子的过程中会损耗更多能量。
发明内容
发明目的:本发明的目的之一是提供一种具低反向恢复电荷的双沟道超结VDMOS器件,减少了超结VDMOS器件的反向恢复电荷,提高器件的反向恢复特性;本发明的目的之二是提供该具低反向恢复电荷的双沟道超结VDMOS器件的制造方法。
技术方案:本发明的具低反向恢复电荷的双沟道超结VDMOS器件包括漏电极,N型重掺杂的漏电极欧姆接触层,交替分布构成漂移区的N型柱区与P型柱区,P型轻掺杂的体(P-body)区,源电极,源电极欧姆接触区重掺杂N+区,源电极增强对P-base区势垒耦合的薄氧化层,栅电极,栅氧化层;与右侧栅氧化层对应的较薄的左侧氧化层;构成纵向沟道的P-base区,源电极欧姆接触区N+层,向上延伸的N-pillar区,纵向栅氧化层,场氧化层。
即:包括漏电极、重掺杂半导体衬底、位于重掺杂半导体衬底上表面的第一N型柱区与P型柱区,第一N型柱区与P型柱区交替分布构成漂移区;第一N型柱区顶部两侧分别设有一个P-body区,P-body区分别与第一N型柱区、P型柱区相接触,每个P-body区中分别设有一个第一重掺杂N+区;
第一N型柱区的上方设有依次层叠的第二N型柱区、P-base区和第二重掺杂N+区,第二N型柱区、P-base区、第二重掺杂N+区形成层叠结构;该层叠结构的一侧设有栅氧化层,另一侧设有沿纵向的第一薄氧化层;栅氧化层的下表面与部分第一N型柱区、部分P-body区、部分第一重掺杂N+区相接触;第一薄氧化层远离层叠结构的一侧设有第二薄氧化层,第二薄氧化层与部分第一N型柱区、部分P-body区相接触;第二薄氧化层远离第一薄氧化层的一侧设有场氧化层,场氧化层与部分第一重掺杂N+区相接触;
栅电极埋设于栅氧化层内,栅电极位于P-body区上方且覆盖P-body区,并使得栅电极靠近层叠结构一侧的纵向栅氧化层的宽度与栅电极下方的栅氧化层的厚度相同,栅电极的下表面低于P-base区的下表面或与其齐平,且栅电极的高度高于P-base区;第一薄氧化层和第二薄氧化层的厚度相同,且厚度小于纵向栅氧化层的宽度;
源电极设于器件表面,源电极与部分第一重掺杂N+区和P-body区的上表面、场氧化层的两侧面和上表面、栅氧化层的一侧面和上表面、第二薄氧化层的上表面、第一薄氧化层的一侧面相接触。
其中,场氧化层的高度与层叠结构的高度可相同,也可不相同;栅电极的左右位置P-body区的上方,并且能够覆盖P-body区;栅电极的下表面和P-base区的下表面相平齐或位于P-base区侧下方。
优选地,所述第二N型柱区和第一N型柱区具有相同的掺杂浓度,且第二N型柱区的厚度是可调节的。
JFET区上面为向上延伸的N-Pillar区(第二N型柱区),该区域与常规超结VDMOS的N型轻掺杂区域(第一N型柱区)性质一致,保证栅极控制的两个MOS结构开启电压电压大小一致,超结VDMOS反向导通阶段的开启电压小于寄生体二极管的开启电压。同时向上延伸的N-pillar区的厚度影响超结VDMOS的导通电阻,N-pillar区的厚度对导通电阻的影响随着厚度的增加而增强,进而可以适当调节N-pillar区的厚度以优化导通电阻。
优选地,所述P-base区和P-body区具有相同的掺杂浓度,第二N型柱区、P-base区具有一致的区域宽度。
向上延伸的N-Pillar区(第二N型柱区)上面为P-base区,该区域与常规超结VDMOS的体(P-body)区性质一致,进而保证栅极控制的两个MOS结构正向开启电压的大小一致,超结VDMOS反向导通阶段的开启电压小于寄生体二极管的开启电压;该区域的厚度使双沟道结构在耐压时不会发生穿通击穿现象,进而可以适当调节P-base区的厚度。
优选地,所述第二重掺杂N+区和第一重掺杂N+区具有相同的掺杂浓度。第二重掺杂N+区与常规超结VDMOS的N型重掺杂区性质一致,该区域为器件导通阶段提供电子,进而可以适当调节第二重掺杂N+区的厚度。
优选地,第二薄氧化层和纵向栅氧化层的厚度是可调节的。适当调节左侧氧化层(第二薄氧化层)的厚度,使超结VDMOS反向导通时左侧氧化层下方的P-body/N-pillar结的开启电压小于常规体二极管的开启电压。
所述栅电极与向上延伸的N-pillar区(第二N型柱区)、P-base区之间的栅氧化层厚度影响超结VDMOS开启电压,纵向栅氧化层的厚度可以调节。
可选的,栅氧化层选用二氧化硅。
优选地,第二N型柱区、P-base区、第二重掺杂N+区三者的宽度相同。
其中,所述器件的重掺杂半导体衬底为N型或P型;如重掺杂半导体衬底为P型则为IGBT器件。
本发明还提供了所述具低反向恢复电荷的双沟道超结VDMOS器件的制造方法,包括如下步骤:
(1)在重掺杂半导体衬底上外延与第一N型柱区掺杂浓度相同的薄膜,在薄膜上刻蚀P型柱区沟槽,再采用多次外延或填充的方法形成P型柱区;
(2)通过离子注入或扩散的方法形成P-body区,通过离子注入或扩散的方法形成第一重掺杂N+区;
(3)氧化形成场氧化层,刻蚀出栅电极窗口,形成栅氧化层、纵向栅氧化层,淀积形成栅电极;
(4)将场氧化层刻蚀出第二N型柱区外延窗口,外延形成第二N型柱区、P-base区,离子注入形成第二重掺杂N+区;
(5)刻蚀出源电极窗口,形成第一薄氧化层和第二薄氧化层,金属化形成源电极;
(6)背面金属化形成漏电极。
发明原理:本发明是一种改变一端反向导通路径并建立另外一条正向导通路径,优化超结VDMOS反向恢复特性的器件;本发明相比于传统结构的超结器件,提出的双沟道结构分别在栅极区域和JFET区上方建立源极,JFET上方依次新建立N-pillar区、P-body区和N+源区,该新建区域与新建立的源极形成了两个源极控制的MOS结构;器件通过控制源极接触区域的二氧化硅层厚度调制临近的PN结的势垒高度,进而改变反向导通时的开启电压,使反向电流优先通过源控MOS区,减小了N-pillar区域的电子对P+pody、P-pillar区域的注入;同时新建立的区域又与栅极形成了另外一个MOS结构,在一个栅极区域建立了两个栅控MOS,作为超结VDMOS正向导通的导通路径,增加了双通路结构的正向导通电路路径,提升了器件的饱和电流特性。
常规超结VDMOS存在大冶金结面积的内部寄生二极管,所以开态时会存储大量过剩载流子,使得开关过程中功耗增大。本发明通过引入一个新的纵向沟道,结合减小一个横向常规沟道氧化层的厚度,减少过剩载流子的存储;一方面获得了较小的发向回复电荷,另一方面保持了新结构的饱和电流能力。
本发明的中的双通路结构通过控制新建源极接触区二氧化硅层厚度来改变器件反向导通时的开启电压大小,开启电压的变化使优先通过通过N-pillar漂移区的电流大小随着二氧化硅层厚度的改变而改变,进而减小N-pillar漂移区内电子对P-body与P-pillar区域的注入,减小漂移区内的存储电荷;同时栅极区域与新加入的区域建立了新正向导通路径,该结构在提升超结VDMOS体二极管反向恢复特性的同时,对双通路结构的正向导通路径进行了优化,提升器件的饱和电流特性。
有益效果:本发明的超结结构优化了现有技术中超结VDMOS存在的器件反向恢复存储电荷的技术问题,相比常规结构,减少了超结VDMOS器件的反向恢复电荷;本发明中的新结构在保持超结VDMOS击穿电压和开态电流处理能力的同时,降低了体内寄生二极管的储存电荷,进而提高器件的反向恢复特性。本发明可应用于对开关速度和电能转换效率要求比较高的应用领域,如电源适配器,LED、LCD、PDP驱动,工业控制、汽车电子等领域。
附图说明
图1是常规超结VDMOS结构;
图2是超结VDMOS反向恢复阶段电子与空穴运动轨迹,其中图2(a)为体二极管正偏,图2(b)为体二极管反偏;
图3是超结VDMOS反向恢复输出特性曲线示意图;
图4是一种具有低反向恢复电荷的双沟道超级结VDMOS结构;
图5是两种结构的关断电流与时间的关系对比曲线图。
具体实施方式
下面结合实施例对本发明进一步地详细描述。
实施例1:
本实施例中的重掺杂半导体衬底以N型为例。
该具有低反向恢复电荷的双沟道超级结VDMOS结构包括漏电极11、N型重掺杂半导体衬底12、交替分布构成漂移区的第一N型柱区13与P型柱区14、P-body区15、第一重掺杂N+区16、源电极17、栅氧化层18、栅电极19、第二N型柱区20、构成纵向沟道的P-base区21、第二重掺杂N+区22、第一薄氧化层23、第二薄氧化层24、纵向栅氧化层25、场氧化层26;
其中,N型重掺杂半导体衬底12为N型重掺杂的漏电极欧姆接触层;第一重掺杂N+区16为与源电极17欧姆接触的重掺杂N+区;第二N型柱区20为向上延伸的N-pillar区第二重掺杂N+区22为与源电极17欧姆接触的重掺杂N+区,第一薄氧化层23为源电极17增强对P-base区21势垒耦合的薄氧化层,第二薄氧化层24为与图4中位于右侧的栅氧化层18对应的较薄的左侧氧化层。
如图4所示,该器件底部为N型重掺杂半导体衬底12,N型重掺杂半导体衬底12的下表面设有漏电极11,上表面设有第一N型柱区(N-pillar)13与P型柱区(P-pillar)14,第一N型柱区13与P型柱区14交替分布构成漂移区;第一N型柱区13顶部左右两侧分别设有一个P-body区15,P-body区15分别与第一N型柱区13、P型柱区14相接触,每个P-body区15中分别设有一个第一重掺杂N+区16;
第一N型柱区13的上方设有依次层叠的第二N型柱区(N-pillar)20、P-base区21和第二重掺杂N+区22,第二N型柱区20、P-base区21和第二重掺杂N+区22形成层叠结构;该层叠结构的右侧设有栅氧化层18,左侧设有沿纵向设置的第一薄氧化层23,且栅氧化层18的左侧面与层叠结构的右侧面相接触,第一薄氧化层23的右侧面与层叠结构的左侧面相接触。
其中,栅氧化层18的下表面与部分第一N型柱区13、P-body区15的左侧部分、部分第一重掺杂N+区16相接触,此处的P-body区15和第一重掺杂N+区16位于器件的右侧。
第一薄氧化层23远离层叠结构的一侧(即左侧)设有沿横向的第二薄氧化层24,第二薄氧化层24与部分第一N型柱区13、P-body区15的右侧部分、部分第一重掺杂N+区16相接触,此处的P-body区15和第一重掺杂N+区16位于器件的左侧。
第二薄氧化层24远离第一薄氧化层23的一侧(即左侧)设有场氧化层26,场氧化层26与部分第一重掺杂N+区16相接触;
栅电极19埋设于栅氧化层18内且位于右侧P-body区15的上方,并能够覆盖P-body区15,且使得栅电极19靠近层叠结构一侧的纵向栅氧化层25的宽度与栅电极19下方的栅氧化层18的厚度相同,且栅电极19的垂直高度高于P-base区21的垂直高度,栅电极19上表面的高度高于P-base区21的上表面,栅电极19的下表面与P-base区21的下表面齐平;
并且,第一薄氧化层23和第二薄氧化层24的厚度相同,且两者的厚度小于纵向栅氧化层25的宽度;第二薄氧化层24的两侧面分别与部分第一薄氧化层23和部分场氧化层26相接触。
源电极17覆盖于器件的上表面,源电极17与部分第一重掺杂N+区16和P-body区15的上表面、场氧化层26的左右两侧面和上表面、栅氧化层18的右侧面和上表面、第二薄氧化层24的上表面、第一薄氧化层23的左侧面相接触。
如图5所示,可以看出新结构的最大反向恢复电流小于常规结构。
本实施例中的超结功率器件,具有正向双沟道导通路径,其一为P-base区21与纵向栅氧化层25构成的纵向沟道,其二为P-body区与栅氧化层18构成的横向沟道。
该超结功率器件具有反向三沟道导通路径,其一为位于左侧的第一重掺杂N+区(N+层)16、P-body区15、第一N型柱区(N-pillar柱区)13、N型重掺杂半导体衬底(N+衬底)12;其二为第二重掺杂N+区(N+层)22、P-base区21、第二N型柱区(向上延伸的N-pillar区)20、第一N型柱区(N-pillar柱区)13、N型重掺杂半导体衬底(N+衬底)12;其三为位于右侧的第一重掺杂N+区(N+层)16、P-body区15、第一N型柱区(N-pillar柱区)13、N型重掺杂半导体衬底(N+衬底)12。路径一和路径二的区别在于第二薄氧化层24和栅氧化层18的厚度不一样,冶金结面势垒高度也不同。
与传统的超结VDMOS器件相比,本发明的结构提出的双沟道结构分别在栅电极区和JFET区上方建立源电极,JFET上方依次新建立N-pillar区、P-body区和N+源区,使得器件的栅电极被分成多区域,如图4所示,新加入的区、源极和栅极将整个栅极分离,形成了一个分离栅极,增加了一个源电极。
本发明的新结构在保持超结VDMOS击穿电压和开态电流处理能力的同时,降低了体内寄生二极管的储存电荷,提高了器件的反向恢复特性。该具有低反向恢复电荷的双沟道超结VDMOS器件的创新之处在于:
(1)新结构的左侧栅氧化层24厚度较常规器件薄,且将源电极17引向薄氧化层24上方,薄的氧化层24增强了源电极17对P-body/N-pillar(即15/13)结势垒高度的调制,降低了PN结势垒高度,使得少子通过冶金结面变得更为困难,从而降低了P-body区15和N-pillar区13储存的载流子,进而降低反向恢复电荷;
(2)纵向第一薄氧化层23也加强了源电极对P-base/N+结势垒高度的调制,降低反向恢复电荷;
(3)纵向栅氧化层25与P-base区21构成的纵向沟道在开态时为器件提供新的电流沟道,保持了新结构的电流饱和能力。
实施例2:
本实施例为具有低反向恢复电荷的双沟道超级结VDMOS结构的制造方法,包括如下步骤:
(1)在重掺杂半导体衬底(N型或P型)12上外延与第一N型柱区13掺杂浓度相同的薄膜,在薄膜上刻蚀P型柱区14沟槽,再采用多次外延或填充的方法形成P型柱区14;
(2)通过离子注入或扩散的方法形成P-body区15,通过离子注入或扩散的方法形成第一重掺杂N+区16;
(3)氧化形成场氧化层26,刻蚀出栅电极19窗口,形成栅氧化层18、纵向栅氧化层25,淀积形成栅电极19;
(4)将场氧化层26刻蚀出第二N型柱区20外延窗口,外延形成第二N型柱区20、P-base区21,离子注入形成第二重掺杂N+区22;
(5)刻蚀出源电极17窗口,形成第一薄氧化层23和第二薄氧化层24,金属化形成源电极17;
(6)背面金属化形成漏电极11。
Claims (8)
1.一种具低反向恢复电荷的双沟道超结VDMOS器件,其特征在于:包括漏电极(11)、重掺杂半导体衬底(12)、位于重掺杂半导体衬底上表面的第一N型柱区(13)与P型柱区(14),第一N型柱区(13)与P型柱区(14)交替分布构成漂移区;第一N型柱区(13)顶部两侧分别设有一个P-body区(15),P-body区(15)分别与第一N型柱区(13)、P型柱区(14)相接触,每个P-body区(15)中分别设有一个第一重掺杂N+区(16);第一N型柱区(13)的上方设有依次层叠的第二N型柱区(20)、P-base区(21)和第二重掺杂N+区(22),第二N型柱区(20)、P-base区(21)、第二重掺杂N+区(22)形成层叠结构;该层叠结构的一侧设有栅氧化层(18),另一侧设有沿纵向的第一薄氧化层(23);
栅氧化层(18)的下表面与部分第一N型柱区(13)、部分P-body区(15)、部分第一重掺杂N+区(16)相接触;第一薄氧化层(23)远离层叠结构的一侧设有第二薄氧化层(24),第二薄氧化层(24)与部分第一N型柱区(13)、部分P-body区(15)相接触;第二薄氧化层(24)远离第一薄氧化层(23)的一侧设有场氧化层(26),场氧化层(26)与部分第一重掺杂N+区(16)相接触;栅电极(19)埋设于栅氧化层(18)内,栅电极(19)位于P-body区(15)上方且覆盖P-body区(15),并使得栅电极(19)靠近层叠结构一侧的纵向栅氧化层(25)的宽度与栅电极(19)下方的栅氧化层(18)的厚度相同,且栅电极(19)的高度高于P-base区(21);第一薄氧化层(23)和第二薄氧化层(24)的厚度相同,且厚度小于纵向栅氧化层(25)的宽度;源电极(17)设于器件表面,源电极(17)与部分第一重掺杂N+区(16)和P-body区(15)的上表面、场氧化层(26)的两侧面和上表面、栅氧化层(18)的一侧面和上表面、第二薄氧化层(24)的上表面、第一薄氧化层(23)的一侧面相接触。
2.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:所述第二N型柱区(20)和第一N型柱区(13)具有相同的掺杂浓度,第二N型柱区(20)的厚度是可调节的。
3.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:所述P-base区(21)和P-body区(15)具有相同的掺杂浓度,P-base区(21)的厚度是可调节的。
4.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:所述第二重掺杂N+区(22)和第一重掺杂N+区(16)具有相同的掺杂浓度,第二重掺杂N+区(22)的厚度是可调节的。
5.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:第二薄氧化层(24)和纵向栅氧化层(25)的厚度是可调节的。
6.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:第二N型柱区(20)、P-base区(21)、第二重掺杂N+区(22)三者的宽度相同。
7.根据权利要求1所述的双沟道超结VDMOS器件,其特征在于:所述重掺杂半导体衬底(12)为N型或P型。
8.一种权利要求1~7任一项所述的双沟道超结VDMOS器件的制造方法,其特征在于包括如下步骤:
(1)在重掺杂半导体衬底(12)上外延与第一N型柱区(13)掺杂浓度相同的薄膜,在薄膜上刻蚀P型柱区(14)沟槽,再采用多次外延或填充的方法形成P型柱区(14);
(2)通过离子注入或扩散的方法形成P-body区(15),通过离子注入或扩散的方法形成第一重掺杂N+区(16);
(3)氧化形成场氧化层(26),刻蚀出栅电极(19)窗口,形成栅氧化层(18)、纵向栅氧化层(25),淀积形成栅电极(19);
(4)将场氧化层(26)刻蚀出第二N型柱区(20)外延窗口,外延形成第二N型柱区(20)、P-base区(21),离子注入形成第二重掺杂N+区(22);
(5)刻蚀出源电极(17)窗口,形成第一薄氧化层(23)和第二薄氧化层(24),金属化形成源电极(17);
(6)背面金属化形成漏电极(11)。
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