CN111769115B

CN111769115B - Three-dimensional memory structure and preparation method thereof

Info

Publication number: CN111769115B
Application number: CN202010540077.3A
Authority: CN
Inventors: 张坤; 王迪; 夏志良; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-06-11
Filing date: 2020-06-11
Publication date: 2021-04-06
Anticipated expiration: 2040-06-11
Also published as: CN111769115A; CN113097215B; CN113097215A

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof, wherein in the preparation process of the three-dimensional memory structure, a step region is divided into a first connection region, a second connection region and a third connection region along a second direction, the second connection region is divided into two step subareas along the second direction, an etching buffer layer is formed on the surface of a sacrificial layer of a stacked structure exposed by the top surfaces of the steps of the two step subareas, a contact hole is formed in the step region with the etching buffer layer, the sacrificial layer positioned in the middle of the second connection region is reserved when the sacrificial layer of the stacked structure is replaced by a grid conductive material, and the grid conductive material is ensured to be electrically connected with the etching buffer layer at the edge of the second connection region, so that a connecting column in the contact hole can be electrically connected with a grid layer through the etching buffer layer. The invention can reduce the process difficulty of the step area contact hole etching and eliminate the risk of word line bridging of different layers during the contact hole etching.

Description

Three-dimensional memory structure and preparation method thereof

Technical Field

The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a three-dimensional memory structure and a preparation method thereof.

Background

Generally, a three-dimensional memory includes a gate stack structure formed by alternately stacking gate layers and interlayer dielectric layers, and a connection stud (CT) electrically connected to a gate in a step region of the gate stack structure. However, in the actual manufacturing process of the three-dimensional memory, in order to achieve a good electrical connection between the connection post and the gate layer in the stacked structure, a contact hole needs to be etched in the dielectric layer covering the gate stack structure until the contact hole exposes the surface of the gate layer in the step region, and then the contact hole is filled with the metal material for forming the connection post.

However, as the integration degree of 3D NAND is higher and higher, the 3D NAND memory has been developed from 32 layers to 64 layers, and the number of layers is even higher, the depth of the contact hole is deeper and deeper, and the requirement for the etching process of the contact hole is more and more strict, during the process of forming the contact hole by etching, a gate layer breakdown (Punch) is easily caused, so that the contact hole penetrates through an interlayer dielectric layer between two adjacent gate layers, in this case, after filling a metal material for forming a connection pillar in the contact hole, a short circuit between different gate layers is caused, that is, Word Line bridging (Word Line Bridge) of different layers is caused, so that a control error on a memory cell is caused, and a memory failure is caused.

Therefore, it is necessary to provide a three-dimensional memory structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for fabricating the same, which are used to solve the technical problem that in the conventional 3D NAND fabrication process, when a contact hole is formed by etching, a gate layer is easily broken down, and thus, when a connection stud is formed in the contact hole, short circuits between different gate layers are caused.

In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a three-dimensional memory structure, including:

providing a semiconductor substrate;

sequentially forming an epitaxial sacrificial layer and a stacked structure on the semiconductor substrate, wherein the stacked structure comprises an interlayer dielectric layer and a sacrificial layer which are alternately stacked, the stacked structure comprises a core region and a step region which are sequentially arranged along a first direction, the step region comprises a first connecting region, a second connecting region and a third connecting region which are sequentially arranged along a second direction, and the second connecting region comprises a first step partition and a second step partition which are sequentially arranged along the second direction;

forming a stepped groove extending along the first direction in the second connection region of the stepped region, wherein the stepped groove includes a plurality of first steps and a plurality of second steps, the first steps are located in the first step partitions, the second steps are located in the second step partitions, and top surfaces of the first steps and the second steps of the same level respectively expose surfaces of the sacrificial layers located on different layers in a direction from the stacked structure to the semiconductor substrate;

forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step;

forming contact holes in the stepped region in which the etching buffer layer is formed, the contact holes exposing the etching buffer layer or penetrating the etching buffer layer, wherein the contact holes are respectively located in the first step partition and the second step partition of the second connection region of the stepped region;

filling a hole sacrificial layer in at least part of the contact hole, wherein at least one contact hole filled with the hole sacrificial layer exists in the first step partition and the second step partition;

forming a grid line isolation groove penetrating through the stacked structure in the stacked structure, wherein the epitaxial sacrificial layer is exposed out of the grid line isolation groove;

removing the sacrificial layer in the stack structure based on the gate line isolation groove to form a gate gap exposing a portion of an end of the etch buffer layer, and the sacrificial layer at a middle of a second connection region of the stepped region being left;

forming a gate conductive portion in the gate gap, wherein the gate conductive portion is connected to the etch buffer layer;

replacing the hole-filling sacrificial layer in the contact hole with a conductive material to form a connection post.

In an optional embodiment, a vertical channel structure is formed in the core region, and the vertical channel structure includes a functional sidewall layer and a channel layer which are sequentially arranged from outside to inside along a radial direction; the step of removing the sacrificial layer in the stacked structure based on the gate line isolation groove to form a gate gap further comprises a step of removing the epitaxial sacrificial layer based on the gate line isolation groove to form an epitaxial gap and forming an epitaxial layer in the epitaxial gap.

In an optional embodiment, the step of removing the epitaxial sacrificial layer based on the gate line isolation trench to form an epitaxial gap, and forming an epitaxial layer in the epitaxial gap comprises:

forming a side wall protective layer on the side wall of the grid line isolation groove;

and removing the epitaxial sacrificial layer and the functional side wall layer of the vertical channel structure at the part surrounded by the epitaxial sacrificial layer on the basis of the grid line isolation groove formed with the side wall protection layer to form the epitaxial gap.

In an optional embodiment, the step of forming the sidewall protection layer on the sidewall of the gate line isolation trench includes sequentially forming a sidewall protection layer composed of a nitride layer, an oxide layer and a nitride layer on the sidewall of the gate line isolation trench.

In an optional embodiment, the vertical channel structure further includes a high-k dielectric layer surrounding the functional sidewall layer.

In an alternative embodiment, the step of forming a contact hole in the stepped region in which the etch buffer layer is formed includes:

and forming a dummy channel hole and the contact hole in the stepped region in which the etching buffer layer is formed, wherein the dummy channel hole sequentially penetrates through the stacked structure and the epitaxial sacrificial layer at the first connection region and/or the third connection region, and the dummy channel hole is located at the first connection region and the third connection region of the stepped region.

In an alternative embodiment, the step of filling the hole sacrificial layer in at least a portion of the contact hole includes:

forming a side wall oxide layer on the side wall surface of the epitaxial sacrificial layer exposed by the pseudo channel hole and the side wall surface of the semiconductor substrate;

filling a hole sacrificial layer in at least part of the contact holes, and filling a hole oxide layer in the pseudo channel holes with the side wall oxide layers and the contact holes without the hole sacrificial layer, wherein the hole sacrificial layer is respectively used as a pseudo channel structure and a pseudo connecting column.

In an alternative embodiment, the step of forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step includes,

forming a side wall spacing layer on the side wall of the stepped groove;

and forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step formed with the side wall spacer.

In an alternative embodiment, the material of the sidewall spacers comprises silicon oxide.

In an optional embodiment, after the step of forming the gate layer in the gate gap, a step of filling an isolation trench filling layer in the gate line isolation trench is further included.

In an alternative embodiment, the material of the isolation trench filling layer comprises silicon nitride or silicon oxide.

In an alternative embodiment, the step of replacing the hole-filling sacrificial layer in the contact hole with a conductive material to form a connection post further comprises a step of forming a first plug on top of the connection post.

In an alternative embodiment, the step of forming a connection stud by replacing the hole-filling sacrificial layer in the contact hole with a conductive material further comprises a step of forming a second plug on top of the vertical channel structure.

In an alternative embodiment, the material of the gate conductive portion comprises a titanium nitride and tungsten composite layer.

In an alternative embodiment, the material of the connecting stud comprises a composite layer of titanium nitride and tungsten.

In an optional embodiment, in the step of forming a contact hole in the step region where the etching buffer layer is formed, a step of forming a doped well contact hole in the step region is further included, and the doped well contact hole exposes a doped well in the semiconductor substrate;

in the step of replacing the hole-filling sacrificial layer in the contact hole with a conductive material to form a connection post, a doped well connection post is also formed in the doped well contact hole.

In an optional embodiment, the step of forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step includes:

forming a polycrystalline silicon layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step;

and forming a metal layer on the surface of the polycrystalline silicon layer, wherein the metal layer and the polycrystalline silicon layer form a silicon metal alloy which is used as the etching buffer layer.

In an optional embodiment, the forming a metal layer on the surface of the polysilicon layer, the metal layer forming a silicon metal alloy with the polysilicon layer, the step of using the silicon metal alloy as the etching buffer layer includes:

forming a metal layer on the surface of the polycrystalline silicon layer;

and carrying out annealing treatment to enable the metal layer and the polycrystalline silicon layer to form a silicon metal alloy, wherein the silicon metal alloy is used as the etching buffer layer.

In an alternative embodiment, the temperature of the annealing treatment is between 400-1100 ℃, and the annealing time is between 1-20 min.

In an alternative embodiment, the material of the metal layer includes one or a combination of at least two of cobalt, nickel, and platinum.

To achieve the above and other related objects, the present invention also provides a three-dimensional memory structure, comprising:

a semiconductor substrate;

the semiconductor device comprises a semiconductor substrate, a gate stack structure and a plurality of gate layers, wherein the semiconductor substrate is provided with the gate stack structure, the gate stack structure comprises an interlayer dielectric layer and the gate layers which are alternately stacked, the gate stack structure comprises a core region and a step region which are sequentially arranged along a first direction, the step region comprises a first connecting region, a second connecting region and a third connecting region which are sequentially arranged along a second direction, the second connecting region comprises a first step partition and a second step partition which are sequentially arranged along the second direction, each gate layer comprises a gate insulating part positioned in the middle of the second connecting region and a gate conducting part surrounding the gate insulating part, and the first direction is not parallel to the second direction;

the first steps are located in the first step subareas, the second steps are located in the second step subareas, and the top surfaces of the first steps and the second steps of the same level respectively expose the surfaces of the gate insulating parts and the surfaces of partial gate conducting parts of the gate layers located on different layers in the direction from the gate laminated structure to the semiconductor substrate;

an etching buffer layer formed on the surface of the gate insulating part of the gate layer and the surface of a part of the gate conductive part exposed by the top surfaces of the first step and the second step;

the connecting columns are formed on the etching buffer layer, one ends of the connecting columns, which are close to the semiconductor substrate, are in contact with the etching buffer layer or penetrate through the etching buffer layer, the projections of the connecting columns on the grid layer are located in the grid insulating part, and at least one connecting column exists in the first step partition and the second step partition.

In an optional embodiment, a vertical channel structure is disposed in the core region, the vertical channel structure penetrates through the gate stack structure, and the vertical channel structure includes a functional sidewall layer and a channel layer sequentially disposed from outside to inside in a radial direction.

In an optional embodiment, the three-dimensional memory structure further comprises a plurality of dummy channel structures and a plurality of dummy connection pillars; the dummy channel structure penetrates through the gate stack structure at the first connection region and/or the third connection region; the pseudo connecting column is formed on the etching buffer layer, and one end of the pseudo connecting column close to the semiconductor substrate is in contact with the etching buffer layer or penetrates through the etching buffer layer.

In an optional embodiment, the three-dimensional memory structure further includes a sidewall oxide layer, the dummy channel structure penetrates through the gate stack structure and extends into the semiconductor substrate, and the sidewall oxide layer is located between a sidewall of the dummy channel structure and the semiconductor substrate.

In an alternative embodiment, the three-dimensional memory structure includes a sidewall spacer formed on a sidewall of the first step in the first step partition and a sidewall of the second step in the second step partition.

In an optional embodiment, the three-dimensional memory structure further comprises an epitaxial layer disposed between the semiconductor substrate and the gate stack structure.

In an optional embodiment, the three-dimensional memory structure further comprises an isolation trench filling layer, the isolation trench filling layer penetrates through the gate stack structure, and the bottom of the isolation trench filling layer is in contact with the epitaxial layer.

In an alternative embodiment, the three-dimensional memory structure further comprises a plurality of first plugs formed on top of the connection pillars.

In an alternative embodiment, the three-dimensional memory structure further comprises a number of second plugs formed on top of the vertical channel structures.

In an alternative embodiment, the material of the gate conductive portion of the gate layer comprises a titanium nitride and tungsten composite layer.

In an alternative embodiment, the material of the connecting stud comprises a titanium nitride and tungsten composite layer.

In an alternative embodiment, the three-dimensional memory structure further comprises a doped well connection pillar located in the second connection region, and the doped well connection pillar is connected with a doped well in the semiconductor substrate.

In an alternative embodiment, the first direction is perpendicular to the second direction.

In an alternative embodiment, the etch buffer layer comprises a silicon metal alloy.

In the manufacturing process of the three-dimensional memory structure, the step region is divided into a first connection region, a second connection region and a third connection region along the second direction, the second connection region is divided into two step partitions along the second direction, and a silicon metal alloy (M) is formed on the surface of a sacrificial layer of the stacked structure exposed by the top surfaces of the steps of the two step partitions_xSi_y) The etching buffer layer is used for forming a contact hole in the stepped region formed with the etching buffer layer, when the sacrificial layer of the stacked structure is replaced by the grid conductive material, the sacrificial layer positioned in the middle of the second connection region is reserved, and the grid conductive material is ensured to be electrically connected with the etching buffer layer at the edge of the second connection region, so that the connecting column in the contact hole can be electrically connected with the grid layer through the etching buffer layer, and even if a Punch (Punch) condition occurs in the etching process of the contact hole, the connecting column formed in the contact hole can not cause Word Line bridging (Word Line Bridge) of different layers, so that the process difficulty of the stepped region contact hole etching can be reduced, the Word Line bridging (Word Line Bridge) of different layers caused by the Punch (Punch) occurring in the etching process of the contact hole can be eliminated, and the performance of the three-dimensional memory device can be improved;

in the three-dimensional memory structure and the preparation method thereof, the etching buffer layer is arranged, so that the etching of the contact hole and the pseudo channel hole can be completed by adopting the same mask and in the same etching step, thereby simplifying the process steps, reducing the etching difficulty of the contact hole and saving the cost.

Drawings

Fig. 1 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory structure according to the present invention.

FIG. 2 is a top view of the three-dimensional memory structure of the present invention.

Fig. 3 is a schematic cross-sectional view of a step trench extending along the first direction and formed in the second connection region of the step region in the preparation of the three-dimensional memory structure according to the present invention, wherein the step trench exposes an X-Y cross-section (corresponding to the X-Y cross-section in fig. 2) of the interlayer dielectric layer.

Fig. 4 is a cross-sectional view taken along line a-a in fig. 3 in the Y direction.

Fig. 5 is a schematic cross-sectional view of the cross-section X-Y (corresponding to the cross-section X-Y in fig. 2) of the three-dimensional memory structure according to the present invention, wherein the interlayer dielectric layer on the top surface of each step in the stepped trench is removed.

Fig. 6 is a cross-sectional view taken along line a-a in fig. 5 in the Y direction.

FIG. 7 is a schematic cross-sectional view in the X-Y direction of forming sidewall spacers on the sidewalls of the step trench in the fabrication of the three-dimensional memory structure of the present invention.

Fig. 8 is a cross-sectional view taken along line a-a in fig. 7 in the Y direction.

Fig. 9 is a schematic cross-sectional view in the X-Y direction of forming a polysilicon layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step in the preparation of the three-dimensional memory structure according to the invention.

Fig. 10 is a cross-sectional view taken along line a-a in fig. 9 in the Y direction.

Fig. 11 is a schematic cross-sectional view in the X-Y direction showing that a metal layer is formed on the surface of the polysilicon layer in the preparation of the three-dimensional memory structure of the present invention, and the metal layer and the polysilicon layer form a silicon metal alloy as the etching buffer layer.

Fig. 12 is a cross-sectional view taken along line a-a in fig. 11 in the Y direction.

Fig. 13 is a schematic cross-sectional view in the X-Y direction showing the formation of a contact hole in the step region where the etching buffer layer is formed and the formation of a sidewall oxide layer on the sidewall surface of the epitaxial sacrificial layer exposed by the dummy trench hole and the sidewall surface of the semiconductor substrate in the fabrication of the three-dimensional memory structure according to the present invention.

Fig. 14 is a cross-sectional view taken along line a-a in fig. 13 in the Y direction.

Fig. 15 is a schematic cross-sectional view taken along the Y direction of the line a-a in fig. 12 when sidewall oxide layers are formed on the sidewall surfaces of the epitaxial sacrificial layer and the semiconductor substrate exposed by the dummy trench hole in the preparation of the three-dimensional memory structure of the present invention.

FIG. 16 is a cross-sectional view of the contact hole and the dummy trench hole filled with a hole sacrificial layer in the three-dimensional memory structure according to the present invention (corresponding to the cross-sectional view of FIG. 2).

Fig. 17 is a cross-sectional view taken along line a-a in fig. 16 in the Y direction.

FIG. 18 is a cross-sectional view of a semiconductor structure of FIG. 16 having a patterned mask layer formed on the surface thereof in the fabrication of a three-dimensional memory structure according to the present invention.

FIG. 19 is a cross-sectional view of a three-dimensional memory structure according to the present invention in the Y-direction, wherein the dummy trench holes and a portion of the contact holes are etched away based on a patterned mask.

Fig. 20 is a schematic cross-sectional view of an X-Y cross-section (corresponding to the X-Y cross-section in fig. 2) of the dummy channel structure and the dummy connection stud respectively formed by removing the filling hole oxide layer in the dummy channel hole and the contact hole of the filling hole sacrificial layer in the three-dimensional memory structure according to the present invention.

Fig. 21 is a cross-sectional view of a gate line isolation trench penetrating through the stacked structure formed in the stacked structure in the fabrication of the three-dimensional memory structure according to the present invention (corresponding to the cross-sectional view of X-Y in fig. 2).

Fig. 22 is a schematic cross-sectional view of an X-Y cross-section (corresponding to the X-Y cross-section in fig. 2) of a sidewall protection layer formed on the sidewall of the gate line isolation trench in the fabrication of the three-dimensional memory structure according to the present invention.

Fig. 23 is a schematic cross-sectional view of an X-Y cross-section (corresponding to the X-Y cross-section in fig. 2) of the three-dimensional memory structure according to the present invention, wherein the epitaxial sacrificial layer is removed based on the gate line isolation trench to form an epitaxial gap.

Fig. 24 is a cross-sectional view of the gate line isolation trench with the sacrificial layer removed to form a gate gap in the stacked structure during the fabrication of the three-dimensional memory structure according to the present invention (corresponding to the cross-sectional X-Y line in fig. 2).

Fig. 25 is a cross-sectional view taken along line a-a in fig. 24 in the Y direction.

FIG. 26 is a cross-sectional view of a gate layer formed in the gate gap during the fabrication of the three-dimensional memory structure according to the present invention (corresponding to the cross-sectional view of FIG. 2).

Fig. 27 is a schematic cross-sectional view of an X-Y cross-section (corresponding to the X-Y cross-section in fig. 2) of the gate line isolation trench filled with the isolation trench filling layer in the preparation of the three-dimensional memory structure according to the present invention.

Fig. 28 is a cross-sectional view taken along line a-a in fig. 27 in the Y direction.

FIG. 29 is a cross-sectional view of a conductive material replacing the hole-filling sacrificial layer in the contact hole to form a connection stud in the fabrication of a three-dimensional memory structure according to the present invention (corresponding to the cross-sectional X-Y view in FIG. 2).

Fig. 30 is a cross-sectional view taken along line a-a in fig. 29 in the Y direction.

FIG. 31 is a cross-sectional view of a cross-section taken along line X-Y (corresponding to the cross-section taken along line X-Y in FIG. 2) illustrating the formation of plugs at the top of the connecting pillars and at the top of the vertical channel structure in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 32 is an enlarged view of a portion of the area indicated by the circle in fig. 31.

Fig. 33 is a cross-sectional view taken along line a-a in fig. 31 in the Y direction.

Fig. 34 is a schematic perspective view illustrating a stepped region having a step according to an embodiment of the present invention.

Drawings

10 semiconductor substrate

101 substrate body

102 doped well

103 silicon oxide layer

11 epitaxial sacrificial layer

12 stack structure

121 interlevel dielectric layer

122 sacrificial layer

13 first cap layer

14 vertical channel structure

141 high dielectric constant dielectric layer

142 functional sidewall layer

143 channel layer

144 plug oxide

15 step groove

16 side wall spacer

17 polysilicon transition layer

18 etch buffer layer

19 step coverage

20 contact hole

21 dummy channel hole

22 sidewall oxide layer

23 mask layer

24 pore-filling oxide layer

25 grid line isolation groove

26 side wall protective layer

261 nitrided layer

262 oxide layer

27 epitaxial gap

28 epitaxial layer

29 gate gap

30 gate stack structure

301 gate conductive part

31 isolation trench fill layer

32 connecting column

33 first plug

34 second plug

35 second cap layer

36 filling hole sacrificial layer

A-A y direction cross-section

Z1 first connection area

Z2 second attachment zone

Z3 third attachment zone

Z21 first step zone

Z22 second step partition

S101 to S110

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

The three-dimensional memory structure of the present invention is applicable to a variety of memory devices including, but not limited to, three-dimensional semiconductor memory devices such as 3D NAND. With the increasing integration degree of 3D NAND, the 3D NAND memory has been developed from 32 layers to 64 layers, and the number of layers is increased even higher, the depth of the contact hole to be etched is deeper and deeper, and the requirement for the etching process of the contact hole is more and more strict, and during the etching process of the contact hole, a gate layer breakdown (Punch) is easily caused, so that the contact hole penetrates through an interlayer dielectric layer between two gate layers.

Therefore, in order to solve the technical problems, namely, in the preparation process of the 3D NAND, gate layers are easy to break down when contact holes are etched, so that short circuit between different gate layers can be caused when connecting columns are formed in the contact holes, the invention provides a three-dimensional memory structure and a preparation method thereof. The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

Example one

FIG. 1 illustrates a flow chart for fabricating a three-dimensional memory structure according to an embodiment of the present invention. Referring to fig. 1, the method for fabricating the three-dimensional memory structure includes:

step S101, providing a semiconductor substrate;

step S102, sequentially forming an epitaxial sacrificial layer and a stacked structure on the semiconductor substrate, wherein the stacked structure comprises alternately stacked interlayer dielectric layers and sacrificial layers, the stacked structure comprises a core region and a step region which are sequentially arranged along a first direction, the step region comprises a first connecting region, a second connecting region and a third connecting region which are sequentially arranged along a second direction, and the second connecting region comprises a first step partition and a second step partition which are sequentially arranged along the second direction;

step S103, forming a step groove extending along the first direction in the second connection region of the step region, where the step groove includes a plurality of first steps and a plurality of second steps, the first steps are located in the first step partitions, the second steps are located in the second step partitions, and top surfaces of the first steps and the second steps of the same level respectively expose surfaces of the sacrificial layers located in different layers in a direction from the stacked structure to the semiconductor substrate;

step S104, forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step;

step S105, forming a contact hole in the step region where the etching buffer layer is formed, the contact hole exposing the etching buffer layer or penetrating the etching buffer layer, wherein the contact hole is respectively located in the first step partition and the second step partition of the second connection region of the step region;

step S106, filling a hole sacrificial layer in at least part of the contact holes, wherein at least one contact hole filled with the hole sacrificial layer exists in the first step partition and the second step partition;

step S107, forming a grid line isolation groove penetrating through the stacked structure in the stacked structure, wherein the epitaxial sacrificial layer is exposed out of the grid line isolation groove;

step S108, removing the sacrificial layer in the stacked structure based on the grid line isolation groove to form a grid gap, wherein the grid gap exposes partial end part of the etching buffer layer, and the sacrificial layer in the middle of the second connection region of the stepped region is reserved;

step S109, forming a gate conductive part in the gate gap, wherein the gate conductive part is connected with the etching buffer layer;

step S110, replacing the hole filling sacrificial layer in the contact hole with a conductive material to form a connection post.

Referring to fig. 2 and fig. 31-33, the three-dimensional memory structure prepared by the method for preparing a three-dimensional memory structure according to the embodiment, wherein fig. 2 shows a top view of the three-dimensional memory structure obtained by preparation, it should be noted that, in order to illustrate the detailed structure of the three-dimensional memory structure of the present invention, only part of the structural features of the three-dimensional memory structure is shown in fig. 2, and details of relevant parts are described below.

The method for fabricating the semiconductor structure of this embodiment will be described in detail with reference to the schematic interface diagrams corresponding to the steps. It should be noted that, in this embodiment, the following fig. 3 and other subsequent cross-sectional views along the X-Y section lines are cross-sectional views of the semiconductor structure formed after different process steps and cut at the same positions as the X-Y section lines in fig. 2; fig. 3 and other cross-sectional views taken along the X-Y line show cross-sectional views in both the X and Y directions, with the left side of the vertical dotted line in fig. 3 being a cross-sectional view taken along the X direction and belonging to the step region, and the right side of the vertical dotted line in fig. 3 being a cross-sectional view taken along the Y direction and belonging to the core region.

First, referring to fig. 3 and 4, step S101 is executed: a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes a substrate body 101, a doping well formed in the substrate body 101 by doping, and a silicon oxide layer 103 formed on the doping well as a protective layer. The substrate body 101 may be selected according to actual requirements of a device, the substrate body 101 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, the substrate body 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, Silicon carbide, and the like, and the semiconductor substrate 10 may also be a stacked structure 12, such as a Silicon/Germanium-Silicon stacked layer, and the like. In the present invention, the substrate body 101 may be, for example, a single crystal silicon substrate, the substrate body 101 may be doped P-type or N-type to form a P-well or an N-well, and further serve as a doped well, the silicon oxide layer 103 may be formed on the substrate body 101 with the doped well by a thermal oxidation or deposition process, and the silicon oxide layer 103 may prevent the doped well below the silicon oxide layer 103 from being damaged by etching when the polysilicon epitaxial sacrificial layer 11 formed above the silicon oxide layer 103 in the subsequent step S102 is removed.

Then, referring to fig. 3 and 4, step S102 is executed: sequentially forming an epitaxial sacrificial layer 11 and a stacked structure 12 on the semiconductor substrate 10, wherein the stacked structure 12 includes an interlayer dielectric layer 121 and a sacrificial layer 122 which are alternately stacked, the stacked structure 12 includes a Core region (Core) and a Step region (stable-Step, SS for short) which are sequentially arranged along a first direction (X direction), the Core region is used for storing data, the Step region is used for connecting with one end of a connection post 32 to be described later, and the other end of the connection post 32 is used for connecting with an interconnection structure; wherein the stepped region comprises a first attachment zone Z1, a second attachment zone Z2 and a third attachment zone Z3 arranged in succession along the second direction (Y-direction); further, the second connecting zone Z2 is divided into two step partitions disposed in sequence along the second direction by a sidewall spacer layer 16 to be described later and defined as a first step partition Z21 and a second step partition Z21, respectively, in the first step partition Z21 and the second step partition Z21 for forming a first step and a second step.

In the present embodiment, referring to fig. 3 and 4, the stacked structure 12 includes an interlevel dielectric layer 121 and a sacrificial layer 122 alternately stacked, and both the bottom layer and the top layer of the stacked structure 12 are the sacrificial layer 122. To say thatIt is clear that, in the present invention, the interlayer dielectric layer 121 and the sacrificial layer 122 have a higher etching selectivity ratio to ensure that the interlayer dielectric layer 121 is hardly removed when the sacrificial layer 122 is subsequently removed; specifically, the material of the sacrificial layer 122 may include, but is not limited to, silicon nitride (Si)₃N₄) The material of the interlayer dielectric layer 121 may include, but is not limited to, silicon oxide (SiO)₂)。

It should be noted that, in the present invention, the number of layers of the sacrificial layer 122 in the stacked structure 12 may include 32, 64, 96 or 128 layers, and the like, and specifically, the number of layers of the sacrificial layer 122 and the interlayer dielectric layer 121 in the stacked structure 12 may be set according to actual needs, which is not limited herein. The sacrificial Layer 122 and the interlayer dielectric Layer 121 may be formed using processes including, but not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process, such as a CVD process.

Referring to fig. 3 and 4, in step S102, a step of forming a vertical channel structure 14 in the core region of the stacked structure 12 is further included, where the vertical channel structure 14 includes a functional sidewall layer 142 and a channel layer 143 sequentially disposed from outside to inside in a radial direction. Specifically, a channel hole may be formed in the core region of the stacked structure 12, the channel hole sequentially penetrates through the stacked structure 12 and the sacrificial epitaxial layer 28 and then extends into the doped well of the semiconductor substrate 10, and then a blocking layer, a storage layer, a tunneling layer and the channel layer 143, the blocking layer, the storage layer and the tunneling layer are sequentially formed in the channel hole as the functional sidewall layer 142. As an example, the material of the blocking layer, the tunneling layer, and the memory layer comprise silicon oxide and silicon nitride, respectively, such that the functional sidewall has an ONO structure. In an alternative embodiment, before forming the functional sidewall layer 142 on the inner wall of the trench hole, a high-K dielectric layer (HK) is further formed on the inner wall of the trench hole, and the functional sidewall layer 142 is formed on the surface of the high-K dielectric layer, wherein the high-K dielectric layer may be made of alumina or the like. In an alternative embodiment, the vertical channel structure 14 further includes a plug oxide 144, and the plug oxide 144 is formed on the surface of the channel layer 143 and filled in the channel hole.

Referring to fig. 3 and 4, in step S102, after the vertical channel structure 14 is formed in the core region of the stacked structure 12, a step of forming a first capping layer 13 on the surface of the stacked structure 12 where the vertical channel structure 14 is formed is further included, where the material of the first capping layer 13 may be, for example, an oxide, such as silicon oxide, and for convenience of description, the first capping layer 13 and the interlayer dielectric layer 121 on the top of the stacked structure 12 may be described as a whole, that is, the top interlayer dielectric layer 121 of the stacked structure 12 includes the top interlayer dielectric layer 121 and the first capping layer 13 in fig. 3 and 4, and the surface of the stacked structure 12 is also the surface of the first capping layer 13.

It should be noted that, in the present embodiment, the vertical channel structure 14 is further formed in the core region of the stacked structure 12 before the step S103, but it is understood that, in other embodiments, the vertical channel structure 14 may also be formed in the core region of the stacked structure 12 after the step S103, that is, the vertical channel structure 14 may also be formed in the core region of the stacked structure 12 after the step groove 15 including a plurality of steps extending along the first direction is formed in the second connection region Z2 of the step region.

Referring to fig. 3 to 6, step S103 is performed to form a step groove 15 extending along the first direction in the second connection region Z2 of the step region, where the step groove 15 includes a plurality of first steps and a plurality of second steps, the first steps are located in the first step partition Z21, the second steps are located in the second step partition Z21, and top surfaces of the first steps and the second steps of the same level respectively expose surfaces of the sacrificial layers 122 located at different layers in a direction pointing to the semiconductor substrate 10 from the stacked structure 12. Note that, in step S103, no step is formed in the first connection region Z1 and the third connection region Z3 located on both sides of the second connection region Z2, and in subsequent step S109, the sacrificial layers 122 at the edge portions of the first connection region Z1, the third connection region Z3 and the second connection region Z2 are replaced with gate conductive portions 301, which are Wall (Wall) structures shown in fig. 34, and the Wall structures may be used for wiring, which will be described later.

Specifically, in step S103, first, for example, a plurality of first initial steps extending in a first direction and a plurality of second initial steps may be formed in the second connection region Z2 by performing a repeated etching-trimming process on the stacked structure 12 using a patterned mask (not shown), the first initial step is located at the first step zone Z21, the second initial step is located at the second step zone Z21, in a direction from the stacked structure 12 to the semiconductor substrate 10, top surfaces of the first initial step and the second initial step of the same level respectively expose end portions of the interlayer dielectric layer 121 located at different layers (see fig. 3 and 4), the patterned mask may include a photoresist or a carbon-based polymer material, and the patterned mask may be removed after the step is formed; then, an end portion of the interlayer dielectric layer 121 is exposed by top surfaces of the first preliminary step and the second preliminary step by etching to expose an end surface of the sacrificial layer 122 of the stack structure 12, thereby forming first steps at the first step partition Z21 and second steps at the second step partition Z21 (see fig. 5 and 6). In the present invention, each first step and each second step includes at least one level, each level being defined as a pair of stacked sacrificial layers 122 and interlayer dielectric layers 121; as an example, only the case where each first step and each second step contain one level is shown in fig. 3 and 4. As an example, fig. 3 only shows a case of including 5 first steps and 4 second steps, and it is understood that the number of the first steps and the number of the second steps can be adjusted as needed, which mainly depends on the number of the sacrificial layers 122 in the stacked structure 12 and the number of layers included in each first step.

Referring to fig. 7-12, step S104 is performed to form an etching buffer layer 18 on the surface of the sacrificial layer 122 exposed by the first step and the second step. Specifically, a polysilicon transition layer 17 may be formed first on the surface of the sacrificial layer 122 exposed by the top surfaces of the first step and the second step, respectively (corresponding to fig. 9 and 10); forming a metal layer on the surface of the polycrystalline silicon transition layer 17 by a deposition process; then annealing treatment is carried out to enable the metal layer and the polycrystalline silicon transition layer 17 to form a silicon metal alloy (M)_xSi_y) The silicon metal alloy serves as the etch buffer layer 18 (corresponding to fig. 11 and 12). As an example, the temperature of the annealing treatment is between 400 and 1100 ℃, and the time of the annealing treatment is between 1 and 20 min. As an example, the material of the metal layer M includes one or a combination of at least two of cobalt, nickel, and platinum. It should be noted that, in other embodiments, other suitable preparation processes may also be adopted to form a silicon metal alloy (M) on the surface of the sacrificial layer 122 exposed by the first step and the second step_xSi_y) As an etch buffer layer 18.

In an alternative embodiment of step S104, when the surface of the polysilicon transition layer 17 is formed with a metal layer through a deposition process, since the metal layer is also formed on the entire surface of the stacked structure 12, after the annealing process, a step of etching away the metal layer located in a region outside the polysilicon transition layer 17 is further required.

In an optional embodiment, step S104 may further include the step of forming a sidewall spacer 16 before the sidewalls of the step trench 15 (corresponding to fig. 7 and 8), and then forming the etching buffer layer 18 on the surface of the sacrificial layer 122 exposed by the top surfaces of the first step and the second step formed with the sidewall spacer 16; wherein the sidewall spacer 16 separates the first step partition Z21 from the second step partition Z21, and the sidewall spacer 16 is formed on the sidewall of each step (first step and second step) of the stepped trench 15, that is, the sidewall spacer 16 is formed on the common sidewall of the interlayer dielectric layer 121 and the sacrificial layer 122 exposed by the sidewall of each step. As an example, the material of the sidewall spacer 16 may be an oxide, such as silicon dioxide.

Note that, since, in step S104, when the etching buffer layer 18 is formed on the surfaces of the first step and the second step, it is not desirable that an etching buffer layer is formed on the surface of the doped well 102, so that when the bottom-most first step (for example, when the top surface of the first step of the same level is higher than the top surface of the second step by one level in the direction from the stacked structure 12 to the semiconductor substrate 10) is etched in step S103, the etching stops in the bottom-most interlayer dielectric layer 121 of the stacked structure 12, the sacrificial epitaxial layer 11 and the underlying semiconductor substrate 10 are not etched (corresponding to figure 9), but after the step of forming the etch buffer layer 18 at the surface of the sacrificial layer 122 exposed by the first step and the second step, the bottom-most first step is etched, stopping at the doped well 102 of the semiconductor substrate 10.

Referring to fig. 13 and 14, step S105 is performed to form a contact hole 20 in the step region where the etching buffer layer 18 is formed, wherein the contact hole 20 exposes the etching buffer layer 18 or penetrates through the etching buffer layer 18, and the contact hole 20 is respectively located in the first step partition Z21 and the second step partition Z21 of the second connection region Z2 of the step region. Specifically, the step capping layer 19, which may be, for example, silicon dioxide, may be first filled in the step groove 15 where the second connection region Z2 of the step region of the etching buffer layer 18 is formed; the step-shaped capping layer 19 is then etched down by a photolithography and etching process to form contact holes 20 in the step-shaped capping layer 19 in the step region, the contact holes 20 exposing the etch buffer layer 18 or penetrating the etch buffer layer 18. It should be noted that all or part of the contact hole 20 formed in the stepped region is used for subsequent filling with a conductive material to form the connection post 32, and the remaining contact hole 20 is used as the dummy contact hole 20 for subsequent forming of a dummy connection post by filling the hole-filling oxide layer 24.

In the step of forming the contact hole 20 in the step region where the etching buffer layer 18 is formed, a step of forming a doped well contact hole 20 in the step region is further included, and the doped well contact hole 20 exposes a doped well in the semiconductor substrate 10; the doped well contact hole 20 is used to form a doped well connection stud 32 in the doped well contact hole 20 at the same time as the step of replacing the hole-filling sacrificial layer 36 in the contact hole 20 with a conductive material to form a connection stud 32 (step S110).

It should be noted that, in fig. 13, from left to right, except for the first contact hole 20 (serving as the doped well contact hole 20) and the second contact hole 20 (formed on the surface of the sacrificial layer 122 at the bottommost portion of the stacked structure 12 exposed by the step), each of the other contact holes 20 penetrates through the etching buffer layer 18 and then etches at least two sacrificial layers 122 penetrating through the bottom portion and the interlayer dielectric layer 121 therebetween, which is to facilitate to describe that even if the contact hole 20 is over-etched during etching, a contact pillar subsequently formed in the contact hole 20 does not cause Word Line bridging (Word Line Bridge) of a different layer, and during an actual manufacturing process, the bottom portion of the contact hole 20 may also directly stop at the surface of the etching buffer layer 18.

Referring to fig. 13 and 14, in a preferred embodiment of step S105, the step cover layer 19 may be etched downward by photolithography and etching processes to simultaneously form a plurality of contact holes 20 and a plurality of dummy channel holes (for forming a dummy channel structure later, see the related part description below) in the step cover layer 19 of the step region, wherein the dummy channel holes sequentially penetrate through the stacked structure 12 and the epitaxial sacrificial layer 11 at the first connection region Z1 and/or the third connection region Z3, and the dummy channel holes are formed in the first connection region Z1 and the third connection region Z3 of the step region, that is, in the first connection region Z1 and/or the third connection region Z3. It should be noted that, in the existing manufacturing process, since each step has a different distance from the top of the stacked structure 12, that is, the etching distance is different, the contact hole 20 at each step needs to be etched in different etching processes, and the contact hole 20 and the dummy trench hole are also etched separately, but the etching buffer layer 18 is disposed on the step surface of the present invention, so that not only can the etching of all the contact holes 20 be completed in one etching process, but also the etching of the contact hole 20 and the dummy trench hole can be completed in the same etching step by using the same mask, the dummy trench hole and the contact hole 20 have the substantially same critical dimension CD, and the different depths are different, which not only simplifies the process steps, reduces the etching difficulty of the contact hole 20, and saves the cost. It will be appreciated that in some embodiments, the dummy channel holes and the contact holes 20 may also be formed by two separate etching processes.

Referring to fig. 15-20, step S106 is performed to fill a hole sacrificial layer 36 in at least a portion of the contact hole 20, and fill a hole oxide layer 24 in the dummy channel hole formed with the sidewall oxide layer 22 and the contact hole 20 not filled with the hole sacrificial layer 36, respectively serving as a dummy channel structure and a dummy connection pillar, which can serve as mechanical support members to prevent collapse of the memory device, wherein at least one contact hole 20 filled with the hole sacrificial layer 36 exists in the first step partition Z21 and the second step partition Z21. Specifically, step S106 includes: step S1061 of filling a hole sacrificial layer 36 in each of the contact holes 20 and the dummy trench holes (corresponding to fig. 16 and 17); step S1062, forming a patterned mask layer 23 on the surface of the stacked structure 12 formed in step S1061, where the openings in the patterned mask layer 23 expose the dummy channel holes and partially serve as dummy contact holes 20 (the number of the dummy contact holes 20 may also be zero, that is, the dummy contact holes 20 are not provided) (corresponding to fig. 18); step S1063, etching and removing the dummy channel holes and the filling sacrificial layers 36 filled in the dummy contact holes 20 based on the patterned mask to reopen the dummy channel holes and the dummy contact holes 20 (corresponding to fig. 19), and then not removing the filling sacrificial layers 36 in the contact holes 20 for forming the connection studs 32; step S1064 is to fill a hole oxide layer 24 in the dummy channel hole re-opened by an etching process (such as dry etching or wet etching) and the dummy contact hole 20 not filled with the hole filling sacrificial layer 36, wherein the hole oxide layer 24 is formed in the dummy channel hole, the dummy contact hole 20 and the top surface of the stacked structure 12 (corresponding to fig. 20). As an example, the material of the hole-filling sacrificial layer 36 may be polysilicon, and the hole-filling oxide layer 24 may be silicon oxide. By way of example, referring to fig. 19, in the second direction, each step is provided with 6 contact holes 20 (of course, other suitable numbers are possible, but must be larger than 2), wherein, from left to right, the 1 st, 2 nd, 5 th, 6 th contact holes 20 are used as the dummy contact holes 20, and the contact holes 20 of the 3 rd and 4 th contact holes 20 are used as the contact holes 20 for forming the connection post 32, that is, at least one contact hole 20 for forming the connection post 32 exists on the first step and the second step, the contact hole 20 for forming the connection post 32 is arranged in the middle of the second region, the gate line gap formed by subsequently removing the sacrificial layer 122 of the stacked structure 12 based on the gate line isolation groove 25 can be prevented from contacting the contact hole 20 for forming the connection post 32, that is, the connection post 32 formed subsequently can be prevented from contacting the gate conductive portion 301 of the gate layer formed in the gate line gap.

It should be noted that, when the material of the hole filling sacrificial layer 36 is polysilicon, since the material of the epitaxial sacrificial layer 11 and the doped well is also polysilicon, before the hole filling sacrificial layer 36 is filled in each of the contact holes 20 and each of the dummy trench holes, a sidewall oxide layer 22 (such as silicon oxide) is formed on the sidewall surface of the epitaxial sacrificial layer 11 exposed by the dummy trench hole and the sidewall surface of the semiconductor substrate 10 by a thermal oxidation process, so as to avoid etching the epitaxial sacrificial layer 11 and the doped well in the process of reopening the dummy trench hole and the dummy contact hole 20 by an etching process in step S1064.

Referring to fig. 21, step S107 is performed to form a gate line isolation trench 25 extending along a first direction in the stacked structure 12 and penetrating through the stacked structure 12, wherein the epitaxial sacrificial layer 11 is exposed from the gate line isolation trench 25. Specifically, for example, photolithography and dry etching processes may be used to form the gate line isolation groove 25 penetrating through the stacked structure 12 in the thickness direction in the stacked structure 12, the gate line isolation groove 25 exposes the epitaxial sacrificial layer 11, the step region is interposed between two adjacent gate line isolation grooves 25, and the first connection region Z1 and the third connection region Z3 of the step region are adjacent to the gate line isolation groove 25 on the sides which are not connected to the second connection region Z2, respectively. It should be noted that, a plurality of gate line isolation trenches 25 with smaller intervals may be further included between two adjacent gate line isolation trenches 25 in the core region, so as to clean the sacrificial layer 122 in the core region of the stacked structure 12.

Referring to fig. 22-25, in step S108, the sacrificial layer 122 in the stacked structure 12 is removed based on the gate line isolation trench 25 to form a gate gap 29, a portion of the end portion of the etch buffer layer 18 is exposed by the gate gap 29, so that the gate conductive portion 301 filled in the gate gap 29 is ensured to contact the etch buffer layer 18, and the sacrificial layer 122 in the middle of the second connection region Z2 in the step region is remained, which ensures that the connection stud 32 is wrapped by the remaining sacrificial layer 122 (serving as a gate insulating portion of the gate layer) and does not contact the gate conductive portion 301 of the gate layer even when the connection stud 32 formed subsequently penetrates through the etch buffer layer 18 and enters the gate layer. Specifically, for example, an etching process (e.g., wet etching) may be used to remove the core region in the stacked structure 12, the sacrificial layer 122 of the first connection region Z1, the third connection region Z3 and the edge region of the second connection region Z2 near the first connection region Z1 and the second connection region Z2 is removed, and the sacrificial layer 122 in the middle region of the second connection region Z2 is remained as a gate insulating portion of the gate layer, so that after the gate conductive portion 301 of the gate layer is formed in the gate gap 29 (see step S109, and fig. 2, 21-30), the gate conductive portion 301 is connected to the etching buffer layer 18 at the edge regions on both sides of the second direction (Y direction) of the second connection region Z2, so that the connection pillar 32 in the contact hole 20 can be electrically connected to the gate layer through the etching buffer layer 18, in other words, the connection stud 32 can lead out the gate conductive portion of the corresponding layer in the wall structure (i.e., the first connection region Z1 or/and the second connection region Z2) in fig. 34 by etching the buffer layer 18. It should be noted that the edge regions of the gate conductive parts 301 on both sides of the first direction (X direction) of the second connection region Z2 may or may not be connected to the etching buffer layer 18, where fig. 2 shows the case of disconnection, and fig. 26 shows that, except that the edge regions of the etching buffer layer 18 on the topmost step on both sides of the first direction of the second connection region Z2 are connected to the gate conductive parts 301 of the topmost gate layer (at this time, it is necessary to ensure that the projection of the contact hole 20 for forming the connection post 32 on the topmost step on the gate layer is located in the gate insulating part), the etching buffer layers 18 on other steps are not connected to the gate conductive parts 301 of the corresponding gate layer on both sides of the first direction of the second connection region Z2. In an optional embodiment of the present invention, the step of removing the sacrificial layer 122 in the stacked structure 12 based on the gate line isolation groove 25 to form the gate gap 29 further includes the steps of removing the epitaxial sacrificial layer 11 based on the gate line isolation groove 25 to form an epitaxial gap 27, and forming an epitaxial layer 28 in the epitaxial gap 27 by an epitaxial process SEG (corresponding to fig. 22-24). The steps of removing the epitaxial sacrificial layer 11 based on the gate line isolation trench 25 to form an epitaxial gap 27, and forming an epitaxial layer 28 in the epitaxial gap 27 further include: forming a sidewall protection layer 26 (corresponding to fig. 22) on the inner wall of the gate line isolation trench 25 and the hole-filling oxide layer 24 on the surface of the stacked structure 12, and etching to remove the sidewall protection layer 26 at the bottom of the gate line isolation trench 25, so as to form a sidewall protection layer 26 on the sidewall of the gate line isolation trench 25; the epitaxial sacrificial layer 11, the functional sidewall layer 142 of the vertical channel structure 14 surrounded by the epitaxial sacrificial layer 11, and the silicon oxide layer 103 between the epitaxial sacrificial layer 11 and the doped well are removed based on the gate line isolation trench 25 formed with the sidewall protection layer 26 to form the epitaxial gap 27 (corresponding to fig. 23). Illustratively, the sidewall protection layer 26 includes a nitride-oxide-nitride sidewall protection layer 26, and the nitride layer 261 (e.g., silicon nitride) -oxide layer 262 (e.g., silicon oxide) -nitride layer 261 is used to form the sidewall protection layer 26 to match the functional sidewall layer 142(ONO layer) for removing the sidewall of the vertical channel structure 14.

Referring to fig. 26, step S109 is executed to form a gate conductive portion 301 in the gate gap 29, wherein the gate conductive portion 301 is connected to the etching buffer layer 18, the gate conductive portion 301 and the remaining sacrificial layer 122 (gate insulating portion) in the same layer are used together as a gate layer, and the gate layer and the interlayer dielectric layer 121 form a gate stack structure 30. As an example, the material of the gate conductive portion 301 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material.

In the present invention, after the step of forming the gate layer in the gate gap 29, a step of filling an isolation trench filling layer 31 in the gate line isolation trench 25 is further included (corresponding to fig. 27 and 28), where the isolation trench filling layer 31 penetrates through the gate stack structure 30, and a bottom of the isolation trench filling layer 31 is in contact with the epitaxial layer 28. As an example, the material of the isolation trench filling layer 31 includes silicon nitride or silicon oxide.

Referring to fig. 27-30, step S110 is performed to replace the filling sacrificial layer 36 in the contact hole 20 with a conductive material to form a connection stud 32, wherein a projection of the connection stud 32 on the gate layer is located inside the gate insulating portion of the gate layer, so that even if the contact hole 20 is over-etched (Punch), the connection stud 32 does not contact the gate conductive portion 301 of the gate layer, thereby avoiding word line bridging of different layers, and the connection stud 32 is used to lead out the gate layer with a corresponding step. Specifically, the step S110 includes a step S1101 of filling an isolation trench filling layer 31 in the gate line isolation trench 25 (corresponding to fig. 27 and 28); step S1102, removing the hole-filling oxide layer 24 on the surface of the stacked structure 12 by using a chemical mechanical polishing CMP process to expose the contact hole 20 filled with the hole-filling sacrificial layer 36; step S1103; etching to remove the hole-filling oxide layer 24 in the contact hole 20 to reopen the contact hole 20; a step S1104; filling the re-opened contact hole 20 and the surface of the stacked structure 12 with a conductive material, and removing the conductive material on the surface of the stacked structure 12 by chemical mechanical polishing CMP, thereby forming a connection post 32 in the re-opened contact hole 20. As an example, the material of the isolation trench filling layer 31 includes silicon nitride or silicon oxide. By way of example, the material of the connection stud 32 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material.

In step S110, a doped well connection stud 32 is also formed in the doped well contact hole 20 in the step of replacing the hole-filling sacrificial layer 36 in the contact hole 20 with a conductive material to form a connection stud 32.

Referring to fig. 31-33, in an alternative embodiment, the step of replacing the hole-filling sacrificial layer 36 in the contact hole 20 with a conductive material to form the connection post 32 further includes forming a second cap layer 35 on the surface of the gate stack structure 30, forming an opening in the second cap layer 35 by using a photolithography process to expose the connection post 32 and the vertical channel structure 14, filling the opening with a conductive material to form a first plug 33 and a second plug 34 in the opening at the top of the connection post 32 and the opening at the top of the vertical channel structure 14, respectively, wherein the first plug 33 is connected to the top of the connection post 32, and the second plug 34 is connected to the channel layer 143 of the vertical channel structure 14. As an example, the material of the first plug 33 and the second plug 34 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material.

Referring to fig. 34, fig. 34 shows only the first step sub-section Z21 and the second step sub-section Z21, the wall structure, and the gate line isolation trench 25 of the step region of the three-dimensional memory structure of the present invention; the wall structure, that is, the first connection region Z1 and the second connection region Z2, is led by introducing the wall structure, specifically, the conductive portion of the gate electrode layer of the corresponding layer in the wall structure is led out by the etching buffer layer 18 and the connection post 32 formed on each step in the step region, and the specific leading-out manner is described in the above step S108, which is not described herein again.

FIG. 2 shows that, as shown in FIG. 2, the method for fabricating the three-dimensional memory structure of the present embodiment is adapted to Word Line Center Driver SS (Word Line Driver SS), that is, the step region is located between two adjacent core regions; it will be appreciated that in some embodiments, it may also be suitable for wordline end drives, i.e., the step region is located on one side or on opposite sides of the core region.

Example two

Referring to fig. 2 and fig. 31-33, the present invention further provides a three-dimensional memory structure fabricated by the fabrication method of the first embodiment, wherein the three-dimensional memory structure at least comprises a semiconductor substrate 10, an epitaxial layer 28, a gate stack structure 30, a plurality of steps (a plurality of first steps and a plurality of second steps), an etching buffer layer 18, and a plurality of connection pillars 32 (CT in fig. 2). The three-dimensional memory structure of the embodiment can reduce the process difficulty of etching the contact hole 20 in the step region, eliminate Word Line bridging (Word Line Bridge) of different layers caused by Punch (Punch) in the etching process of the contact hole 20, and improve the performance of the three-dimensional memory.

Referring to fig. 2 and fig. 31-33, in the present embodiment, the semiconductor substrate 10 includes a substrate body 101, and a doped well is formed in the substrate body 101 through a doping process. The substrate body 101 may be selected according to actual requirements of a device, the substrate body 101 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, the substrate body 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, Silicon carbide, and the like, and the semiconductor substrate 10 may also be a stacked structure 12, such as a Silicon/Germanium-Silicon stacked layer, and the like. In the present invention, the substrate body 101 may be, for example, a single crystal silicon substrate, and the substrate body 101 may be doped P-type or N-type to form a P-well or an N-well, which is further used as a doped well.

Referring to fig. 31-33, in the present embodiment, the epitaxial layer 28 is formed on the semiconductor substrate 10 by an epitaxial process SEG, and the material of the epitaxial layer 28 may be, for example, doped polysilicon, for connecting the channel layer 143 of the vertical channel structure 14 with a doped well of the semiconductor substrate 10.

Referring to fig. 2 and fig. 31 to 33, in the present embodiment, the gate stack structure 30 is formed on the epitaxial layer 28, the gate stack structure 30 includes an interlayer dielectric layer 121 and a gate layer which are stacked alternately, the gate stack structure 30 includes a core region and a step region which are sequentially arranged along a first direction, the step region includes a first connection region Z1, a second connection region Z2 and a third connection region Z3 which are sequentially arranged along a second direction, the second connection region Z2 is divided into a first step partition Z21 and a second step partition Z21 which are sequentially arranged along the second direction by a sidewall spacer 16 located in a middle portion of the second connection region Z2, and each gate layer includes a gate insulating portion located in the middle portion of the second connection region Z2 and a gate conductive portion 301 which partially surrounds the gate insulating portion. As an example, the material of the gate conductive portion 301 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material. As an example, the material of the gate insulating portion may include silicon nitride, for example. In this embodiment, the first direction is an X direction, the first direction is parallel to the semiconductor substrate 10, the second direction is a Y direction, the second direction is parallel to the semiconductor substrate 10, and the first direction and the second direction form an included angle, such as 90 °. It should be noted that, in this embodiment, the number of the gate layer in the gate stack structure 30 may include 32, 64, 96 or 128 layers, and the like, and specifically, the number of the gate layer and the interlayer dielectric layer 121 in the stacked structure 12 may be set according to actual needs, which is not limited herein. The gate Layer and the interlayer dielectric Layer 121 may be formed by a process including, but not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process, such as a CVD process. In this embodiment, the first connection region Z1 and the third connection region Z3 on both sides of the second connection region Z2 of the gate stack structure 30 are not stepped, and are connected by a Wall structure as a Wall (Wall) structure. It should be noted that the forming process and the structural features of the gate stack structure 30 are described in detail in the first embodiment, and are not described herein again.

Referring to fig. 31 to 33, in the present embodiment, a first cap layer 13 is further formed on the gate stack structure 30, a material of the first cap layer 13 may be, for example, an oxide, such as silicon oxide, for convenience of description, the first cap layer 13 and the interlayer dielectric layer 121 on the top of the gate stack structure 30 may be described as a whole, that is, the top interlayer dielectric layer 121 of the gate stack structure 30 mentioned later includes the top interlayer dielectric layer 121 and the first cap layer 13 in fig. 31 and 33, and a surface of the stack structure 12 is also the surface of the first cap layer 13.

Referring to fig. 2 and fig. 31-33, in the present embodiment, the first steps are located in the first step sub-area Z21, and the second steps are located in the second step sub-area Z21, that is, the cross section of the second area Z2 along the Y direction includes two steps, i.e., a first step and a second step, which are separated by the sidewall spacer 16 (see fig. 2 and fig. 33). In the present embodiment, in a direction from the gate stack structure 30 toward the semiconductor substrate 10, top surfaces of the first step and the second step of the same level respectively expose surfaces of the gate insulating portion and a portion of the gate conductive portion 301 of the gate layer at different levels. As an example, each of the steps includes at least one level, each level being defined as a pair of stacked gate layers and interlayer dielectric layers 121; as an example, only a case where each step contains one hierarchy is shown in fig. 31 and 33. It should be noted that the forming process and the structural features of the step are described in detail in the first embodiment, and are not described herein again.

Referring to fig. 2 and fig. 31 to 33, the etching buffer layer 18 is disposed on the surface of the gate insulating portion of the gate layer exposed by the top surfaces of the first step and the second step and on the surface of a portion of the gate conductive portion 301, respectively. As an example, the etch buffer layer 18 includes a silicon metal alloy (M)_xSi_y). As an example, the material of the metal layer M includes one or a combination of at least two of cobalt, nickel, and platinum. In addition, the step is formedThe process and the structural features are described in detail in the first embodiment, and are not described herein again.

Referring to fig. 2 and fig. 31-33, in the present embodiment, a plurality of connection pillars 32 are formed on the etching buffer layer 18, one end of each connection pillar 32 close to the semiconductor substrate 10 is in contact with the etching buffer layer 18 or penetrates through the etching buffer layer 18, a projection of each connection pillar 32 on the gate layer is located in the gate insulating portion of the gate layer, at least one connection pillar 32 exists in the first step partition Z21 and the second step partition Z21, and the connection pillar 32 is connected to the etching buffer layer 18 on the top surface of the corresponding step, so as to lead out the corresponding gate layer. By way of example, the material of the connection stud 32 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material. It should be noted that the forming process and the structural features of the connecting stud 32 are described in detail in the first embodiment, and are not described herein again.

Referring to fig. 31-33, in an alternative embodiment, the three-dimensional memory structure further includes a doped well connection stud 32 (the leftmost connection stud 32 in fig. 31), the doped well connection stud 32 is located in the second connection region Z2, and the doped well connection stud 32 is connected to a doped well in the semiconductor substrate 10.

Referring to fig. 2 and fig. 31-33, in an alternative embodiment, the three-dimensional memory structure further includes a plurality of dummy channel structures (DCHs in fig. 2) and a plurality of dummy connection pillars (DCTs in fig. 2, the number of which may also be zero), and the dummy channel structures and the dummy connection pillars can be used as mechanical support members to prevent collapse of the memory device; the dummy channel structure sequentially penetrates through the gate stack structure 30 and the epitaxial layer 28 at the first connection region Z1 and/or the third connection region Z3; the dummy connection post is formed on the etching buffer layer 18, and one end of the dummy connection post close to the semiconductor substrate 10 is in contact with the etching buffer layer 18 or penetrates through the etching buffer layer 18. As an example, referring to fig. 33, along the second direction, 1 connecting stud 32 (although other suitable numbers are also possible, but must be greater than or equal to 1) and 2 dummy connecting studs are respectively disposed on the first step/the second step, wherein, from left to right, the 1 st, 2 nd, 5 th, and 6 th dummy connecting studs are dummy connecting studs, and the 3 rd and 4 th dummy connecting studs, that is, at least one contact hole 20 for forming the connecting stud 32, exist on the first step and the second step. By way of example, the dummy channel structures and dummy connection studs, and connection studs 32, have substantially the same critical dimension CD, except that they differ in depth. It should be noted that the forming process and the structural features of the dummy channel structure and the dummy connection pillar are described in detail in the first embodiment, and are not repeated herein.

Referring to fig. 2 and fig. 31 to 33, in the present embodiment, a vertical channel structure 14 (CH in fig. 2) is disposed in the core region, the vertical channel structure 14 sequentially penetrates through the gate stack structure 30 and the epitaxial layer 28, and the vertical channel structure includes a functional sidewall layer 142 and a channel layer 143 that are sequentially disposed from outside to inside in a radial direction. The functional sidewall layer 142 includes a blocking layer, a storage layer, and a tunneling layer sequentially disposed along a radial direction from outside to inside. As an example, the material of the blocking layer, the tunneling layer, and the memory layer comprise silicon oxide and silicon nitride, respectively, such that the functional sidewall has an ONO structure. In an alternative embodiment, the vertical channel structure 14 further includes a high-K dielectric layer (high-K dielectric layer, HK) surrounding the functional sidewall layer 142, and the material of the high-K dielectric layer may be alumina or the like. In an alternative embodiment, the vertical channel structure 14 further includes a plug oxide 144, and the plug oxide 144 is formed on the surface of the channel layer 143 and filled in the channel hole.

Referring to fig. 31-33, in an alternative embodiment, the three-dimensional memory structure further includes a sidewall oxide layer 22, the dummy channel structure sequentially penetrates through the gate stack structure 30 and the epitaxial layer 28 and extends into the semiconductor substrate 10, and the sidewall oxide layer 22 is located between a sidewall of the dummy channel structure and the semiconductor substrate 10.

Referring to fig. 31-33, in an alternative embodiment, the three-dimensional memory structure includes a sidewall spacer 16 formed on the sidewall of the first step in the first step partition Z21 and the sidewall of the second step in the second step partition Z21. Specifically, the sidewall spacers 16 are formed on the sidewalls of each first step and each second step of the stepped trench 15, that is, the sidewall spacers 16 are formed on the common sidewalls of the interlayer dielectric layer 121 and the sacrificial layer 122 exposed by the sidewalls of each step, and the sidewall spacers 16 separate the first step partition Z21 from the second step partition Z21. As an example, the material of the sidewall spacer 16 may be an oxide, such as silicon dioxide.

Referring to fig. 2 and fig. 31-33, in an alternative embodiment, the three-dimensional memory structure further includes an isolation trench filling layer 31, the isolation trench filling layer 31 (which is formed in the gate line isolation trench GLS) penetrates through the gate stack structure 30, and the bottom of the isolation trench filling layer 31 contacts the epitaxial layer 28. As an example, the material of the isolation trench filling layer 31 includes silicon nitride or silicon oxide.

Referring to fig. 31-33, in an alternative embodiment, the three-dimensional memory structure further includes a second cap layer 35, and a first plug 33 and a second plug 34; the second cap layer 35 covers the surface of the first cap layer 13 above the gate stack structure 30 and the surface of the stepped cap layer 19 in the stepped region of the gate stack structure 30, the first plug 33 is formed at the top of the connection post 32, and the first plug 33 is connected to the connection post 32 after penetrating through the second cap layer 35; the second plug 34 is formed on the top of the vertical channel structure 14, and the second plug 34 sequentially penetrates through the second cap layer 35 and the first cap layer 13 and then is connected to the channel layer 143 of the vertical channel structure 14. As an example, the material of the first plug 33 and the second plug 34 may be, for example, a titanium nitride and tungsten composite layer, or other suitable conductive material.

In summary, in the process of fabricating the three-dimensional memory structure of the present invention, the step region is divided into the first connection region Z1, the second connection region Z2 and the third connection region Z3 along the second direction, the second connection region Z2 is divided into two step partitions along the second direction, the etching buffer layer 18 of silicon metal alloy (MxSiy) is formed on the surface of the sacrificial layer 122 of the stacked structure 12 exposed by the top surfaces of the steps of the two step partitions, the contact hole 20 is formed in the step region where the etching buffer layer 18 is formed, and when the sacrificial layer 122 of the stacked structure 12 is replaced with the gate conductive material, the sacrificial layer 122 located in the middle of the second connection region Z2 is remained, and the gate conductive material is ensured to be electrically connected to the etching buffer layer 18 at the edge of the second connection region Z2, so that the connection post 32 in the contact hole 20 can be electrically connected to the gate layer by the etching buffer layer 18, even if the situation of perforation (Punch) occurs in the etching process of the contact hole 20, the connecting column 32 formed in the contact hole 20 cannot cause the phenomenon of Word Line bridging (Word Line Bridge) of different layers, so the invention can reduce the process difficulty of the etching of the contact hole 20 in the stepped region, eliminate the Word Line bridging (Word Line Bridge) of different layers caused by the perforation (Punch) occurring in the etching process of the contact hole 20 and improve the performance of the three-dimensional memory device;

in the three-dimensional memory structure and the preparation method thereof, the etching buffer layer 18 is arranged, so that the etching of the contact hole 20 and the pseudo channel hole can be completed by adopting the same mask and in the same etching step, thereby simplifying the process steps, reducing the etching difficulty of the contact hole 20 and saving the cost.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for preparing a three-dimensional memory structure is characterized by comprising the following steps:

providing a semiconductor substrate;

forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step, wherein the etching buffer layer is made of a conductive material;

2. The method for fabricating a three-dimensional memory structure according to claim 1, wherein a vertical channel structure is formed in the core region, and the vertical channel structure comprises a functional sidewall layer and a channel layer sequentially arranged from outside to inside along a radial direction; the step of removing the sacrificial layer in the stacked structure based on the gate line isolation groove to form a gate gap further comprises a step of removing the epitaxial sacrificial layer based on the gate line isolation groove to form an epitaxial gap and forming an epitaxial layer in the epitaxial gap.

3. The method for fabricating a three-dimensional memory structure according to claim 2, wherein the step of removing the epitaxial sacrificial layer based on the gate line isolation trench to form an epitaxial gap and forming an epitaxial layer in the epitaxial gap comprises:

4. The method of claim 3, wherein the step of forming a sidewall protection layer on the sidewall of the gate line isolation trench comprises sequentially forming a sidewall protection layer comprising a nitride layer, an oxide layer and a nitride layer on the sidewall of the gate line isolation trench.

5. The method of claim 1, wherein the step of forming a contact hole in the step region where the etching buffer layer is formed comprises:

6. The method as claimed in claim 5, wherein the step of filling the hole sacrificial layer in at least a portion of the contact hole comprises:

7. The method of claim 1, wherein the step of forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step comprises,

forming a side wall spacing layer on the side wall of the stepped groove;

and forming the etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step on which the side wall spacer is formed.

8. The method of claim 7, wherein the material of the sidewall spacer comprises silicon oxide.

9. The method of claim 1, further comprising a step of filling an isolation trench filling layer in the gate line isolation trench after the step of forming the gate layer in the gate gap.

10. The method of claim 9, wherein the isolation trench filling layer comprises silicon nitride or silicon oxide.

11. The method as claimed in claim 1, wherein the step of replacing the hole-filling sacrificial layer in the contact hole with a conductive material to form a connection stud further comprises a step of forming a first plug on top of the connection stud.

12. The method of claim 1, wherein the core region has a vertical channel structure formed therein, and the step of replacing the hole-filling sacrificial layer in the contact hole with a conductive material to form a connection stud further comprises a step of forming a second plug on top of the vertical channel structure.

13. The method of claim 1, wherein the material of the gate conductive portion comprises a titanium nitride and tungsten composite layer.

14. The method of claim 1, wherein the material of the connection stud comprises a composite layer of titanium nitride and tungsten.

15. The method of claim 1, further comprising a step of forming a doped well contact hole in the step region, wherein the step of forming a contact hole in the step region with the etching buffer layer, wherein the doped well contact hole exposes a doped well in the semiconductor substrate;

16. The method of fabricating a three-dimensional memory structure according to any one of claims 1 to 15, wherein the step of forming an etching buffer layer on the surface of the sacrificial layer exposed by the top surfaces of the first step and the second step comprises:

17. The method according to claim 16, wherein the forming a metal layer on the surface of the polysilicon layer, the metal layer and the polysilicon layer forming a silicon metal alloy, and the step of using the silicon metal alloy as the etching buffer layer comprises:

forming a metal layer on the surface of the polycrystalline silicon layer;

18. The method as claimed in claim 17, wherein the annealing temperature is between 400-1100 ℃ and the annealing time is between 1-20 min.

19. The method of claim 16, wherein the metal layer comprises one or a combination of at least two of cobalt, nickel, and platinum.

20. A three-dimensional memory structure, the three-dimensional memory structure comprising:

a semiconductor substrate;

the etching buffer layer is formed on the surface of the gate insulating part of the gate layer and the surface of part of the gate conducting part, which are exposed by the top surfaces of the first step and the second step, and is made of a conducting material;

21. The three-dimensional memory structure of claim 20, wherein a vertical channel structure is disposed in the core region, the vertical channel structure extending through the gate stack structure, the vertical channel structure comprising a functional sidewall layer and a channel layer disposed sequentially from outside to inside in a radial direction.

22. The three-dimensional memory structure of claim 21, wherein the vertical channel structure further comprises a high-k dielectric layer surrounding the functional sidewall layer.

23. The three-dimensional memory structure of claim 20, further comprising a plurality of dummy channel structures and a plurality of dummy connection pillars; the dummy channel structure penetrates through the gate stack structure at the first connection region and/or the third connection region; the pseudo connecting column is formed on the etching buffer layer, and one end of the pseudo connecting column close to the semiconductor substrate is in contact with the etching buffer layer or penetrates through the etching buffer layer.

24. The three-dimensional memory structure of claim 23, further comprising a sidewall oxide layer, wherein the dummy channel structure extends through the gate stack structure and into the semiconductor substrate, and wherein the sidewall oxide layer is between a sidewall of the dummy channel structure and the semiconductor substrate.

25. The three-dimensional memory structure of claim 20, wherein the three-dimensional memory structure comprises a sidewall spacer formed on a sidewall of the first step in the first step partition and a sidewall of the second step in the second step partition.

26. The three-dimensional memory structure of claim 20, further comprising an epitaxial layer disposed between the semiconductor substrate and the gate stack structure.

27. The three-dimensional memory structure of claim 26, further comprising an isolation trench fill layer, wherein the isolation trench fill layer extends through the gate stack structure and a bottom of the isolation trench fill layer is in contact with the epitaxial layer.

28. The three-dimensional memory structure of claim 27, wherein the material of the isolation trench fill layer comprises silicon nitride or silicon oxide.

29. The three-dimensional memory structure of claim 20, further comprising a number of first plugs formed on top of the connection pillars.

30. The three-dimensional memory structure of claim 21, further comprising a number of second plugs formed on top of the vertical channel structures.

31. The three-dimensional memory structure of claim 20, wherein the material of the gate conductive portion of the gate layer comprises a titanium nitride and tungsten composite layer.

32. The three-dimensional memory structure of claim 20, wherein the material of the connection stud comprises a titanium nitride and tungsten composite layer.

33. The three-dimensional memory structure of claim 20, further comprising a doped well connection stud located in the second connection region and connected with a doped well in the semiconductor substrate.

34. The three-dimensional memory structure of claim 20, wherein the first direction is perpendicular to the second direction.

35. The three-dimensional memory structure of any of claims 20-34, wherein the etch buffer layer comprises a silicon metal alloy.