CN111757038B - Pixel data processing method and integrated chip - Google Patents
Pixel data processing method and integrated chip Download PDFInfo
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- CN111757038B CN111757038B CN202010647208.8A CN202010647208A CN111757038B CN 111757038 B CN111757038 B CN 111757038B CN 202010647208 A CN202010647208 A CN 202010647208A CN 111757038 B CN111757038 B CN 111757038B
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Abstract
The invention discloses a pixel data processing method and an integrated chip. The method comprises the following steps: if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency; determining a pixel format according to the actual parallel processing pixel number; and converting the number of pixels input by each clock of the pixel data into the pixel format. The technical scheme converts the pixel number input by each clock into a format which can meet the determined pixel number of actual parallel processing so as to reduce the working frequency of processing the pixel data and improve the working stability of the integrated chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of data communication, in particular to a pixel data processing method and an integrated chip.
Background
Video image processing systems are increasingly used in a wide variety of fields, such as device inspection/detection, security monitoring, industrial vision, and artificial intelligence. With the increasing of the resolution of the video image processing system, the number of channels (Lane) used on the terminal device for video display increases, and the Link Rate (LR) also increases, which makes higher and higher requirements on the stability, coordination, and the like of the hardware platform of the video image processing system.
Under the scenario of a large increase in data processing capacity, the capability of an integrated chip to process Pixel data in parallel is limited, and the increase of the bit number (BPP), the Frame Rate (FR), and the like of each Pixel can cause a large increase in the Pixel data to be processed, which is sent into an Intellectual Property (IP) core of the integrated chip, so that the operating frequency of the integrated chip is too high, the data processing performance is reduced, and the stability of the operation of the integrated chip is affected.
Disclosure of Invention
The invention provides a pixel data processing method and an integrated chip, which are used for reducing the working frequency of pixel data processing and improving the working stability of the integrated chip.
In a first aspect, an embodiment of the present invention provides a pixel data processing method, applied to an integrated chip of a video image processing system, including:
if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency;
determining a pixel format according to the actual parallel processing pixel number;
converting the number of Pixels Per Clock (PPC) of the pixel data into the pixel format.
Further, the method also comprises the following steps:
and adjusting the actual use size of the internal storage space according to the pixel number input by each clock and the actual parallel processing pixel number, and caching the pixel data into the internal storage space.
Further, the determining the number of pixels actually processed in parallel includes:
and calculating the number of actually parallel processed pixels according to the frame rate, the number of bits of each pixel and the mapping relation between the number of actually parallel processed pixels and the working frequency, so that the working frequency corresponding to the number of actually parallel processed pixels is lower than the current working frequency.
Further, the method also comprises the following steps:
if the working frequency corresponding to the actual parallel processing pixel number still exceeds the effective working frequency range, the working frequency corresponding to the actual parallel processing pixel number is made to belong to the effective working frequency range by at least one of the following modes:
adjusting the frame rate;
adjusting the frame rate adjustment step length;
and adjusting the number of bits of each pixel.
Further, the adjusting the frame rate includes:
and starting from the upper limit of the frame rate which can be supported by the panel, adjusting the frame rate in a descending manner according to the step length of the frame rate adjustment.
Further, the method also comprises the following steps: and improving the total pixel number of the panel display by at least one of the following modes:
adjusting the number of bits of each pixel;
adjusting the frame rate adjustment step length;
adjusting the frame rate;
adjusting the pixel number of actual parallel processing;
the actual size of the internal storage space is adjusted.
Further, the adjusting the frame rate includes:
and starting from the lower limit of the frame rate which can be supported by the panel, adjusting the frame rate in an incremental mode according to the step length of the frame rate adjustment.
In a second aspect, an embodiment of the present invention provides an integrated chip, including: a processor and a memory;
the memory is used for caching pixel data;
the processor is provided with:
the parallel data control module is used for determining the actual parallel processing pixel number if the current working frequency of the pixel data to be processed exceeds the effective working frequency range, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency;
the data conversion module is used for determining a pixel format according to the actual parallel processing pixel number;
and the input data control module converts the pixel number input by each clock of the pixel data into the pixel format.
Further, the method comprises the following steps:
and the memory state control module is used for adjusting the actual use size of the internal storage space of the memory according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching the pixel data into the internal storage space of the memory.
Further, the memory includes at least one of: a First-in First-out (FIFO) Memory, a Random Access Memory (RAM), a Read-Only Memory (ROM), and an internal logic module.
The embodiment of the invention provides a pixel data processing method and an integrated chip. The method comprises the following steps: if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency; determining a pixel format according to the actual parallel processing pixel number; and converting the number of pixels input by each clock of the pixel data into the pixel format. According to the technical scheme, the pixel number input by each clock is converted into the format capable of meeting the determined pixel number of actual parallel processing, so that the working frequency of pixel data processing is reduced, and the working stability of the integrated chip is improved.
Drawings
Fig. 1 is a flowchart of a pixel data processing method according to an embodiment of the present invention;
fig. 2 is a flowchart of a pixel data processing method according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of a hardware structure of an integrated chip according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an integrated chip processor according to a third embodiment of the present invention;
fig. 5 is a schematic diagram of a pixel data processing process according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures associated with the present invention are shown in the drawings, not all of them.
Example one
Fig. 1 is a flowchart of a pixel data processing method according to an embodiment of the present invention, which is applicable to a case of processing pixel data, and in particular, to a Video image processing system based on a Field Programmable Gate Array (FPGA) and an embedded system, and in particular, to a Video image processing system with a Video Electronics Standard Association (VESA) digital Video Interface standard (DP), a Mobile Industry Processor Interface standard (MIPI), and a High Definition Multimedia Interface standard (HDMI). The method may be performed by an integrated chip of a video image processing system, the integrated chip including but not limited to an FPGA, a Micro Controller Unit (MCU), a Digital Signal Processor (DSP), and the like.
As shown in fig. 1, the method specifically includes the following steps:
and S110, if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency.
Specifically, in the video image processing system, the higher the total number of pixels displayed on the panel, the higher the BPP or FR, the higher the operating frequency of processing the pixel data, and if the operating frequency (pixel clock) of processing the pixel data exceeds the effective operating frequency range, the stability of the integrated chip in processing the pixel data cannot be ensured, and the reliable operation of the video image processing system cannot be ensured. In this case, the present embodiment aims to meet the stability and reliability requirements of the system by calculating and adjusting the number of pixels actually processed in parallel. For example, under the condition that other influencing factors are not changed, the higher number of pixels actually processed in parallel is selected, so that the parallel processing efficiency can be improved, the working frequency of the integrated chip for processing pixel data is reduced, and panel display and frame rate with higher total number of pixels can be supported on the basis.
Illustratively, the effective operating frequency range includes a maximum operating frequency threshold supported by the integrated chip, and if the current operating frequency exceeds the maximum operating frequency threshold, the number of actually parallel-processed pixels needs to be calculated and adjusted, for example, when the number of pixels input per clock is 2, and the current operating frequency exceeds the maximum operating frequency threshold, the number of actually parallel-processed pixels can be adjusted to 4, so as to reduce the operating frequency for processing the pixel data.
And S120, determining a pixel format according to the actual parallel processing pixel number.
Specifically, the determined actual parallel-processed pixel number in this embodiment enables the integrated chip to operate at a lower operating frequency, and on the basis of determining the actual parallel-processed pixel number, the corresponding pixel format is determined according to the determined actual parallel-processed pixel number, and the determined actual parallel-processed pixel number is used as a basis for performing format conversion on the input pixel data.
And S130, converting the number of pixels input by each clock of the pixel data into the pixel format.
Specifically, the number of pixels input by each clock affects the parallel processing capability of the integrated chip, and the larger the number of pixels input by each clock is, the more complex the processing structure of the pixel data is, and the stronger the parallel processing capability is correspondingly. In this embodiment, the number of pixels per clock input of the pixel data is converted according to the determined pixel format, and in the case of conversion into the pixel format, the number of pixels actually entering the IP core is also identical to the determined number of pixels actually processed in parallel, thereby reducing the operating frequency of the integrated chip to a certain extent. It should be noted that after conversion, the number of pixels input per clock is no longer the influence factor of the operating frequency, and the main factor influencing the operating frequency is the number of pixels actually processed in parallel.
If the current working frequency belongs to the effective working frequency range (for example, is lower than the maximum working frequency threshold) after the adjustment of the actual parallel processing pixel number, the pixel data can be processed and output according to the current BPP, FR, the actual parallel processing pixel number and the like without other adjustments; if the current operating frequency still exceeds the effective operating frequency range after the adjustment of the actual parallel processing pixel number, further adjustment, such as reduction of BPP, reduction of FR, etc., is required until the operating frequency for processing the pixel data meets the effective operating frequency range.
Furthermore, in the process of adjusting the number of pixels actually processed in parallel to reduce the operating frequency, the actual usage size of the internal storage space needs to be adjusted in a coordinated manner to balance the internal and external resources of the storage device, especially the storage resources, thereby avoiding system instability and even system collapse caused by too high resource occupancy rate. After the adjustment of the number of pixels actually processed in parallel and the actually used size of the internal storage space, the internal storage space for caching the pixel data should also be in a state of stable operation of the memory, that is, the occupancy rate of the internal storage space is less than a certain boundary value. For FPGA, the boundary value is set to 90%, for example, if the buffered pixel data occupies more than 90% of the internal storage space in the current states of BPP, FR, the number of pixels actually processed in parallel, and the like, the stable operation of the integrated chip cannot be guaranteed.
In the pixel data processing method provided by the embodiment of the invention, the pixel number input by each clock is converted into the format capable of meeting the determined pixel number of the actual parallel processing, so that the working frequency of processing the pixel data is reduced, and the working stability of an integrated chip is improved.
Example two
Fig. 2 is a flowchart of a pixel data processing method according to a second embodiment of the present invention, which is optimized based on the second embodiment, and a process of adjusting a working frequency of pixel data is specifically described in this embodiment. In the embodiment, firstly, the working frequency of pixel data processing is reduced by adjusting the number of pixels actually processed in parallel; if the working frequency of the processed pixel data still exceeds the effective working frequency range after the actual parallel processing pixel number is adjusted, the BPP, FR and/or the step length of FR adjustment are further adjusted to enable the working frequency of the processed pixel data to be within the effective working frequency range, and the adjustment mode can quickly reduce the working frequency of the processed pixel data to be within the effective working frequency range, so that the running stability of the system is ensured.
In this embodiment, on the premise that the working frequency of processing the pixel data is within the effective working frequency range, the total pixel number displayed by the panel is further increased as much as possible, and the efficiency of processing the pixel data is further increased. It should be noted that technical details that are not described in detail in the present embodiment may be referred to any of the above embodiments.
Specifically, as shown in fig. 2, the method specifically includes the following steps:
s201, adjusting the number of pixels input by each clock, and determining the current working frequency of the processed pixel data.
In this embodiment, the adjustment of the number of pixels actually subjected to parallel processing is the most effective way to reduce the operating frequency, and in addition, the number of pixels input per clock and the number of pixels actually entering the IP core may be adjusted in advance. For example, in the process of processing pixel data, the adjustment of the operating frequency can be divided into three stages: firstly, pre-adjusting the number of pixels input by each clock in the working parameter range of the integrated chip, and determining the current working frequency; if the number of pixels input by each clock is adjusted in advance, the current working frequency cannot be guaranteed to belong to the effective working frequency range, the number of pixels actually entering an IP core is adjusted, meanwhile, the adjustment of the actual use size of the internal storage space is combined to optimize the working frequency, if the current working frequency cannot meet the effective working frequency range through the adjustment of the internal storage space, for example, under the scene that the higher resolution of 4K, 8K and the like needs to be supported, the requirement on the total number of pixels needing to be processed and output and displayed is higher, the actual demand is met by further adjusting the number of pixels actually processed in parallel, and the adjustment of the actual use size of the internal storage space is combined in the process.
S202, is the current operating frequency of the processed pixel data out of the effective operating frequency range? If yes, go to S203; if not, S209 is executed.
And S203, calculating the number of actually parallel processed pixels according to the frame rate, the number of bits of each pixel and the mapping relation between the number of actually parallel processed pixels and the working frequency, so that the working frequency corresponding to the number of actually parallel processed pixels is lower than the current working frequency.
Specifically, in this embodiment, the number of pixels that can satisfy the actual parallel processing that reduces the operating frequency may be determined according to the frame rate, the bit number BPP of each pixel, and the mapping relationship between the number of pixels actually subjected to the parallel processing and the operating frequency. Table 1 is a mapping table between frame rate, BPP, PPC, actual number of pixels processed in parallel and operating frequency.
TABLE 1 mapping relationship table between frame rate, BPP, PPC, actual parallel processing pixel number and operating frequency
As shown in table 1, after being converted, the number of pixels per clock input is no longer a factor of the operating frequency, but is the number of pixels actually processed in parallel. Wherein, BPP and operating frequency are in positive correlation, FR and operating frequency are in positive correlation, and the number of pixels actually processed in parallel is in negative correlation with the operating frequency. According to the mapping relation shown in table 1, when the current working frequency exceeds the effective working frequency range, the frame rate and the BPP can be kept unchanged, and a higher number of pixels for actual parallel processing is selected to reduce the working frequency; if the operating frequency still cannot meet the effective operating frequency range by only adjusting the number of pixels actually processed in parallel, further adjustment of BPP and/or FR is required.
It should be noted that table 1 only gives some exemplary values of frame rate, BPP, and PPC. In practical applications, the panel usually supports a frame rate range, such as 30-60 Hz, 60-120 Hz, 75-144 Hz, etc.; the BPP supported in the video image processing system comprises: 18. 24, 30, 36, 48, etc., under the condition that other influencing factors are not changed, the working clock is improved by about 25% when the BPP is 48 compared with the IP core working clock when the BPP is 24, and the improvement of the actual working clock is closely related to the type of the device which is actually used.
In some embodiments, the effective operating frequency range is related to the type of the IP core of the integrated chip, and generally refers to a nominal range, such as 80-135 MHz, which enables the IP core of the integrated chip to operate normally and process data.
And S204, determining a pixel format according to the actual parallel processing pixel number.
And S205, converting the number of pixels input by each clock into the pixel format.
And S206, according to the number of pixels input by each clock and the number of pixels actually processed in parallel, adjusting the actually used size of the internal storage space, and caching the pixel data into the internal storage space.
Specifically, in this embodiment, the actual size of the internal storage space is adaptively adjusted, and the unprocessed pixel data is buffered in cooperation with the conversion process of the pixel data. It should be noted that the present embodiment does not limit the execution sequence of S206 and S203-S205, that is, in the process of processing the relationship between the number of pixels input per clock and the number of pixels actually processed in parallel, the input pixel data or the converted output pixel data can be flexibly buffered, the internal storage space of the memory can be efficiently utilized, and the efficiency of pixel data processing can be improved.
S207, the working frequency corresponding to the actual parallel-processed pixel number still exceeds the effective working frequency range? If yes, executing S207; otherwise, S209 is executed.
And S208, adjusting at least one of the frame rate, the frame rate adjusting step length or the number of bits of each pixel, so that the working frequency corresponding to the number of pixels actually processed in parallel belongs to the effective working frequency range.
Specifically, if the operating frequency corresponding to the actual parallel-processed pixel number still exceeds the effective operating frequency range, the operating frequency corresponding to the actual parallel-processed pixel number is made to belong to the effective operating frequency range by at least one of the following manners: adjusting the frame rate; adjusting the frame rate adjustment step length; the number of bits per pixel is adjusted.
Specifically, the number of pixels actually processed in parallel (and the actually used size of the corresponding internal storage space) is a main factor affecting the pixel data processing performance, in this embodiment, the internal storage space of the memory is utilized as much as possible to increase the number of pixels actually processed in parallel, so as to increase the frame rate and BPP value as much as possible, and achieve the pixel data processing or display performance as high as possible. If the working frequency corresponding to the actual parallel processing pixel number still exceeds the effective working frequency range after the adjustment, other parameters are further adjusted to obtain that the working frequency corresponding to the actual parallel processing pixel number belongs to the effective working frequency range.
For example, the frame rate adjustment may specifically be: the frame rate is adjusted in a decreasing manner according to the step length of the frame rate adjustment from the upper limit of the frame rate that the panel can support, so that the operating frequency corresponding to the number of pixels actually processed in parallel is reduced to the effective operating frequency range, and the panel can display at the optimal frame rate (the highest frame rate satisfying the effective operating frequency range).
For example, the step length for adjusting the frame rate may specifically be: the step length of frame rate adjustment is increased preferentially, and the frame rate is roughly adjusted so as to obtain the display frame rate under the condition that the panel can stably operate within the shortest adjustment time.
For example, the adjusting the number of bits of each pixel may specifically be: the number of bits per pixel is preferably reduced to ensure stable display of the panel in the shortest adjustment time.
S209, adjusting at least one of the digit of each pixel, the frame rate adjusting step length, the frame rate, the actual parallel processing pixel number and the actual using size of the internal storage space, so as to increase the total pixel number of the panel display.
In this embodiment, on the premise that the operating frequency corresponding to the actual number of pixels processed in parallel belongs to the effective operating frequency range, the total number of pixels displayed on the panel is increased as much as possible by adjusting the parameters on the premise that the stability of the integrated chip for processing the pixel data is ensured, and the pixel data processing efficiency and the display performance are improved.
For example, the frame rate adjustment may specifically be: and starting from the lower limit of the frame rate which can be supported by the panel, adjusting the frame rate in an incremental mode according to the step length of the frame rate adjustment so as to ensure that the panel can display at the optimal frame rate.
Further, the step length for adjusting the frame rate may specifically be: the frame rate adjustment step length is preferentially reduced, and the fine adjustment of the frame rate can be realized by using a smaller step length, thereby being beneficial to obtaining the optimal frame rate.
Further, the adjusting the number of bits of each pixel may specifically be: the bit number (BPP) of each pixel is preferentially increased, so that the display capability of the panel is improved as much as possible on the premise that the working frequency corresponding to the number of pixels which are actually processed in parallel is reduced to an effective working frequency range.
Furthermore, other parameters are preferentially adjusted, and when the adjustment of other parameters cannot meet the actual requirement, the pixel number of the actual parallel processing is adjusted again, and the pixel number of the actual parallel processing can be unchanged or reduced, so that the basic operation of the panel is completed under the condition of not adjusting as much as possible.
Through the adjustment, the total pixel number displayed by the panel can be improved, so that the performance of the panel and a video image processing system is balanced, and the capability of stable display and output of the panel is achieved.
And S210, processing and outputting the pixel data.
The operation parameter adjustment process is described below by way of an example. The present example adjusts the operating frequency of pixel data processing based on the mapping relationship shown in table 1. Illustratively, for a support panel in a video image processing system, the total number of pixels is calculated as: 8888000, respectively; when the BPP is 48, the working clock is improved by about 25 percent compared with the IP verification working clock when the BPP is 24; the effective operating frequency range of the IP core is: 80-135 MHz; the actual frame rate range of the panel is: 30-75 Hz; the number of pixels input per clock has values of 1, 2, 4.
Illustratively, the operating frequency may be adjusted in different ways in the following priority order:
1) increasing or decreasing the number of pixels of the actual parallel processing entering the IP core;
2) adjusting the actual use size of the internal storage space of the memory, wherein the memory comprises an FIFO (first in first out), an RAM (random access memory), an ROM (read only memory), a logic module and the like;
3) increasing or decreasing the step size of the frame rate adjustment;
4) increasing or decreasing the number of bits per pixel;
5) the frame rate is increased or decreased.
For 1), preferentially increasing the number of pixels entering an IP core to improve the image processing capability, thereby effectively improving the pixel data processing efficiency and reducing the working frequency;
for 3), preferentially increasing the step length of frame rate adjustment, and roughly adjusting the frame rate to obtain the display frame rate under the condition that the panel can basically run in the shortest adjustment time;
for 4), the number of bits of each pixel is preferentially reduced to ensure that the panel can stably display;
for 5), it is preferred to try from the upper limit of the frame rate that the panel can support, and adjust in a decreasing manner to enable the panel to display at the optimal frame rate while lowering the operating frequency.
Illustratively, the total number of pixels of the panel display may be increased in different ways in the following priority order:
1) increasing or decreasing the number of bits per pixel;
2) increasing or decreasing the frame rate;
3) increasing or decreasing the step size of the frame rate adjustment;
4) increasing or decreasing the number of pixels entering the IP core;
5) the storage used inside the adjusting device comprises FIFO, RAM, ROM, logic module and the like.
For 1), preferentially increasing the number of bits of each pixel to improve the display capability of the panel;
for 2), the method preferentially tries from the lower limit of the frame rate which can be supported by the panel, and the method is adjusted in an incremental mode so that the panel can display at the optimal frame rate on the premise of stable operation;
for 3), preferentially reducing the step length of frame rate adjustment, and finely adjusting the frame rate to obtain the display frame rate under the optimal performance under the condition of adapting to the performance improvement strategy;
for 4), the number of pixels of the actual parallel processing entering the IP core is preferentially reduced or not changed, and stable display of the panel is completed without adjustment.
The pixel data processing method provided by the second embodiment of the invention is optimized on the basis of the above embodiment, firstly, the working frequency of the processed pixel data is reduced by adjusting the actual parallel-processed pixel number, and then the BPP, FR and/or the step length of FR adjustment can be further adjusted so as to enable the working frequency of the processed pixel data to be within the effective working frequency range, thereby quickly and effectively reducing the working frequency of the processed pixel data to be within the effective working frequency range and ensuring the stability of system operation; and each parameter is flexibly adjusted according to a certain priority order, so that the total pixel number displayed by the panel is improved, and the pixel data processing efficiency and the panel display performance are further improved.
EXAMPLE III
Fig. 3 is a schematic diagram of a hardware structure of an integrated chip according to a third embodiment of the present invention. The integrated chip can be FPGA, MCU, DSP, etc. As shown in fig. 3, the integrated chip provided in this embodiment includes: a processor 310 and a memory 320; the memory 320 is used for buffering pixel data. The number of the processors 310 in the integrated chip may be one or more, and fig. 3 illustrates one processor 310, and the processor 310 and the memory 320 may be connected by a bus or other means, and fig. 3 illustrates the connection by a bus.
The memory 320 is also used to store one or more programs, which are executed by the processor 310, so that the processor 310 realizes the pixel data processing method described in any of the above embodiments, as a computer-readable storage medium.
Fig. 4 is a schematic structural diagram of an integrated chip processor according to a third embodiment of the present invention. As shown in fig. 4, the processor 310 is provided with:
the parallel data control module 20 is configured to determine an actual parallel-processed pixel number if a current working frequency of the processed pixel data exceeds an effective working frequency range, so that the working frequency corresponding to the actual parallel-processed pixel number is lower than the current working frequency;
the data conversion module 30 is used for determining a pixel format according to the actual parallel processing pixel number;
and an input data control module 10 for converting the number of pixels of the pixel data input per clock into the pixel format.
In the integrated chip provided by the third embodiment of the present invention, the number of pixels input per clock is converted into a format that can meet the determined number of pixels actually processed in parallel, so as to reduce the operating frequency of processing pixel data and improve the operating stability of the integrated chip.
On the basis of the above embodiment, the method further includes:
and the memory state control module is used for adjusting the actual use size of the internal storage space of the memory according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching the pixel data into the internal storage space of the memory.
On the basis of the above embodiment, the memory 320 includes at least one of: FIFO memory, RAM, ROM, internal logic module.
Further, the parallel data control module 20 is configured to calculate the number of pixels actually processed in parallel according to a mapping relationship between a frame rate, the number of bits of each pixel, and the number of pixels actually processed in parallel and an operating frequency, so that the operating frequency corresponding to the number of pixels actually processed in parallel is lower than the current operating frequency.
Further, the parallel data control module 20 is further configured to, if the working frequency corresponding to the actual parallel-processed pixel number still exceeds the effective working frequency range, enable the working frequency corresponding to the actual parallel-processed pixel number to belong to the effective working frequency range by at least one of the following manners:
adjusting the frame rate;
adjusting the step length of the frame rate adjustment;
and adjusting the number of bits of each pixel.
Further, the parallel data control module 20 is further configured to increase the total pixel count of the panel display by at least one of the following manners:
adjusting the number of bits of each pixel;
adjusting the frame rate adjustment step length;
adjusting the frame rate;
adjusting the number of pixels actually processed in parallel;
the actual size of the internal storage space is adjusted.
Fig. 5 is a schematic diagram of a pixel data processing process according to a third embodiment of the present invention. As shown in fig. 5, the input data control module 10 is used to effectively control the number of pixels input per clock to adapt to the requirement of the number of pixels of the actual parallel processing entering the IP core.
The parallel data control module 20 is configured to calculate the number of pixels actually processed in parallel in the IP core, and dynamically adjust the usage states of the input data control module 10, the data conversion module, and the internal storage space of the memory according to the calculation result, for example, when the number of pixels actually processed in parallel is determined and the available storage in the memory does not meet the requirement of pixel data processing, the input data control module 10 may be adjusted to control the actual PPC and relieve the internal storage pressure.
And the memory state control module 40 is used for processing pixel data such as caching.
And the data conversion module 30 is configured to determine a format corresponding to the actual parallel-processed pixel number, notify the input data control module 10 of converting the PPC into a format actually entering the IP core, and output an enable signal of the pixel actually entering the IP core to control actual pixel output.
The memory state control module 40 may cooperate to implement two functions: one is used for inputting the adjustment of the number of pixels that the data control module inputs for each clock; and the other for parallel processing pixel data and enabling adjustments of the data actually entering the IP core by the parallel data control block 20 and the data conversion block 30.
In the pixel data processing process, the parallel data control module 20 determines the number of pixels actually processed in parallel and informs the data conversion module 30 of the need for parallel processing; the data conversion module 30 determines the corresponding format and informs the input data control module 10, and the input data control module 10 converts the input PPC into the format required by the parallel data control module 20; the memory state control module 40 buffers the pixel data to match with the adjustment of the input data control module 10 to the PPC and the adjustment of the parallel data control module 20 and the data conversion module 30 to the actual parallel-processed pixel number, so as to finally make the working frequency within the effective working frequency range and support the panel display with higher pixel number.
The data conversion module 30 determines the format of the parallel pixels to be converted, for example, 2, 4 or higher, and issues a request to the input data control module 10 to issue the number of pixels to be processed in parallel, and the input data control module 10 starts a process of converting the PPC into a format suitable for the number of pixels to be processed in parallel, where the process includes more conversion requirements such as pixel width conversion and bit conversion, and after the process is started, the process notifies the PPC adjustment part of the memory state control module 40 according to a preset storage mode, and calls a corresponding internal storage space to complete format conversion.
The integrated chip proposed by the present embodiment and the pixel data processing method proposed by any of the above embodiments belong to the same inventive concept, and technical details that are not described in detail in the present embodiment can be referred to any of the above embodiments, and the present embodiment has the same beneficial effects as performing the pixel data processing method.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
1. A pixel data processing method is applied to an integrated chip of a video image processing system, and is characterized by comprising the following steps:
if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency;
determining a pixel format according to the actual parallel processing pixel number;
converting the number of pixels of the pixel data input by each clock into the pixel format;
the determining the number of pixels actually processed in parallel comprises:
according to the mapping relation among the frame rate, the number of bits of each pixel, the number of pixels actually processed in parallel and the working frequency, the number of pixels actually processed in parallel is calculated, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency, the number of pixels actually processed in parallel is increased by utilizing the internal storage space of the memory, the frame rate and the number of bits of each pixel are increased, and high display performance is achieved.
2. The method of claim 1, further comprising:
and adjusting the actual use size of an internal storage space according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching pixel data into the internal storage space.
3. The method of claim 1, further comprising:
if the working frequency corresponding to the actual parallel processing pixel number still exceeds the effective working frequency range, the working frequency corresponding to the actual parallel processing pixel number is made to belong to the effective working frequency range by at least one of the following modes:
adjusting the frame rate;
adjusting the step length of the frame rate adjustment;
and adjusting the number of bits of each pixel.
4. The method of claim 3, wherein the adjusting the frame rate comprises:
and starting from the upper limit of the frame rate which can be supported by the panel, adjusting the frame rate in a descending manner according to the step length of the frame rate adjustment.
5. The method according to any one of claims 1-4, further comprising: and improving the total pixel number of the panel display by at least one of the following modes:
adjusting the number of bits of each pixel;
adjusting the frame rate adjustment step length;
adjusting the frame rate;
adjusting the pixel number of actual parallel processing;
and adjusting the practical use size of the internal storage space.
6. The method of claim 5, further comprising, prior to said determining a number of pixels to be actually processed in parallel:
and adjusting the number of pixels input by each clock of the pixel data, and determining the current working frequency of the processed pixel data.
7. An integrated chip, comprising: a processor and a memory;
the memory is used for caching pixel data;
the processor is provided with:
the parallel data control module is used for determining the actual parallel processing pixel number if the current working frequency of the pixel data to be processed exceeds the effective working frequency range, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency;
the data conversion module is used for determining a pixel format according to the actual parallel processing pixel number;
the input data control module converts the number of pixels input by each clock of the pixel data into the pixel format;
the determining the number of pixels actually processed in parallel comprises:
according to the mapping relation among the frame rate, the number of bits of each pixel, the number of pixels actually processed in parallel and the working frequency, the number of pixels actually processed in parallel is calculated, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency, the number of pixels actually processed in parallel is increased by utilizing the internal storage space of the memory, the frame rate and the number of bits of each pixel are increased, and high display performance is achieved.
8. The integrated chip of claim 7, further comprising:
and the memory state control module is used for adjusting the actual use size of the internal storage space of the memory according to the pixel number input by each clock and the actual parallel processing pixel number, and caching the pixel data into the internal storage space of the memory.
9. The integrated chip of claim 7, wherein the memory comprises at least one of: FIFO memory, RAM, ROM, and internal logic module.
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