CN111755052A - Nonvolatile memory, nonvolatile memory system, and read and write methods

Info

Abstract

Description

Claims

CN111755052A

Publication number: CN111755052A
Application number: CN202010754428.0A
Authority: CN
Inventors: 庞理; 韩小炜
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2020-10-09

The invention relates to a non-volatile memory comprising a plurality of memory cells and an AND module, the non-volatile memory being configured to: in response to a received read address, reading states of at least two memory cells coupled in storage bits of the read address, and passing the read states of the at least two memory cells to the AND module, wherein the AND module is configured to perform an AND operation on the read states of the at least two memory cells to obtain data stored in the read address. The invention also relates to a non-volatile memory system, a method of reading from and writing to a non-volatile memory.

Nonvolatile memory, nonvolatile memory system, and read and write methods

Technical Field

The present invention relates to the field of memory technology, and in particular to non-volatile memories, non-volatile memory systems, and methods of reading and writing to non-volatile memories.

Background

A semiconductor memory is an electronic data storage device implemented on a semiconductor-based integrated circuit. Examples of the semiconductor memory may include volatile memory and nonvolatile memory. Volatile memories require an applied voltage to retain stored information, while non-volatile memories do not.

Examples of the nonvolatile Memory may include a Flash Memory (Flash Memory), a Resistive Random Access Memory (RRAM), a Phase Change Random Access Memory (PRAM), a Conductive-Bridging Random Access Memory (CBRAM), a Ferroelectric Random Access Memory (FRAM), and a Magnetoresistive Random Access Memory (MRAM). The Flash memory stores data by changing the charge state in the floating grid; RRAMs store data using a variable resistance material such as a composite metal oxide whose resistance value changes when a voltage is applied; PRAMs store data by modifying the state of the substance from which the device is fabricated; CBRAM uses programmable metal elements as solid-state electrodes to store data, the number of metal ions in the solid-state electrodes changing when a voltage is applied; FRAM stores data using a ferroelectric layer; also, the MRAM stores data using a magnetic storage element formed of two ferromagnetic plates.

In recent years, various semiconductor memories having improved performance have been proposed. However, further improvements in the performance of semiconductor memories have been a goal in the art.

Disclosure of Invention

The inventive concept is based on the recognition that many factors can cause variations in the data stored in semiconductor memories, particularly non-volatile memories. Accordingly, the inventive concept proposes to improve the performance of the semiconductor memory by securing data reliability.

According to a first aspect of the present invention, there is provided a non-volatile memory, wherein the non-volatile memory comprises a plurality of memory cells and an and module, the non-volatile memory being configured to:

in response to receiving a read command and a read address, reading the state of at least two memory cells coupled in a storage bit of the read address, an

Transferring the read states of the at least two memory cells to the AND module,

wherein the AND module is configured to AND the read states of the at least two memory cells to obtain the data stored in the read address.

According to a second aspect of the present invention, there is provided a nonvolatile memory, wherein the nonvolatile memory includes:

a first memory array and a second memory array, each of the first memory array and the second memory array comprising a plurality of stored bits, each of the plurality of stored bits corresponding to an access address of the memory array;

a first read circuit connected with the first memory array and configured to read a state of a storage bit of a read address in the first memory array in response to a received read command and read address;

a second read circuit connected with the second memory array and configured to read a state of a storage bit of the read address in the second memory array in response to the read command and the read address;

and a module, an input terminal of the and module being connected to an output terminal of the first read circuit and an output terminal of the second read circuit, and the and module being configured to perform an and operation on an output of the first read circuit and an output of the second read circuit to obtain the data stored in the read address.

According to a third aspect of the present invention there is provided a non-volatile memory system comprising a non-volatile memory according to the first or second aspect above.

According to a fourth aspect of the present invention, there is provided a method of reading from and writing to a non-volatile memory, wherein the non-volatile memory comprises a plurality of memory cells, wherein the method comprises:

receiving a read command and a read address;

reading states of at least two memory cells coupled in storage bits of the read address; and

and operations are performed on at least two states read from the at least two memory cells to obtain data stored in the read address.

According to a fifth aspect of the present invention, there is provided a method of reading from and writing to a non-volatile memory, wherein the non-volatile memory comprises a first memory array and a second memory array, each of the first memory array and the second memory array comprising a plurality of stored bits, each of the plurality of stored bits corresponding to an address;

wherein the method comprises:

receiving a read command and a read address;

reading a state of a storage bit of the read address of the first memory array;

reading a state of a storage bit of the read address of the second memory array; and

and the states read from the two storage bits of the read address to obtain the data stored in the read address.

It will be appreciated by those skilled in the art that the technical effects as set forth in relation to the first aspect of the invention can be achieved according to the second to fifth aspects of the invention. The nonvolatile memory, the nonvolatile memory system and the reading and writing method thereof can improve the reliability of stored data.

Drawings

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made to the accompanying drawings, in which:

FIG. 1 illustrates a schematic diagram of a RRAM memory cell of the 1T1R structure;

fig. 2A to 2C illustrate an initial state, a high resistance state, and a low resistance state of the variable resistor of the RRAM;

FIG. 3 illustrates a memory array based on 1T1R memory cells, according to one example of an embodiment of the invention;

FIGS. 4A and 4B illustrate schematic diagrams of an ideal distribution probability and an actual distribution probability of a current read from a memory cell;

FIG. 5 illustrates a schematic diagram of a memory structure according to one example of an embodiment of the invention;

FIG. 6A illustrates a schematic diagram of a memory cell structure storing bits in accordance with one embodiment of the invention;

FIG. 6B is a schematic diagram illustrating a distribution probability of a read current for one embodiment of the memory cell structure of FIG. 6A;

FIG. 7 illustrates a flow diagram of a method of reading from and writing to non-volatile memory according to one embodiment of the invention;

FIG. 8 illustrates a flow diagram of a method of reading and writing to the memory of FIG. 5 according to one embodiment of the invention; and

FIG. 9 illustrates a block diagram of a memory system, according to an embodiment of the invention.

Detailed Description

RRAM is a type of nonvolatile memory. The physical mechanism of RRAM is a defect theory, and information is stored by a resistance state of a resistance change material, and a change in the resistance state is changed by an external voltage. FIG. 1 illustrates a schematic diagram of the 1T1R structure of an RRAM memory cell. The RRAM memory cell shown in fig. 1 includes a variable resistor R and a transistor T having a drain, a gate and a source connected to a negative pole of the variable resistor R, a word line WL and a source line SL, respectively, and a positive pole connected to a bit line BL.

The variable resistor R is composed of two layers of

conductive material

3, 4 and a layer of resistive dielectric material 2 sandwiched therebetween. Fig. 2A to 2C show three resistance states of the variable resistance of the RRAM. Specifically, fig. 2A shows an initial state of the variable resistor, and the newly prepared resistive dielectric material layer 2 exhibits a relatively high resistance value. By applying a suitable voltage across the two layers of

conductive material

3, 4 for initialisation, a conductive filament 6 can be formed across the layer 2, as shown in figure 2B. Since the conductive filaments 6 are conductive paths through the layer 2, the layer 2 with the conductive filaments 6 exhibits a relatively low electrical resistance. Fig. 2C shows that applying a "reset" voltage across the two

layers

3, 4 of conductive material will result in the formation of a break 8 in the conductive filament 6, the break 8 having a relatively high resistance, such that the layer 2 exhibits a relatively high resistance (high resistance state). Application of a "set" voltage across the two

layers

3, 4 of conductive material will cause the conductive filaments at the break 8 to recover, causing the layer 2 to exhibit a relatively low resistance (low resistance state). The high resistance state of layer 2 obtained by "reset" in fig. 2C may represent a digital signal state "0", while the low resistance state of layer 2 obtained by "set" in fig. 2B may represent a digital signal state "1".

FIG. 3 illustrates one embodiment of a memory array 300 based on 1T1R memory cells. In the embodiment of FIG. 3, memory array 300 includes a main array 310 of a plurality of 1T1R memory cells arranged in rows and columns and a reference array 330 of a column of 1T1R memory cells, the memory cells of each row in main array 310 being coupled by word lines to the memory cells of the same row in reference array 330. The memory array 300 of FIG. 3 also includes a row decoder 350 and a column decoder 360, where the row decoder 350 and the column decoder 360 parse received address commands to identify memory cells that need to be written to or read from. Specifically, the row decoder 350 performs the selection and driving operation of the word line wl (i), i being 0, 1, … …, x-1; the column decoder 350 selects a connection state between the global bit line GBL and each bit line bl (j) to be output and a connection state between the global source line GSL and each source line sl (j) to be output, j being 0, … …, y-1, according to a column address. In writing data, appropriate drive voltages are applied to the selected word line wl (i), and thus to the gates of the transistors to which the selected word line wl (i) is connected, and appropriate voltages are applied to the global bit line GBL and global source line GSL, and thus to the selected bit line bl (j) and selected source line sl (j), to effect writing of the selected memory cell. Global source line GSL is connected to a positive input of Current Sense Amplifier (CSA) 362. In reading data, a read voltage is applied to the global bit line GBL by applying an appropriate drive voltage to the selected word line wl (i), and the read voltage is applied to the selected memory cell through the selected bit line bl (j), so that the current Icell flowing through the selected memory cell flows out to the positive input of the current sense amplifier 362 via the selected source line sl (j) and the global source line GSL. In addition, a reference current Iref flowing on a corresponding row of memory cells in the reference array 330 is input to a negative input of a current sense amplifier 362 via a current buffer 332, and the current sense amplifier 362 compares the current Icell and the reference current Iref to obtain a state of the selected memory cell. It should be understood that fig. 3 illustrates only one example of an embodiment of the invention, and that any other suitable example will occur to those of skill in the art. For example, the connection state of the global source line GSL and each source line sl (j) may be selected by the row decoder 350 according to a row address.

FIG. 4A illustrates a schematic diagram of the probability of an ideal distribution of current read from a memory cell. Current I flowing through variable resistor in high resistance state_HLower current I flowing through the variable resistor in the low resistance state_LHigher. The resistance of the variable resistor of the memory cell is substantially normally distributed in either a high resistance state or a low resistance state due to variations in manufacturing process, write circuit path, power supply state, and the like, so that the current I_HAnd current I_LAnd also generally follows a normal distribution. Ideally, it is desirable to reference the current I_REFSet at a current I_HAnd current I_LIn the middle, the margin for reading "0" is made the same as the margin for reading "1", i.e., Δ_H＝Δ_L＝(I_L-I_H)/2. However, recovering the break 8 (set, write "1") is easy, and forming the break 8 (reset, write "0") is difficult. In other words, the failure rate for writing a "0" is higher than the failure rate for writing a "1". This results in a high resistance state current I_HThe actual probability distribution of (a) will not be as ideal as shown in fig. 4B. If the reference current I is still chosen according to the ideal situation_REFThen readThe margin for taking "0" is less than the margin for reading "1", i.e. Δ_H<Δ_L＝(I_L-I_H)/2. Many nonvolatile memories have such a phenomenon that writing "1" is easy and writing "0" is difficult, which is particularly serious in RRAM. It is based on this recognition that various embodiments of the present invention have been proposed.

The following description sets forth example embodiments according to the present disclosure. Other example embodiments and implementations will be apparent to those of ordinary skill in the art. Further, those of ordinary skill in the art will recognize that a variety of equivalent techniques may be applied in place of or in combination with the embodiments discussed below, and all such equivalents are to be considered encompassed by the present disclosure.

According to a first aspect of the present invention, there is provided a non-volatile memory, wherein the non-volatile memory comprises a plurality of memory cells and an and module, the non-volatile memory may be configured to:

In embodiments of the present invention, the state of a memory cell refers to a digital signal state of "0" or "1" as described above, which can be used to determine whether the stored data is a "0" or a "1". Those skilled in the art will appreciate that the AND block may be implemented by an AND gate or a combination of a NAND gate and a NOT gate.

According to a particular embodiment of the first aspect of the present invention, the plurality of memory cells may be divided into a plurality of memory bits, and each memory bit of the plurality of memory bits may comprise at least two memory cells coupled. In an embodiment of the first aspect of the present invention, the access address of the memory corresponds to a storage bit of the memory, and the storage bit refers to one or more memory cells corresponding to the access address of the memory. In other words, the physical address of one or more memory units contained in the storage bit corresponding to the access address can be obtained according to the access address of the memory.

According to one embodiment of the first aspect of the present invention, the non-volatile memory is configured such that at least two memory cells coupled in respective storage bits are used to store the same write data. In embodiments of the present invention, "coupled" means that a plurality of memory cells are associated with each other, and such association may be through a line connection or may refer to an access of the plurality of memory cells coupled through decoding of an access address.

According to a preferred embodiment of the first aspect of the present invention, each of the plurality of memory bits comprises two memory cells coupled. In other words, two memory cells are used as one storage bit. Assuming a memory cell write "0" failure rate f₀Far greater than the failure rate f for writing "1₁I.e. f₀>>f₁If the state read from one of the two memory cells is "0" and the state read from the other memory cell is "1", the storage bit in which the two memory cells are located is assumed to store data of "0". This configuration of using two memory cells as one storage bit may also be referred to as a dual-modular redundancy configuration, with the states read from the memory cells and the output states of the storage bits as shown in table 1 below:

TABLE 1 read State vs. output State relationship

Thus, according to embodiments of the present invention, the actual failure rates for writing a "1" and writing a "0" are shown in tables 2 and 3 below:

TABLE 2 failure rate for write "1

TABLE 3 failure rate for writing "0

In one embodiment, the error correction capability (e.g., ECC error correction rate) of the ECC of the memory system is 0.66% with fee 30bit/568B, whereas the failure rate of the memory cell write "1" is f₁0.1%, the failure rate of the memory cell to write a "0" is f₀5% (obviously, f)₀Beyond the error correction capability of ECC). Table 4 showsThe actual failure rates of the dual modular redundancy configuration and the non-dual modular redundancy configuration of the above embodiments are given.

TABLE 4 actual failure rates for dual and non-dual modular redundancy configurations

Failure rate	Non-dual modular redundancy configuration	Dual modular redundancy configuration
			f₁	0.1％	0.2％
f₀	5％	0.25％

As can be seen from Table 4, the failure rate f of the final write "0" is greatly reduced by using the method of an embodiment of the present invention₀，f₁<fcc and f₀<The failure rates of fecc, i.e. write "0" and write "1", are both within the range of ECC error correction capability. Thus, this dual modular redundancy configuration is well suited to memories where the failure rates of write "0" and write "1" are severely mismatched.

According to one embodiment of the first aspect of the present invention, wherein each memory cell is uniquely addressable by a combination of a word line and a bit line, and the two memory cells coupled in each memory bit are addressable by a single word line and a paired bit line. In other words, the two memory cells in each memory bit are in different columns of the same row.

According to another embodiment of the first aspect of the present invention, wherein each memory cell is uniquely addressable by a combination of a word line and a bit line, and the two memory cells coupled in each memory bit are addressable by a pair of word lines and a single bit line. In other words, the two memory cells in each memory bit are in different rows of the same column.

However, embodiments of the invention are not limited to the use of two memory cells as one memory bit, and in some embodiments of the first aspect of the invention, each of the plurality of memory bits may include more than two coupled memory cells.

According to an embodiment of the first aspect of the present invention, wherein each memory cell of the plurality of memory cells may be selected from one of: flash Memory cells, phase change Random Access Memory (PRAM) cells, Resistive Random Access Memory (RRAM) cells, Programmable Metallization Cells (PMC), Conductive Bridging Random Access Memory (CBRAM) cells, Ferroelectric Random Access Memory (FRAM) cells, Magnetoresistive Random Access Memory (MRAM) cells, and Spin Transfer Torque Random Access Memory (STT-MRAM) cells.

It will be understood by those skilled in the art that the access address of the memory array may correspond to a read address of the memory when data is read, or may correspond to a write address of the memory when data is written. According to an embodiment of the second aspect of the present invention, the first memory array and the second memory array may be configured to store the same write data at respective storage bits of the same access address. In one embodiment, when writing data, the first and second memory arrays receive the same write command and write address, the write command including write data, such that the stored bits of the write address of the first memory array store the write data (e.g., "0"), and the stored bits of the same write address of the second memory array also store the write data ("0").

In an embodiment of the second aspect of the invention, each access address of the memory corresponds to one stored bit of the first memory array and one stored bit of the second memory array, the stored bits referring to the one or more memory cells to which the access address of the memory array corresponds, since the first memory array and the second memory array will receive the same access address. In other words, the physical address of one or more memory cells contained in the storage bit corresponding to the access address can be obtained according to the access address of the memory array.

According to an embodiment of the second aspect of the invention, wherein the non-volatile memory may further comprise:

a row decoder connected with the first memory array and the second memory array and configured to select a row in the first memory array and a row in the second memory array to be accessed according to a received row address;

a first column decoder connected with the first memory array and configured to select a column of the first memory array to be accessed according to a received column address; and

a second column decoder connected with the second memory array and configured to select a column in the second memory array to be accessed according to the received column address.

It will be appreciated by those skilled in the art that in the second aspect of the invention, the first read circuit may be implemented by a current buffer, a row decoder, a first column decoder and a current sense amplifier as described above. Specifically, for example, a row decoder selects and drives a word line WL according to a read address, a first column decoder selects a bit line BL and a source line SL, a current buffer reads a current fed back from the source line SL of a memory cell selected with the word line WL in a reference array, the first column decoder outputs the current of the selected memory cell in the first memory array, and then a current sense amplifier compares the two currents and outputs a digital signal state "0" or "1" (i.e., a state of a storage bit of the read address in the first memory array). The implementation of the second read circuit is similar to the implementation of the first read circuit.

According to one embodiment of the second aspect of the present invention, wherein each of the plurality of memory bits may include one or more memory cells.

According to a particular embodiment of the second aspect of the present invention, wherein each of the one or more memory cells may be selected from one of the following: a flash memory cell, a phase change random access memory cell, a resistive random access memory cell, a programmable metallization cell, a conductive bridging random access memory cell, a ferroelectric random access memory cell, a magnetoresistive random access memory cell, and a spin transfer torque random access memory cell.

According to a third aspect of the present invention, there is provided a non-volatile memory system, wherein the non-volatile memory system may comprise the non-volatile memory according to the first or second aspect described above.

According to an embodiment of the third aspect of the present invention, wherein the non-volatile memory system may comprise a controller configured to resolve the received address signals into a row address and a column address.

According to a fourth aspect of the present invention, there is provided a method of reading from and writing to a non-volatile memory comprising a plurality of memory cells, wherein the method comprises:

receiving a read command and a read address;

According to one embodiment of the fourth aspect of the present invention, wherein the plurality of memory cells may be divided into a plurality of memory bits, and each of the plurality of memory bits comprises at least two memory cells coupled. In an embodiment of the fourth aspect of the present invention, the access address of the memory is in one-to-one correspondence with the storage bit of the memory, which refers to one or more memory cells to which the access address of the memory corresponds. In other words, the physical address of one or more memory units contained in the storage bit corresponding to the access address can be obtained according to the access address of the memory.

According to an embodiment of the fourth aspect of the invention, wherein the method may comprise:

receiving a write address and a write command containing write data; and

writing the same write data to at least two memory cells coupled in storage bits of the write address.

According to a preferred embodiment of the fourth aspect of the present invention, wherein each of the plurality of memory bits may comprise two memory cells coupled, wherein each memory cell is uniquely addressed by a combination of a word line and a bit line.

According to one embodiment of the fourth aspect of the present invention, the two memory cells coupled in each storage bit are addressable by a single word line and a pair of bit lines. In other words, the two memory cells in each memory bit are in different columns of the same row.

According to another embodiment of the fourth aspect of the present invention, the two memory cells coupled in each storage bit are addressable by a pair of word lines and a single bit line. In other words, the two memory cells in each memory bit are in different rows of the same column.

According to an embodiment of the fourth aspect of the present invention, each memory cell of the plurality of memory cells may be selected from one of: the memory comprises a flash memory bit unit, a phase change random access memory unit, a resistance change random access memory unit, a programmable metallization unit, a conductive bridging random access memory unit, a ferroelectric random access memory unit, a magnetic resistance random access memory unit and a spin transfer torque random access memory unit.

According to one embodiment of the fourth aspect of the invention, each storage bit may comprise more than two coupled memory cells.

According to a fifth aspect of the present invention, there is provided a method of reading from and writing to a non-volatile memory, wherein the non-volatile memory may include a first memory array and a second memory array, each of the first memory array and the second memory array may include a plurality of memory bits, each of the plurality of memory bits corresponding to an address;

wherein the method may comprise:

receiving a read command and a read address;

reading a state of a storage bit of the read address of the first memory array;

According to an embodiment of the fifth aspect of the invention, the method may comprise:

receiving a write address and a write command including write data; and

writing the same write data to the storage bits of the write address of the first memory array and the storage bits of the write address of the second memory array.

In an embodiment of the fifth aspect of the invention, since the first memory array and the second memory array will receive the same access address, each access address of the memory corresponds to one stored bit of the first memory array and one stored bit of the second memory array, the stored bits referring to the one or more memory cells to which the access address of the memory array corresponds. In other words, the physical address of one or more memory cells contained in the storage bit corresponding to the access address can be obtained according to the access address of the memory array.

According to an embodiment of the fifth aspect of the invention, the non-volatile memory may further comprise a row decoder, a first column decoder and a second column decoder, wherein the method may comprise:

resolving a row address and a column address according to the received address, transmitting the row address to the row decoder, and transmitting the column address to the first column decoder and the second column decoder;

in response to a received row address, the row decoder selects a row of the first memory array and a row of the second memory array to be accessed;

in response to a received column address, the first column decoder selects a column in the first memory array to be accessed; and

in response to the received column address, the second column decoder selects a column in the second memory array to be accessed.

According to one embodiment of the fifth aspect of the present invention, each of the plurality of memory bits comprises one or more memory cells.

According to an embodiment of the fifth aspect of the invention, each of the one or more memory cells may be selected from one of: a flash memory cell, a phase change random access memory cell, a resistive random access memory cell, a programmable metallization cell, a conductive bridging random access memory cell, a ferroelectric random access memory cell, a magnetoresistive random access memory cell, and a spin transfer torque random access memory cell.

Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Figure 5 illustrates a schematic diagram of a memory structure according to one example of an embodiment of the invention. As shown in FIG. 5, the memory 500 includes two

main memory arrays

510 and 520, two

reference arrays

530 and 540, a row decoder 550, and two

column decoder modules

560 and 570. Each main array includes x rows and y columns of RRAM cells containing variable resistors and transistors, and each reference array includes x rows and 1 column of RRAM cells. On each row, the gates of the transistors of the RRAM cells of the main array and the reference array are both coupled to a word line WL; on each column, the anode of the variable resistance of the RRAM cell is coupled to a bit line BL and the drain of the transistor is coupled to a source line SL. The row decoder 550 performs selection and driving operations of the word line WL, for example, the word line WL receives a high potential to turn on the transistor, according to a row address. The

column decoder modules

560 and 570 select the bit line BL and the source line SL, respectively, according to the column address, and output currents on the selected source line SL (i.e., the current Icell1 for the selected memory cell of the main array 510 and the current Icell2 for the selected memory cell of the main array 520, respectively) during the read phase.

Memory 500 also includes two

current buffers

532 and 542, two

current sense amplifiers

562 and 572, and an and gate 580. The

current buffers

532 and 542 apply an appropriate read voltage through the bit line BL and receive the reference currents Iref1 and Iref2 fed back to the source line SL, respectively. The negative input of the current sense amplifier 562 is connected to the output of the current buffer 532, and the positive input is connected to the output of the column decoder module 560, and outputs a digital signal state DQ 1; the negative input of the current sense amplifier 572 is connected to the output of the current buffer 542, and the positive input is connected to the output of the column decoder block 570, and outputs the digital signal state DQ 2. The input of the and gate unit 580 is connected to the outputs of the

current sense amplifiers

562 and 572, thereby performing an and operation on the digital signal states DQ1 and DQ2, and outputting the obtained result to the total data output terminal DQ. As can be seen from the exemplary arrangement in fig. 5, the main array, the reference array, the current buffer, the column decoder module, and the current sense amplifier in pairs are symmetrically arranged, which makes the consistency of the line length, the actual temperature distribution, and the like stronger, and thus the consistency of the stored data stronger.

It will be appreciated by those skilled in the art that the illustration of figure 5 is merely one example of an embodiment of the invention, however other variations of this embodiment may exist. In another embodiment of the invention, the two reference arrays in fig. 5 may be replaced by one reference array, both main arrays having the output of the reference array as the reference current, and the cathodes of both sense amplifiers receiving the reference current. To achieve symmetry, the reference array may be disposed between the two main arrays.

In another embodiment of the present invention, the bit lines BL may be arranged not parallel to the source lines but parallel to the word lines WL, and the row decoder 550 performs selection and voltage application operations of the bit lines BL, in which the bit lines BL and the word lines WL of the same row are selected in pairs.

Figure 6A illustrates a schematic diagram of a memory cell structure storing bits in accordance with one embodiment of the invention. In this embodiment, one memory cell in FIG. 5 is replaced by two

memory cells

610 and 620 of the same row, without the need for a reference array. Specifically, in the write phase, if a "1" is to be written to a memory bit, then memory cell 610 is written to a "1" and memory cell 620 is written to a "0", and similarly for a memory bit a "0". In the read phase,

memory cells

610 and 620 are read outState, where the state of memory cell 620 is taken as the logical reference for memory cell 610. That is, the column decoder block selects two column outputs to the current sense amplifier for comparison. FIG. 6B illustrates a schematic diagram of distribution probabilities of read currents for one embodiment of the memory cell structure of FIG. 6A. As can be seen from FIG. 6B, the case of the reference current Iref using the reference array shown in FIG. 4A (where Δ_H＝Δ_L＝(I_L-I_H) /2) in comparison, in the implementation of FIG. 6A, the read margin of the memory cell is increased by a factor of two, Δ_H＝Δ_L＝I_L-I_H. Such an arrangement further improves the reliability of the data.

In another embodiment of the present invention, one memory cell in FIG. 5 is replaced by two memory cells of the same column. In the write phase, the two memory cells write the same write data; in the reading phase, the current flowing out of the source line SL of the two memory cells is the sum of the currents flowing through the two memory cells by selecting the word lines WL1 and WL2 of the two rows of the two memory cells. Such a configuration proportionally increases the read margin, thereby further improving the reliability of the data.

FIG. 7 illustrates a flow diagram of a method of reading from and writing to non-volatile memory according to one embodiment of the invention. In using the non-volatile memory of the present invention, data to be stored is generally stored in the memory, and specifically, the memory receives a write address and a write command containing the write data (step 702), and then determines a corresponding storage bit according to the write address and writes the same write data to a memory cell coupled to the storage bit (step 704). When the stored data needs to be used, a read command and a read address are sent to the memory. The memory receives a read command and a read address (step 706), then determines the corresponding memory bit from the read address, and reads the state of the coupled memory cell in the memory bit (step 708). Finally, an and operation is performed on the read state to obtain the data stored in the read address (step 710).

FIG. 8 illustrates a flow diagram of a method of reading and writing to the memory of FIG. 5, according to one embodiment of the invention. First, the memory 500 receives a write address and a write command containing write data (step 802), the write address is supplied to the row decoder 550, the

column decoders

560 and 570, and the write data is supplied to the

column decoders

560 and 570. The row decoder 550 selects and drives the word line WL according to a row address of a write address, and the

column decoder modules

560 and 570 select the bit line BL and the source line SL according to a column address of the write address and drive the selected bit line BL and the source line SL according to write data, thereby writing the write data to all the memory cells corresponding to the selected word line WL, bit line BL, and source line SL (step 804). When the stored data needs to be used, memory 500 receives a read command and a read address (step 806), which is provided to row decoder 550,

column decoders

560 and 570. The row decoder 550 selects and drives the word line WL according to a row address of a read address, and the

column decoder modules

560 and 570 select the bit line BL and the source line SL according to a column address of the read address.

Column decoder modules

560 and 570 read out the current Icell1 of the selected memory cell of the main array 510 and the current Icell2 of the selected memory cell of the main array 520, respectively. At the same time, the

current buffers

532 and 542 read the reference currents Iref1 and Iref2 fed back on the source line SL of the memory cells selected by the word line WL in the

reference arrays

530 and 540, respectively. The current sense amplifier 562 compares the currents Icell1 and Iref1 to obtain the state DQ1 for the memory bit of the read address in the main array 510 (step 808), and the current sense amplifier 572 compares the currents Icell2 and Iref2 to obtain the state DQ2 for the memory bit of the read address in the main array 520 (step 810). Finally, and gate unit 580 performs an and operation on state DQ1 and state DQ2, thereby obtaining the data stored in the read address for output (step 812).

FIG. 9 illustrates a block diagram of a storage system, according to an example of an embodiment of the invention. As shown in fig. 9, the memory system 1000 may include a nonvolatile memory device 1100 and a controller 1200. The nonvolatile memory device 1100 may include a memory cell array including a plurality of nonvolatile memory cells and peripheral circuits for performing read/write operations with respect to the memory cell array. The controller 1200 generates a command/address (CMD/ADD) for controlling the nonvolatile memory device 1100 and supplies write DATA to the nonvolatile memory device 1100 or receives read DATA from the nonvolatile memory device 1100.

The controller 1200 may include a host Interface (IF) 1210 for connecting with a host and a memory IF1230 for connecting with the nonvolatile memory device 1100. A control logic unit 1220 for controlling the overall operation of the controller 1200 may also be included in the controller 1200. For example, the control logic unit 1220 supplies various control signals for read/write operations with respect to the nonvolatile memory device 1100 through the memory IF1230 according to a command input from the host. The RAM may be provided inside or outside the control logic unit 1220 so that write data may be temporarily stored in the RAM in a data write operation or read data may be temporarily stored in the RAM in a data read operation.

Names of components disclosed herein represent examples that can be applied to the inventive concept, and the nonvolatile memory device 1100 and the controller 1200 can be implemented using a separate semiconductor chip or a separate semiconductor package. The nonvolatile memory device 1100 and the controller 1200 may be integrated in a single chip or a single semiconductor package, and in this case, the nonvolatile memory device 1100 itself may be referred to as a memory system including the memory device and the controller. The memory system 1000 including the nonvolatile memory device 1100 and the controller 1200 may be implemented using a memory Card (e.g., a Secure Digital (SD) Card, a multimedia Card (MMC), or the like), a memory stick, a USB flash Disk, or a Solid State Disk (Solid State Disk).

In one or more embodiments, systems and/or modules and/or units and/or circuits and/or blocks may be provided in whole or in part in hardware and/or firmware, including but not limited to: one or more Application Specific Integrated Circuits (ASICs), digital signal processors, discrete circuitry, logic gates, standard integrated circuits, state machines, look-up tables, controllers (e.g., by executing appropriate instructions and including microcontrollers and/or embedded controllers), Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and the like, as well as various combinations thereof. In particular, in one or more embodiments, the controller, nonvolatile memory, sense amplifiers, column decoder modules, current buffers, row decoders, and modules, etc. may be implemented, in whole or in part, as so-called Application Specific Integrated Circuits (ASICs), i.e., Integrated Circuits (ICs) tailored to their particular use. Furthermore, in one or more embodiments, methods according to the present invention may be performed using software that may have been downloaded and/or stored in a corresponding memory, e.g., volatile memory (such as RAM, DRAM, SRAM, etc.) or non-volatile memory (such as CD-ROM, flash memory devices, etc.). Alternatively, the device may be implemented in whole or in part with programmable logic, e.g., as a Field Programmable Gate Array (FPGA). For example, the circuit may be implemented in CMOS, for example using a hardware description language (such as Verilog, VHDL, etc.).

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference signs or labels in the claims should not be construed as limiting the scope.

Memory cell1

Memory cell2

Storing bits

1. A non-volatile memory, comprising a plurality of memory cells and an and module, the non-volatile memory configured to:

2. The non-volatile memory as claimed in claim 1, wherein the plurality of memory cells are divided into a plurality of storage bits, and each storage bit of the plurality of storage bits comprises at least two memory cells coupled.

3. The non-volatile memory as claimed in claim 1 or 2, wherein the non-volatile memory is configured such that at least two memory cells coupled in respective memory bits are used to store the same write data.

4. The non-volatile memory as claimed in any one of claims 1 or 3, wherein the plurality of memory cells are divided into a plurality of storage bits, each storage bit of the plurality of storage bits comprises two memory cells coupled, each memory cell is uniquely addressed by a combination of a word line and a bit line, and the two memory cells coupled in each storage bit are addressed by a single word line and a pair of bit lines.

5. The non-volatile memory as claimed in any one of claims 1 or 3, wherein the plurality of memory cells are divided into a plurality of storage bits, each storage bit of the plurality of storage bits comprises two memory cells coupled, each memory cell is uniquely addressed by a combination of a word line and a bit line, and the two memory cells coupled in each storage bit are addressed by a pair of word lines and a single bit line.

6. The non-volatile memory as claimed in any one of claims 1 to 5, wherein each of the plurality of memory cells is selected from one of: a flash memory cell, a phase change random access memory cell, a resistive random access memory cell, a programmable metallization cell, a conductive bridging random access memory cell, a ferroelectric random access memory cell, a magnetoresistive random access memory cell, and a spin transfer torque random access memory cell.

7. A non-volatile memory, wherein the non-volatile memory comprises: a first memory array and a second memory array, each of the first memory array and the second memory array comprising a plurality of stored bits, each of the plurality of stored bits corresponding to an access address of the memory array;

8. A non-volatile memory system comprising the non-volatile memory according to any one of claims 1 to 7.

9. A method of reading from and writing to a non-volatile memory, wherein the non-volatile memory comprises a plurality of memory cells, wherein the method comprises:

receiving a read command and a read address;

10. A method of reading and writing to a non-volatile memory, the non-volatile memory comprising a first memory array and a second memory array, each of the first memory array and the second memory array comprising a plurality of stored bits, each of the plurality of stored bits corresponding to an address;

wherein the method comprises:

receiving a read command and a read address;

reading a state of a storage bit of the read address of the first memory array;