CN111739935A - Inorganic synapse transistor structure and method of fabrication - Google Patents

Inorganic synapse transistor structure and method of fabrication Download PDF

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CN111739935A
CN111739935A CN202010251422.1A CN202010251422A CN111739935A CN 111739935 A CN111739935 A CN 111739935A CN 202010251422 A CN202010251422 A CN 202010251422A CN 111739935 A CN111739935 A CN 111739935A
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layer
epitaxial
inorganic
gate dielectric
dielectric layer
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钟高阔
李江宇
訾孟飞
唐铭锴
黄明强
任传来
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Shenzhen Institute of Advanced Technology of CAS
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Shenzhen Institute of Advanced Technology of CAS
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Abstract

The invention relates to an inorganic synapse transistor structure and a manufacturing method, wherein the structure comprises: a flexible substrate; a buffer layer formed on the substrate; a bottom gate electrode formed on the buffer layer; an epitaxial gate dielectric layer formed on the bottom gate electrode; a channel layer formed on the epitaxial gate dielectric layer; and a source electrode and a drain electrode provided on the channel layer. The synapse transistor prepared by the invention effectively overcomes the defects that the synapse transistor adopting ionic liquid or solid electrolyte as a gate medium is difficult to realize miniaturization and integration, and the device linearity and symmetry are relatively poor and cannot resist high temperature. The synapse transistor prepared by the method has flexibility, bending resistance and high temperature resistance, can keep the performance basically unchanged under the bending condition or at 100 ℃, and the energy consumption of each device in the learning process is only 10-30pJ, which is beneficial to the practical application of the synapse transistor in the field of high-precision artificial nerve morphology calculation.

Description

Inorganic synapse transistor structure and method of fabrication
Technical Field
The invention relates to the technical field of synapse devices for simulating biological synapse forms and manufacturing thereof, in particular to an inorganic synapse transistor structure and a manufacturing method thereof.
Background
With the rapid development of artificial intelligence, the demand for various intelligent tasks has increased explosively worldwide from real-time big data analysis, mechanical automation control to visual and auditory recognition. Currently, computer processing based mainly on von neumann architecture requires huge energy consumption and complex algorithms, and it is difficult to break through the related bottleneck of data transmission between memory and central processing unit (von neumann bottleneck). And the nerve morphology calculation simulates the human brain to process and store data simultaneously, so that the bottleneck of von Neumann is overcome, and extremely high operation efficiency and extremely low operation power consumption can be realized. The human brain perceives, learns, and memories through 1012 neurons and 1015 synapses. In order to realize neuromorphic computation, synaptic devices simulating biological synapse morphology and function are of particular importance and are also receiving high attention.
In order to simulate the synaptic function and apply it to high-efficiency and high-precision neuromorphic computation, the synaptic device needs rich synaptic plasticity (synaptic plasticity), good linearity and symmetry. Short-term synaptic plasticity (STP) and long-term synaptic plasticity (LTP) are the most important synaptic plasticity. At present, nonvolatile memories, memristors, phase change memories and the like based on ion migration are widely applied to artificial synapse simulation. At present, the most researched devices are double-end devices, and because the devices have the defects of complex bionic function and ultralow power consumption, the devices with three ends are more and more emphasized. The idea that one transistor simulates a synaptic behavior becomes realisticIn some studies, it has been proposed to use MoO3Graphene and WO3、WSe2Materials are used as a channel to prepare a three-terminal synaptic transistor, however, the gate dielectric of the transistor still adopts ionic liquid or solid electrolyte, the devices are difficult to realize miniaturization and integration, and meanwhile, the linearity and symmetry of the devices are relatively poor, so that the high-precision artificial nerve shape calculation is not facilitated. At present, inorganic artificial synapses with flexibility and wearability are rarely developed, and high temperature tolerance cannot be achieved.
The invention patent application publication number CN108550627A discloses a flexible epitaxial ferroelectric gate thin film transistor and a preparation method thereof, wherein the transistor comprises: a mica flexible substrate; a buffer layer formed on the substrate; a bottom gate electrode formed on the buffer layer; an epitaxial ferroelectric thin film layer formed on the bottom gate electrode; a channel layer formed on the epitaxial ferroelectric thin film layer; a source electrode formed on the channel layer; and a drain electrode formed on the channel layer and separated from the source electrode. This patent application discloses SrRuO as a perovskite oxide having metallic conductivity3The epitaxial thin film is used as a bottom gate electrode, the perovskite oxide epitaxial ferroelectric thin film is used as a gate dielectric layer, the mechanical bending characteristic is very good, the bending radius of 2mm and repeated bending for 1000 times can be borne, and the electrical performance of the ferroelectric gate thin film transistor is kept basically unchanged; the reading and writing speed is high; the high temperature resistance is excellent, and the electrical properties of the alloy are not obviously changed after annealing at 400 ℃. The grid dielectric layer adopts single-layer structure Pb (Zr)0.52Ti0.48)O3The ferroelectric film and the channel layer adopt ZnO films. However, the lattice matching of the upper gate dielectric layer and other layers in the manufacturing process affects the resistance of leakage current, energy consumption is high in the learning process of current simulation synapses, and simulation identification precision of synapse performance needs to be improved under the conditions of bending and high temperature.
The invention patent application publication number CN110416312A discloses a low-power-consumption neurosynaptic thin film transistor and a preparation method thereof, wherein the structure of the transistor sequentially comprises the following components from bottom to top: a back gate electrode, a gate dielectric layer, a conductive channel and a source-drain electrode, wherein the source-drain electrode is arranged on the upper surface of the gate dielectric layer, and the conductive channel is positioned on the upper surface of the gate dielectric layerAnd forming a channel on the upper surface and two sides of the source-drain electrode. The patent antecedent has ultralow power consumption of a normal focus level; the adjustable memory time from milliseconds to thousands of seconds can be realized at different preparation temperatures of the dielectric layer; meanwhile, the use of all-inorganic materials greatly improves the stability of the device; the flexibility and synaptic performance of the low power neurosynaptic thin film transistor can be used for flexible electronics and large-scale neuromorphic circuitry. Wherein, the back gate electrode is selected from a low-resistance heavily-doped p-type silicon substrate with resistivity<0.005 omega-cm, and gate dielectric layer made of Al2O3、SiO2、ZrO2、HfO2TiO2 or La2O3One or more of the materials can be combined at will, and the conductive channel adopts IGZO, ITO and In2O3、ZnO、SnO2Or Ga2O3One or any combination of several of the materials. Because the lattice matching of the gate dielectric layer and other adjacent layers influences the epitaxial growth of the thin film, the gate dielectric layer is formed by the atomic layer deposition technology, different devices are required to be used in the manufacturing process, the flexible structure of the transistor is influenced, and meanwhile, the simulation identification precision of the synapse performance under the conditions of bending and high temperature is not facilitated.
Disclosure of Invention
The main purpose of the present invention is to provide an inorganic synapse transistor structure, which has the characteristics of good linearity, large working temperature span, and realization of better synapse performance simulation identification accuracy under the conditions of bending and higher temperature, so as to solve the technical problem of reduced synapse performance simulation identification accuracy of the conventional synapse transistor under the conditions of multiple bending or/and higher temperature.
Another objective of the present invention is to provide a method for manufacturing an inorganic synapse transistor structure, which can manufacture a synapse transistor having a high synapse performance under multiple bending or/and high temperature conditions with a high simulation recognition accuracy.
The third objective of the present invention is to provide an inorganic synapse transistor structure, which can realize that one transistor or device can simulate a synapse behavior, thereby facilitating the miniaturization and integration of a chip, and having the advantages of flexibility, wearability, and high temperature tolerance.
The main purpose of the invention is realized by the following technical scheme:
an inorganic synapse transistor structure is provided, comprising:
a mica flexible substrate;
the buffer layer is formed on the mica flexible substrate;
a bottom gate electrode layer formed on the buffer layer, the bottom gate electrode layer being SrRuO epitaxially grown based on the buffer layer3An epitaxial thin film;
the epitaxial gate dielectric layer is formed on the bottom gate electrode layer, the epitaxial gate dielectric layer is of an ABA sandwich structure which is based on the bottom gate electrode layer and has ferroelectricity through epitaxial growth, constituent elements of two A layers of the ABA sandwich structure comprise Sr and Ti, constituent elements of a B layer of the ABA sandwich structure comprise Ti, and the first A layer and the second A layer are substantially the same;
the channel layer is formed on the epitaxial gate dielectric layer and is an amorphous epitaxial thin film epitaxially grown on the second A layer based on the epitaxial gate dielectric layer;
and a source electrode and a drain electrode disposed on the channel layer.
By adopting the first basic technical scheme, considering that the inorganic synapse transistor structure integrally forms the flexible performance, the buffer layer, the bottom gate electrode layer, the epitaxial gate dielectric layer and the channel layer have the same simulation recognition precision for synapse performance under the conditions of flat state to multiple bending and high temperature, the buffer layer, the bottom gate electrode layer, the epitaxial gate dielectric layer and the channel layer are implemented based on the epitaxial growth of the front layer, the amorphous channel layer is selected, simultaneously considering that the inorganic synapse transistor structure integrally forms, the buffer layer, the bottom gate electrode layer, the epitaxial gate dielectric layer and the channel layer have the same simulation recognition precision for synapse performance under the conditions of flat state to multiple bending and high temperature, the ABA sandwich structure with ferroelectricity is further used as the epitaxial gate dielectric layer, the leakage current resistance and the epitaxial growth operability of the gate dielectric layer are improved, more specifically, the constituent elements of two A layers of the ABA sandwich, the first A layer and the second A layer are substantially the same, so that the ABA sandwich structure provides a ferroelectric B layer which can be smoothly epitaxially grown, and epitaxial growth of a channel layer of a rear layer is facilitated. Tests show that the nerve morphology calculation simulation of the inorganic synapse transistor shows the recognition precision higher than 80% when the bending radius is 4 mm, and also shows the recognition precision higher than 80% when the bending times reach 100 or 400, and the recognition precision performance can be kept unchanged under the bending process or at 100 ℃.
The present invention in a preferred example may be further configured to: the inorganic synapse transistor has the overall performance of low power consumption, high temperature resistance and flexibility; the nerve morphology calculation simulation of the inorganic synapse transistor shows a recognition accuracy higher than 80% when the bending radius is 4 mm, and also shows a recognition accuracy higher than 80% when the bending times reach 100 times or 400 times, the recognition accuracy performance can be kept unchanged under the bending process or at 100 ℃, and the energy consumption of each equipment unit of the inorganic synapse transistor in the learning process is 10-30 pJ.
By adopting the preferable technical scheme, the performance verification that the inorganic synapse transistor has low power consumption, high temperature resistance and flexibility is utilized, so that a semiconductor transistor or device can simulate a synapse behavior, the synapse behavior can be conveniently implemented in the miniaturization and integration process of a semiconductor chip by the synapse device, and meanwhile, the synapse transistor can be miniaturized and applied to flexible wearable occasions.
The present invention in a preferred example may be further configured to: the ABA sandwich structure is SrTiO3/PbZrTiO3/SrTiO3In which the PbZrTiO of the B layer3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films.
By adopting the preferred technical scheme, the lead zirconate titanate with excellent ferroelectric property is used as a basic core of a gate dielectric layer of the inorganic synaptic transistor, the lead zirconate titanate which is a material has good fatigue resistance, small coercive field and stable ferroelectric property, an ABA sandwich structure which is adaptive to epitaxial growth of other adjacent layers of the inorganic synaptic transistor is developed based on the basic core research of the lead zirconate titanate, the leakage current of the lead zirconate titanate is effectively reduced, and the lead zirconate titanate is more optimally fused in the framework of the inorganic synaptic transistor. In addition, the molar ratio of Ti to Zr can be further improved, for example, Ti: Zr ≧ (0.48 ÷ 0.52), i.e., the ratio of lead zirconate titanate in the gate dielectric layer can allow a wider range of more flexible changes, such as adjustment of ferroelectricity, without damaging the ability of the gate dielectric layer to be epitaxially grown on the bottom gate electrode layer or adversely affecting the curvature.
The present invention in a preferred example may be further configured to: the composition of the amorphous epitaxial thin film is n-type IGZO (indium gallium zinc oxide); the buffer layer is made of CoFe2O4(cobalt ferrite), the composition material of the source electrode and the drain electrode is selected from one or more of titanium, palladium, nickel, chromium, platinum and gold, and is preferably gold.
By adopting the preferred technical scheme, the epitaxial formation of the channel layer and the buffer layer in the synapse device in the semiconductor chip manufacturing process is realized by utilizing the material selection of the channel layer, the buffer layer and the source and drain electrodes.
The present invention in a preferred example may be further configured to: the thicknesses of the buffer layer and the two A layers of the ABA sandwich structure are controlled to be smaller than those of the bottom gate electrode layer and the channel layer, the B layer of the ABA sandwich structure is used as a main body layer of the epitaxial gate dielectric layer, and the thickness of the B layer accounts for more than 70% of the overall thickness of the epitaxial gate dielectric layer.
By adopting the above preferred technical scheme, the respective upper limits of the thicknesses of the buffer layer and the a layer can be controlled without affecting the ferroelectricity and epitaxial growth of the B layer by utilizing the specific control of the respective thicknesses of the buffer layer and the two a layers of the ABA sandwich structure and the minimum maintenance of the thickness of the B layer in the ABA sandwich structure.
The present invention in a preferred example may be further configured to: the thickness of the buffer layer or the individual thickness of the two A layers of the ABA sandwich structure is 5-20 nm, preferably 5-10 nm, the thickness of the bottom gate electrode layer is 10-40 nm, preferably 15-30 nm, and the thickness of the channel layer is 30-60 nm; the respective thicknesses of the source electrode and the drain electrode are between 60 and 80 nm; the thickness of the gate dielectric layer is 120-180 nm; the thickness of the mica flexible substrate is less than or equal to 30 mu m.
By adopting the preferred technical scheme, the thickness range of each layer is defined from thin to thick, the thickness of the layer used for isolation, buffering and excessive epitaxy is minimum, the thicknesses of the electrode layer, the channel layer and the source and drain electrodes are moderate, the thickness of the gate dielectric layer with ferroelectricity between the electrode layer and the channel layer is only second to that of the mica flexible substrate, the thickness of each layer is properly configured, the whole thickness achieves ideal thinning adjustment, the functions of each layer are not damaged, and the repeated bending use of the inorganic synapse transistor structure is facilitated.
The main purpose of the invention is realized by the following technical scheme:
a method for manufacturing an inorganic synapse transistor structure according to any of the above aspects is provided, comprising:
fixing a mica sheet on an operation table, and reducing the thickness of the mica sheet to be less than or equal to 30 μm to form the mica flexible substrate;
depositing CoFe on the mica flexible substrate2O4A thin film to obtain the buffer layer;
carrying out epitaxial growth on the buffer layer to obtain SrRuO3A thin film to obtain the bottom gate electrode layer;
epitaxially growing the ferroelectric ABA sandwich structure on the bottom gate electrode layer to obtain the epitaxial gate dielectric layer;
epitaxially growing an IGZO thin film on the epitaxial gate dielectric layer to obtain the channel layer, and annealing;
sputtering a metal layer on the channel layer, and forming the source electrode and the drain electrode from the metal layer.
By adopting the second basic technical scheme, the inorganic synapse transistor structure is prepared by utilizing specific layer-by-layer epitaxial growth, and the obtained product can resist bending and is not layered.
The present invention in a preferred example may be further configured to: the mica sheet is a smooth and crack-free natural mica sheet, the mica sheet is pasted on an operation table through double faced adhesive tape, and mica is peeled off layer by layer through a pointed forceps until the thickness of the mica sheet is smaller than 30 mu m.
The present invention in a preferred example may be further configured to: formation of CoFe on deposition2O4The film is deposited by using pulsed laser with the parameters that the deposition chamber is vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 500-600 ℃; the deposition oxygen pressure is 30-50 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
in the growth of SrRuO3The film is deposited by pulse laser with the parameters of the reaction chamber being vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 550-620 ℃; the deposition oxygen pressure is 50-80 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
pulsed laser deposition is used in the process of growing the ABA sandwich structure with ferroelectricity, and the parameters are that the reaction chamber is vacuumized to be less than or equal to 1 × 10-6Pa; the deposition temperature is 500-600 ℃; the oxygen pressure of the deposit is 100-200 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
the pulsed laser deposition is used in the process of growing the IGZO film, and the parameters are that the reaction chamber is vacuumized to be less than or equal to 1 × 10-6Pa; the deposition temperature is 300-400 ℃; the deposition oxygen pressure is 1-10 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min.
By adopting the preferable technical scheme, parameters of epitaxial growth of each layer, including vacuum degree, temperature, oxygen pressure, laser energy, laser pulse frequency and deposition rate, can be further researched and confirmed by using pulsed laser deposition.
The third objective of the present invention is to provide an inorganic synapse transistor structure, comprising: a flexible substrate; a bottom gate electrode formed on the substrate; an epitaxial gate dielectric layer formed on the bottom gate electrode; a channel layer formed on the epitaxial gate dielectric layer; a source electrode and a drain electrode formed on the channel layer; the channel layer is made of n-type semiconductor materials, and the epitaxial gate dielectric layer has ferroelectric properties; when the bending radius of the inorganic synaptic transistor is 4 mm, the epitaxial gate dielectric layer and the channel layer are not broken continuously, the neural morphology calculation simulation of the inorganic synaptic transistor shows the identification precision higher than 80%, and when the bending times reach 100 or 400 times, the neural morphology calculation simulation of the inorganic synaptic transistor also shows the identification precision higher than 80%;
preferably, the epitaxial gate dielectric layer is SrTiO3/PbZrTiO3/SrTiO3In which PbZrTiO is present3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films;
preferably, the bottom gate electrode layer specifically includes a SrRuO3 epitaxial film, the channel layer specifically includes an n-type IGZO epitaxial film, and the source electrode and the drain electrode each specifically include an Au metal electrode;
preferably, the thickness of the bottom gate electrode layer is 10-30 nm; the thickness of the epitaxial gate dielectric layer is 120-180 nm; the thickness of the channel layer is 30-60 nm.
In summary, the invention includes at least one of the following beneficial technical effects:
1. the inorganic synapse transistor structure prepared by the invention has a framework of a flexible ferroelectric thin film transistor, can take a two-sided layer A such as SrTiO3 and a core layer B such as a perovskite oxide epitaxial ferroelectric thin film as a gate dielectric layer on the basis of taking a perovskite oxide SrRuO3 epitaxial thin film with metal conductivity as a bottom gate electrode, has a ferroelectric ABA sandwich structure, has a similar lattice structure and good lattice matching property in a third layer, can epitaxially grow a high-quality dielectric thin film on the bottom gate electrode layer, and is beneficial to the epitaxial growth of an amorphous channel layer;
2. the inorganic synapse transistor structure prepared by the invention has the characteristics of low power consumption, high temperature resistance and flexibility, can be flexibly bent, can bear bending radius of 4 mm and repeated bending for 400 times, and keeps the performance of the synapse transistor basically unchanged;
3. the inorganic synapse transistor structure which is low in power consumption, high-temperature resistant and bendable and prepared by the invention has excellent high-temperature resistance, and the electrical property of the inorganic synapse transistor structure is not obviously changed after annealing at 100 ℃;
4. the method effectively overcomes the defects that the synaptic transistor adopting the ionic liquid or the solid electrolyte as the gate medium is difficult to realize miniaturization and integration, and the linearity and the symmetry of the device are relatively poor and cannot resist high temperature, and is beneficial to the practical application in the field of high-precision artificial nerve shape calculation;
5. according to the synapse transistor and the manufacturing method thereof, the n-type semiconductor material can be further selected as the material of the synapse device or the channel layer of the synapse transistor, the ferroelectric material such as lead zirconate titanate is used as the main material of the gate dielectric layer, voltage is applied to the gate dielectric layer through the gate, the ferroelectric domain in the gate dielectric layer is subjected to polarization inversion, the change of the ferroelectric domain can change the conductance of the channel layer, the synapse behavior is simulated through the change of the conductance, the simulation of the synapse behavior of the transistor is realized, and the characteristics of low power consumption, easiness in miniaturization and integration are realized because the ferroelectric domain is easy to invert. Meanwhile, the synapse transistor has the effects of flexibility and large working temperature span.
Drawings
FIG. 1 is a schematic cross-sectional view of a synaptic transistor structure according to some embodiments of the invention;
FIG. 2 is a schematic diagram illustrating the operation of a synaptic transistor structure according to some embodiments of the present invention;
FIGS. 3A-3F are schematic component diagrams illustrating the main steps in a method of fabricating a synapse transistor structure in a preferred embodiment of the invention;
FIG. 4 illustrates a transfer curve of a synapse transistor structure in accordance with an embodiment of the invention;
FIG. 5 shows an output curve of a synapse transistor structure in accordance with an embodiment of the invention;
FIG. 6 illustrates a synaptic transistor structure continuously modulating the change in conductance through positive and negative spikes in accordance with an embodiment of the invention;
FIG. 7 illustrates a synaptic transistor structure that continuously modulates the change in conductance through positive and negative spikes at different temperatures in accordance with an embodiment of the invention;
FIG. 8 illustrates energy consumption of a synapse transistor structure in a learning process for one spike and one cycle in accordance with an embodiment of the invention;
FIG. 9 illustrates the recognition accuracy of synapse transistor structures fabricated in accordance with embodiments of the invention at different bend radii and different bend times;
FIG. 10 illustrates the recognition accuracy of synapse transistor structures fabricated in accordance with embodiments of the invention at different numbers of bends.
The reference numerals are 10, a mica flexible substrate, 11, a buffer layer, 20, a bottom gate electrode layer, 30, a gate dielectric layer, 40, a channel layer, 61, a source electrode, 62 and a drain electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art with the understanding of the inventive concept of the present invention are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In order to facilitate understanding of the technical solution of the present invention, the structure and the manufacturing method of the inorganic synapse transistor of the present invention are described in further detail below, but are not to be construed as the scope of the present invention. FIG. 1 is a schematic cross-sectional view of a synapse transistor structure in accordance with some embodiments of the present invention, FIG. 2 is a schematic operation diagram of a synapse transistor structure in accordance with some embodiments of the present invention, and FIGS. 3A-3F are schematic component diagrams illustrating various main steps of a method for fabricating a synapse transistor structure in accordance with a preferred embodiment of the present invention. The invention provides an inorganic synapse transistor structure with low power consumption, high temperature resistance and flexibility, which is a three-terminal device.
Referring to fig. 1 and fig. 2, a first embodiment of the invention provides an inorganic synapse transistor structure comprising:
a mica flexible substrate 10;
a buffer layer 11 formed on the mica flexible substrate 10;
a bottom gate electrode layer 20 formed on the buffer layer 11, the bottom gate electrode layer 20 being SrRuO epitaxially grown on the buffer layer 113An epitaxial thin film;
the epitaxial gate dielectric layer 30 is formed on the bottom gate electrode layer 20, the epitaxial gate dielectric layer 30 is an ABA sandwich structure which is based on the bottom gate electrode layer 20 and has ferroelectricity through epitaxial growth, wherein the constituent elements of two a layers of the ABA sandwich structure comprise Sr and Ti, the constituent element of a B layer comprises Ti, and the first a layer and the second a layer are substantially the same;
a channel layer 40 formed on the epitaxial gate dielectric layer 30, wherein the channel layer 40 is an amorphous epitaxial thin film epitaxially grown on the basis of the second a layer of the epitaxial gate dielectric layer 30;
and a source electrode 61 and a drain electrode 62 disposed on the channel layer 40.
In a specific application, a voltage signal may be applied to the source electrode 61 and the drain electrode 62, and a current signal in the channel layer 40 may be detected, so that the conductance of the channel layer 40 may be obtained.
The implementation principle of the embodiment is as follows: the buffer layer 11, the bottom gate electrode layer 20, the epitaxial gate dielectric layer 30 and the channel layer 40 are epitaxially grown based on a previous layer, the amorphous channel layer 40 is selected, the bendable durability of the inorganic synapse transistor structure is improved, the ABA sandwich structure with ferroelectricity is further used as the epitaxial gate dielectric layer 30, and the leakage current resistance and the epitaxial growth operability of the gate dielectric layer 30 are improved. The constituent elements of the two A layers of the ABA sandwich structure comprise Sr and Ti, the constituent element of the B layer comprises Ti, the first A layer and the second A layer are substantially the same, the epitaxial growth of the B layer which provides ferroelectricity for the ABA sandwich structure and the epitaxial growth of the channel layer 40 which is used as a rear layer are facilitated, and the simulation recognition precision of synapse performance is consistent under the conditions of flat shape to multiple bending and high temperature.
With respect to the mica flexible substrate 10, the thickness of the mica flexible substrate 10 may be 30 μm or less. The mica sheet is a smooth and crack-free natural mica sheet, the mica sheet is pasted on an operation table through double faced adhesive tape, and mica is peeled off layer by layer through a pointed forceps until the thickness of the mica sheet is smaller than 30 mu m. The mica flexible substrate 10 was used in the test with a thickness of 30 μm. Without limitation, the mica flexible substrate 10 may also be made of other substrate materials used in chip fabrication.
Regarding the buffer layer 11, as an intermediate transition layer of the mica flexible substrate 10 to the bottom gate electrode layer 20, the composition of the buffer layer 11 may specifically be CoFe2O4. The thickness of the buffer layer 11 is between 5 and 20nm, preferably between 5 and 10 nm. The buffer layer 11 was used in the test with a thickness of 10 nm. The buffer layer 11 may also be made of other intermediate materials that facilitate epitaxial growth of the bottom gate electrode layer 20 during the chip manufacturing process, or in some cases, the buffer layer 11 may be omitted.
As for the bottom gate electrode layer 20, CoFe-based2O4Epitaxially grown SrRuO3The electrode layer(s) has conductivity and can serve as a gate of a synaptic transistor. The thickness of the bottom gate electrode layer 20 is 10 to 40 nm, preferably 15 to 30 nm. The bottom gate electrode layer 20 was used in the test with a thickness of 40 nm. But not limited thereto, other conductive gate materials of the chip process may be used for the bottom gate electrode layer 20.
Regarding the epitaxial gate dielectric layer 30, the dielectric layer separating the bottom gate electrode layer 20 and the channel layer 40 may be designed as an ABA sandwich structure with ferroelectricity for synaptic transistor application. The ABA sandwich structure is SrTiO3/PbZrTiO3/SrTiO3In which the PbZrTiO of the B layer3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films. The thickness of the gate dielectric layer 30 is 120-180 nm. The respective thicknesses of the two A layers of the ABA sandwich structure are between 5 and 20nm, preferably between 5 and 10 nm. In the experiment, the composition of the material of the layer A is SrTiO3The thickness of the material is divided into three groups of 7 nm, 10 nm and 13 nm, and the material compositions of the B layer materials corresponding to the three groups are Pb (Zr) respectively0.1Ti0.9)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3And the thickness is 150 nm. But not limited thereto, the epitaxial gate dielectric layer 30 may also be made of other ferroelectric dielectric materials in the chip process. As proved by experiments, the thickness value of the A layer needs to be larger when the molar ratio of the titanium to the zirconium of the B layer is smaller under the same leakage current resistance in the ABA sandwich structure. The thickness of the layer A can be reduced by utilizing the improvement of the molar ratio of titanium to zirconium of the layer B.
Regarding the channel layer 40, which is used as a channel of a synaptic transistor, under the action of the electric field of the bottom gate electrode layer 20, the ferroelectric domain of the epitaxial gate dielectric layer 30 undergoes polarization reversal, and the change of the ferroelectric domain causes the conductance of the channel layer 40 to change, so that the conductance change can be used to simulate a synaptic behavior. In a specific application, the conductance may be used directly for the simulation of the synaptic behavior, or may be used indirectly for the simulation of the synaptic behavior, for example, the current in the channel layer 40 may be used for the simulation of the synaptic behavior. The thickness of the channel layer 40 is 30-60 nm; in the experiment, the material of the channel layer 40 is specifically an N-type semiconductor material IGZO, with a thickness of 60 nm. But not limited thereto, the channel layer 40 may also use other semiconductor materials of the chip manufacturing process that are capable of simulating the synaptic behavior.
The source electrode 61 and the drain electrode 62 are disposed on the channel layer 40 with a gap therebetween, and are in contact with the channel layer 40. The source electrode 61 and the drain electrode 62 are used to measure the conductance of the channel layer 40, which represents the change in the ferroelectric domain in the channel layer 40. The source electrode 61 and the drain electrode 62 are made of one or more materials selected from titanium, palladium, nickel, chromium, platinum and gold, preferably gold. The respective thicknesses of the source electrode 61 and the drain electrode 62 are between 60nm and 80 nm. In the test, the source electrode 61 and the drain electrode 62 may be gold electrodes, and the test thickness is 70 nm. However, the source electrode 61 and the drain electrode 62 may be made of other electrode materials in a chip manufacturing process.
In a preferred example, the respective thicknesses of the buffer layer 11 and the two a layers of the ABA sandwich structure are controlled to be smaller than the respective thicknesses of the bottom gate electrode layer 20 and the channel layer 40, the B layer of the ABA sandwich structure serves as a bulk layer of the epitaxial gate dielectric layer 30, and the thickness of the B layer accounts for more than 70% of the overall thickness of the epitaxial gate dielectric layer 30. Therefore, by specific control of the respective thicknesses of the buffer layer 11 and the two a layers of the ABA sandwich structure and minimum maintenance of the thickness of the B layer in the ABA sandwich structure, the respective upper limits of the thicknesses of the buffer layer 11 and the a layers are controlled without affecting the ferroelectricity and epitaxial growth of the B layer.
Regarding performance of inorganic synaptic transistors, the inorganic synaptic transistors have low power consumption, high temperature resistance, and flexible performance as a whole; the S1 of the inorganic synapse transistor is higher than 80% in the neural morphology calculation simulation when the bending times reach 100 or 400 times, the recognition accuracy performance can be kept unchanged under the bending process or at 100 ℃, and the energy consumption of each equipment unit of the inorganic synapse transistor in the learning process is 10-30 pJ. Therefore, the performance verification that the inorganic synapse transistor is low in power consumption, high-temperature resistant and bendable is utilized, one semiconductor transistor or device can simulate a synapse behavior, the synapse behavior can be conveniently implemented in miniaturization and integration processes of a semiconductor chip, and meanwhile, the synapse transistor or device can be miniaturized and applied to flexible wearable occasions.
In addition, FIG. 3A to FIG. 3F are schematic diagrams illustrating the main steps of the method for fabricating the synapse transistor structure in the preferred embodiment of the invention. A second embodiment of the present invention further provides a method for fabricating an inorganic synapse transistor structure, which may be used for fabricating an inorganic synapse transistor structure according to any of the above-mentioned aspects. The manufacturing method comprises the following steps:
referring to fig. 3A in a coordinated manner, fixing the mica sheet on the operation table, and reducing the thickness of the mica sheet to be less than or equal to 30 μm to form the mica flexible substrate 10;
with reference to FIG. 3B, CoFe is deposited on the mica flexible substrate 102O4A thin film to obtain said buffer layer 11; in one or more specific examples, CoFe is formed on deposition2O4The film is deposited by using pulsed laser with the parameters that the deposition chamber is vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 500-600 ℃; the deposition oxygen pressure is 30-50 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
with reference to fig. 3C, SrRuO is epitaxially grown on the buffer layer 113A thin film to obtain the bottom gate electrode layer 20; in one or more specific examples, SrRuO is grown3The film is deposited by pulse laser with the parameters of the reaction chamber being vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 550-620 ℃; the deposition oxygen pressure is 50-80 mtorr; the laser energy is 300-350 mJ; laser pulse frequencyThe rate is 10 Hz; the deposition rate is 1-5 nm/min;
referring to fig. 3D, the ABA sandwich structure with ferroelectricity is epitaxially grown on the bottom gate electrode layer 20 to obtain the epitaxial gate dielectric layer 30. in one or more specific examples, pulsed laser deposition is used during the growth of the ABA sandwich structure with ferroelectricity, and the parameters are that the reaction chamber is evacuated to 1 × 10 or less-6Pa; the deposition temperature is 500-600 ℃; the oxygen pressure of the deposit is 100-200 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
with reference to fig. 3E, an IGZO thin film is epitaxially grown on the epitaxial gate dielectric layer 30 to obtain the channel layer 40, and an annealing process is performed, in one or more specific examples, pulsed laser deposition is used during the IGZO thin film growth process, and the parameters are that the reaction chamber is evacuated to less than or equal to 1 × 10-6Pa; the deposition temperature is 300-400 ℃; the deposition oxygen pressure is 1-10 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
with reference to fig. 3F, sputtering a metal layer on the channel layer 40, and forming the source electrode 61 and the drain electrode 62 from the metal layer to obtain a synapse transistor structure; in one or more embodiments, pulsed laser deposition is used to further study and confirm the parameters of epitaxial growth of layers inside the fabricated synaptic transistor structure, including vacuum, temperature, oxygen pressure, laser energy, laser pulse frequency, and deposition rate.
The inorganic synapse transistor structure is prepared by the specific layer-by-layer epitaxial growth, and the obtained product can resist bending and is not layered.
Referring to fig. 2 again, after a voltage is applied to the bottom gate electrode layer 20, as a presynaptic stimulus, charges are induced on the lower surface of the channel layer 40 by electrostatic induction of the gate dielectric layer 30 and polarization reversal of the internal ferroelectric material, and then different charges are induced on the upper surface thereof, so that an electric dipole moment perpendicular to the channel layer 40 is formed, such that the conductance of the channel layer 40 changes, and the change in conductance, i.e., synaptic weight, is reflected by testing the magnitude of the current between the source electrode 61 and the drain electrode 62.
In a particular application, the gate voltage applied to the bottom gate electrode layer 20 is greater than the voltage corresponding to the coercive electric field of the ferroelectric material of the channel layer 40 to cause polarization reversal of the ferroelectric domains in the ferroelectric material of the channel layer 40, while the voltages applied to the source electrode 61 and the drain electrode 62 are less than the voltage corresponding to the coercive electric field of the ferroelectric material of the channel layer 40 to measure the value of current through the channel layer 40 to characterize changes in conductance in the channel layer 40. Referring to fig. 4, the transfer curve of the synaptic transistor, a constant voltage VDS = 0.5V is applied between the source electrode 61 and the drain electrode 62, the gate voltage VGS is changed from-5V to 5V, and the relationship between ISD and VGS is measured, as shown in fig. 5.
FIG. 6 illustrates the change in conductance of the synaptic transistor continuously modulated by the positive and negative spikes according to the present embodiment; at a positive spike, the conductance of the synaptic transistor exhibits a continuous and linear increase, which is considered a long-range enhancement. At the negative spike, the device conductance will gradually decrease, which is considered a long-range rejection.
FIG. 7 shows that the synapse transistor of the present embodiment continuously modulates the conductance through positive and negative spikes at different temperatures, and still maintains the long-range enhancement and long-range inhibition characteristics at 100 ℃.
FIG. 8 shows the energy consumption of a synapse transistor of an embodiment in a learning process for one spike and one cycle; the energy consumption of each peak of the burst transistor in the graph is as small as 0.26 fJ, and the energy consumption of each device in the learning process is about 10-30pJ, which is far less than the energy consumption of the RRAM and the FeFET.
FIGS. 9 and 10 show the recognition Accuracy (Accuracy) of the synapse transistor fabricated in accordance with the present embodiment under different bending radii and different bending times (cycles); as shown in fig. 9, the statistical curves L7 and L8, the neuromorphic computational simulation showed a recognition accuracy of more than 80% at the bending radii of 4 mm and 10 mm, and exhibited the same performance as the unbent statistical curve L6. The statistical curves L10 and L11 shown in fig. 10 also showed higher than 80% recognition accuracy at 100 and 400 bending times, and showed the same performance as the initial statistical curve L9. Preferably, as the initial recognition accuracy is higher (e.g., higher than 90%), the recognition accuracy at different bending radii and at different bending times can be maintained in a higher range, e.g., higher than 90%.
Referring to fig. 1, a third embodiment of the present invention provides an inorganic synapse transistor structure comprising: a flexible substrate 10; a bottom gate electrode layer 20 formed on the substrate 10; an epitaxial gate dielectric layer 30 formed on the bottom gate electrode layer 20; a channel layer 40 formed on the epitaxial gate dielectric layer 30; a source electrode 61 and a drain electrode 62 formed on the channel layer 40; the channel layer 40 is made of n-type semiconductor material, and the epitaxial gate dielectric layer 30 has ferroelectric properties; when the bending radius of the inorganic synaptic transistor is 4 mm, the epitaxial gate dielectric layer 30 and the channel layer 40 are not broken continuously, the nerve morphology calculation simulation of the inorganic synaptic transistor shows a recognition accuracy higher than 80%, when the bending times reach 100 times or 400 times, the nerve morphology calculation simulation of the inorganic synaptic transistor also shows a recognition accuracy higher than 80%, and the recognition accuracy performance can be kept unchanged in the bending process or at 100 ℃. Therefore, one transistor or device can simulate a synapse behavior, which is beneficial to miniaturization and integration of a chip, and has the advantages of flexibility, wearability and high temperature tolerance. A preferred example is to maintain a recognition accuracy of higher than 90%.
In a preferred example, the epitaxial gate dielectric layer 30 is SrTiO3/PbZrTiO3/SrTiO3In which PbZrTiO is present3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films.
In a preferred example, the bottom gate electrode layer 20 specifically includes SrRuO3An epitaxial thin film, wherein the channel layer 40 specifically comprises an n-type IGZO epitaxial thin film, the source electrode 61 and the drainThe electrodes 62 each specifically include an Au metal electrode.
In a preferred example, the thickness of the bottom gate electrode layer 20 is 10 to 30 nm; the thickness of the epitaxial gate dielectric layer 30 is 120-180 nm; the thickness of the channel layer 40 is 30 to 60 nm.
The embodiments of the present invention are merely preferred embodiments for easy understanding or implementing of the technical solutions of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes in structure, shape and principle of the present invention should be covered by the claims of the present invention.

Claims (10)

1. An inorganic synapse transistor structure, comprising:
a mica flexible substrate (10);
a buffer layer (11) formed on the mica flexible substrate (10);
a bottom gate electrode layer (20) formed on the buffer layer (11), the bottom gate electrode layer (20) being SrRuO epitaxially grown on the basis of the buffer layer (11)3An epitaxial thin film;
the epitaxial gate dielectric layer (30) is formed on the bottom gate electrode layer (20), the epitaxial gate dielectric layer (30) is in an ABA sandwich structure which is based on the bottom gate electrode layer (20) and has ferroelectricity through epitaxial growth, constituent elements of two A layers of the ABA sandwich structure comprise Sr and Ti, constituent elements of a B layer of the ABA sandwich structure comprise Ti, and the first A layer and the second A layer are substantially the same;
a channel layer (40) formed on the epitaxial gate dielectric layer (30), the channel layer (40) being an amorphous epitaxial thin film epitaxially grown based on a second A layer of the epitaxial gate dielectric layer (30);
a source electrode (61) and a drain electrode (62) disposed on the channel layer (40).
2. The inorganic synapse transistor structure of claim 1, wherein the inorganic synapse transistor has low power consumption, high temperature resistance, and flexibility as a whole; the nerve morphology calculation simulation of the inorganic synapse transistor shows a recognition accuracy higher than 80% when the bending radius is 4 mm, and also shows a recognition accuracy higher than 80% when the bending times reach 100 times or 400 times, the recognition accuracy performance can be kept unchanged under the bending process or at 100 ℃, and the energy consumption of each equipment unit of the inorganic synapse transistor in the learning process is 10-30 pJ.
3. The inorganic synapse transistor structure of claim 1, wherein the ABA sandwich structure is in particular SrTiO3/PbZrTiO3/SrTiO3In which the PbZrTiO of the B layer3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films.
4. The inorganic synapse transistor structure of claim 1, wherein the composition of the amorphous epitaxial thin film is IGZO of n-type; the buffer layer (11) is made of CoFe2O4(ii) a The source electrode (61) and the drain electrode (62) are made of one or more materials selected from titanium, palladium, nickel, chromium, platinum and gold.
5. The inorganic synapse transistor structure of any of claims 1-4, wherein the respective thicknesses of the buffer layer (11) and the A layers of the ABA sandwich structure are controlled to be smaller than the respective thicknesses of the bottom gate electrode layer (20) and the channel layer (40), the B layer of the ABA sandwich structure is used as the bulk layer of the epitaxial gate dielectric layer (30), and the thickness of the B layer accounts for more than 70% of the overall thickness of the epitaxial gate dielectric layer (30).
6. The inorganic synapse transistor structure of claim 5, wherein the buffer layer (11) or the respective thicknesses of the two A layers of the ABA sandwich structure is between 5-20 nm, preferably between 5-10 nm, the bottom gate electrode layer (20) is between 10-40 nm, preferably between 15-30 nm, the channel layer (40) is between 30-60 nm; the respective thicknesses of the source electrode and the drain electrode are between 60 and 80 nm; the thickness of the gate dielectric layer (30) is 120-180 nm; the mica flexible substrate (10) has a thickness of 30 [ mu ] m or less.
7. A method of fabricating the inorganic synapse transistor structure of any of claims 1-6, comprising:
fixing mica sheets on a console and reducing the thickness of the mica sheets to be less than or equal to 30 μm to form the mica flexible substrate (10);
depositing CoFe on the mica flexible substrate (10)2O4-a thin film to obtain said buffer layer (11);
carrying out epitaxial growth on the buffer layer (11) to obtain SrRuO3A thin film to obtain the bottom gate electrode layer (20);
epitaxially growing the ferroelectric ABA sandwich structure on the bottom gate electrode layer (20) to obtain the epitaxial gate dielectric layer (30);
epitaxially growing an IGZO thin film on the epitaxial gate dielectric layer (30) to obtain the channel layer (40), and annealing;
sputtering a metal layer on the channel layer (40), and forming the source electrode (61) and the drain electrode (62) from the metal layer.
8. The method according to claim 7, wherein the mica sheet is a smooth and crack-free natural mica sheet, the mica sheet is attached to a console with double-sided tape, and the mica is peeled off layer by layer with a pointed tweezers until the thickness of the mica sheet is less than 30 μm;
formation of CoFe on deposition2O4The film is deposited by using pulsed laser with the parameters that the deposition chamber is vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 500-600 ℃; oxygen pressure of 30-50 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
in the growth of SrRuO3The film is deposited by pulse laser with the parameters of the reaction chamber being vacuumized to less than or equal to 1 × 10-6Pa; the deposition temperature is 550-620 ℃; the deposition oxygen pressure is 50-80 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
pulsed laser deposition is used in the process of growing the ABA sandwich structure with ferroelectricity, and the parameters are that the reaction chamber is vacuumized to be less than or equal to 1 × 10-6Pa; the deposition temperature is 500-600 ℃; the oxygen pressure of the deposit is 100-200 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min;
the pulsed laser deposition is used in the process of growing the IGZO film, and the parameters are that the reaction chamber is vacuumized to be less than or equal to 1 × 10-6Pa; the deposition temperature is 300-400 ℃; the deposition oxygen pressure is 1-10 mtorr; the laser energy is 300-350 mJ; the laser pulse frequency is 10 Hz; the deposition rate is 1-5 nm/min.
9. An inorganic synapse transistor structure, comprising: a flexible substrate (10); a bottom gate electrode layer (20) formed over the substrate; an epitaxial gate dielectric layer (30) formed on the bottom gate electrode layer (20); a channel layer (40) formed on the epitaxial gate dielectric layer (30); providing a source electrode (61) and a drain electrode (62) formed on the channel layer (40), the channel layer (40) being constructed using an n-type semiconductor material, the epitaxial gate dielectric layer (30) having ferroelectric properties; when the bending radius of the inorganic synaptic transistor is 4 mm, the epitaxial gate dielectric layer (30) and the channel layer (40) are not broken continuously, the neural morphology calculation simulation of the inorganic synaptic transistor shows a recognition accuracy higher than 80%, when the bending times reach 100 or 400 times, the neural morphology calculation simulation of the inorganic synaptic transistor also shows a recognition accuracy higher than 80%, and the recognition accuracy performance can be kept unchanged in the bending process or at 100 ℃.
10. The inorganic synapse transistor structure of claim 9, wherein the epitaxial gate dielectric layer (30) is SrTiO3/PbZrTiO3/SrTiO3In which PbZrTiO is present3Is selected from Pb (Zr)0.1Ti0.9)O3、Pb(Zr0.2Ti0.8)O3、Pb(Zr0.3Ti0.7)O3And Pb (Zr)0.52Ti0.48)O3Any one or combination of the formed epitaxial films;
preferably, the bottom gate electrode layer (20) comprises in particular SrRuO3An epitaxial thin film, the channel layer (40) comprising in particular an IGZO epitaxial thin film of n-type, the source electrode (61) and the drain electrode (62) each comprising in particular an Au metal electrode;
preferably, the thickness of the bottom gate electrode layer (20) is 10-30 nm; the thickness of the epitaxial gate dielectric layer (30) is 120-180 nm; the thickness of the channel layer (40) is 30-60 nm.
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