CN111739927A - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor device Download PDFInfo
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- CN111739927A CN111739927A CN202010186965.XA CN202010186965A CN111739927A CN 111739927 A CN111739927 A CN 111739927A CN 202010186965 A CN202010186965 A CN 202010186965A CN 111739927 A CN111739927 A CN 111739927A
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- 238000000034 method Methods 0.000 claims abstract description 52
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
A semiconductor device and a method of manufacturing the semiconductor device are provided. The method comprises the following steps: providing a substrate comprising a first region and a second region; forming a first channel layer in the first region of the substrate; forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region; etching an upper surface of the second region of the substrate; forming a protective layer covering the first channel layer in the first region of the substrate and the second region of the substrate; removing the protective layer on the second region of the substrate; forming a gate insulating material layer on the protective layer and on the second region of the substrate; and removing the gate insulating material layer and the protective layer on the first region of the substrate.
Description
Cross Reference to Related Applications
The present application claims priority from korean patent application No.10-2019-0033293 filed at 25.3.2019 in the korean intellectual property office and korean patent application No.10-2019-0064342 filed at 31.5.2019 in the korean intellectual property office, the entire disclosures of which are incorporated herein by reference.
Technical Field
Example embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device.
Background
With the reduction in size, low-voltage semiconductor devices have been developed. However, the semiconductor device may include a booster circuit, or may itself have a power supply voltage of 12V when used in a vehicle. Accordingly, the semiconductor device may include a low voltage transistor and a high voltage transistor.
In a process of forming a low voltage transistor and a high voltage transistor in a semiconductor device, silicon germanium and silicon for forming a channel may be oxidized, or germanium may be precipitated.
Disclosure of Invention
According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: forming a first channel layer in a first region of a substrate, the substrate including the first region and a second region; forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region; etching an upper surface of the second region of the substrate; forming a protective layer covering the first channel layer in the first region of the substrate and covering the second region of the substrate; removing the protective layer on the second region of the substrate; forming a gate insulating material layer on the protective layer and on the second region of the substrate; and removing the gate insulating material layer and the protective layer on the first region of the substrate.
According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: forming a first channel layer in a first region of a substrate, the substrate including the first region and a second region, the first channel layer including silicon germanium; etching an upper surface of the second region of the substrate; forming a protective layer covering the first channel layer in the first region of the substrate and covering the second region of the substrate; removing the protective layer on the second region of the substrate; forming a second channel layer in the second region of the substrate; forming a layer of gate insulating material to cover the protective layer and to cover the second region of the substrate; and removing the gate insulating material layer and the protective layer on the first region of the substrate. The substrate may include a sequential stack of a first silicon layer, an insulating layer, and a second silicon layer. The first channel layer may be formed in the second silicon layer.
According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate comprising a first region, a second region, and a third region; an isolation region in the substrate, the isolation region electrically isolating respective portions of the first, second, and third regions from one another; a first channel layer located in the first region of the substrate; a first gate insulating layer on the first channel layer; a second gate insulating layer on the second region of the substrate; a third gate insulating layer on the third region of the substrate; a first source/drain region in the first channel layer; a second source/drain region in the second region of the substrate; a second channel layer located in the second region of the substrate and between the second source/drain regions; a third source/drain region in the third region of the substrate; and a third channel layer located in the third region of the substrate and between the third source/drain regions. The upper surface of the first channel layer may be distant from the bottom surface of the substrate with respect to both the upper surface of the second channel layer and the upper surface of the third channel layer.
Drawings
Fig. 1 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts.
Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 are views illustrating stages in a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.
Fig. 17 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts.
Fig. 18 and 19 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.
Fig. 20 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts.
Fig. 21, 22 and 23 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.
Fig. 24, 25 and 26 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.
Detailed Description
Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the application.
Fig. 1 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts.
Referring to fig. 1, the semiconductor device may include a substrate 100, a first channel layer 111, a second channel layer 112, a third channel layer 113, a first gate structure 120, a second gate structure 130, a third gate structure 140, a first source/drain region 125, a second source/drain region 135, a third source/drain region 145, an interlayer insulating layer 150, and an isolation region STI.
The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In some example embodiments, the substrate 100 may include a semiconductor material other than silicon, for example, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the inventive concept is not limited thereto. Hereinafter, it will be described that the substrate 100 is an SOI substrate.
The substrate 100 may include a first silicon layer 101, an insulating layer 102, and a second silicon layer 103. Insulating layer 102 may comprise, for example, silicon oxide (SiO)2) However, the inventive concept is not limited thereto. For example, the first silicon layer 101 may be a silicon substrate.
Insulating layer 102 may have, for example, a thickness of about
To about
And the second silicon layer 103 may have a thickness 102T of, for example, about
To about
Thickness 103T, the inventive concept is not limited thereto.
When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the relevant numerical value include a tolerance of ± 10% around the recited numerical value. When a range is specified, the range includes all values therebetween, for example, in increments of 0.1%.
The substrate 100 may include a first region I, a second region II, and a third region III adjacent to each other.
For example, a low voltage transistor may be disposed in the first region I, a high voltage transistor may be disposed in the second region II, and a medium voltage transistor may be disposed in the third region III.
The first, second, and third regions I, II, and III may each include an NMOS region N and a PMOS region P.
In fig. 1, it is illustrated that the low voltage transistor, the high voltage transistor, and the middle voltage transistor are sequentially disposed, but the inventive concept is not limited thereto. In some example embodiments, the order of arrangement of the low voltage transistor, the high voltage transistor, and the medium voltage transistor may be changed.
The first channel layer 111 may be disposed in the first region I of the substrate 100. Specifically, the first channel layer 111 may be disposed in the second silicon layer 103 of the PMOS region P in the first region I. Accordingly, the PMOS region P and the NMOS region N in the first region may be referred to as a fourth region and a fifth region of the substrate 100, the first channel layer 111 may be understood to be in the fourth region, and the lower surface 111b of the first channel layer 111 may be understood to be lower (e.g., close to the bottom surface 100b of the substrate) with respect to the upper surface of the fifth region of the substrate 100, where such upper surface of the fifth region may be the upper surface 100a of the substrate 100.
The first channel layer 111 may contact the insulating layer 102. In some example embodiments, the first channel layer 111 may be spaced apart from the insulating layer 102.
The first channel layer 111 may include, for example, silicon germanium (SiGe), but the inventive concept is not limited thereto.
The second channel layer 112 may be disposed in the second region II of the substrate 100. Specifically, the second channel layer 112 may be disposed in the first silicon layer 101 in the PMOS region P in the second region II.
The second channel layer 112 may include, for example, silicon germanium (SiGe), but the inventive concept is not limited thereto.
The third channel layer 113 may be disposed in the third region III of the substrate 100. Specifically, the third channel layer 113 may be disposed in the first silicon layer 101 of the PMOS region P in the third region III.
The third channel layer 113 may include, for example, silicon germanium (SiGe), but the inventive concept is not limited thereto.
The second and third channel layers 112 and 113 may be disposed at the same level with respect to the upper surface of the substrate 100 (e.g., may be at least partially coplanar with the upper surface 100a of the substrate 100). The second channel layer 112 and the third channel layer 113 may each includeIncluding and/or entirely including silicon (Si). The first channel layer 111 may be disposed at a different level from the second and third channel layers 112 and 113 with respect to the upper surface of the substrate 100. To reiterate, the first channel layer 111 may not be at least partially coplanar with the second channel layer 112 and/or the third channel layer 113. That is, the upper surface 111a of the first channel layer 111 may be located at a higher level than the upper surfaces 112a and 113a of the second and third channel layers 112 and 113. To reiterate, the upper surface 111a of the first channel layer 111 may be distant from the bottom surface 100b of the substrate 100 with respect to the upper surface 112a of the second channel layer 112 and the upper surface 113a of the third channel layer 113. For example, a height difference between an upper surface of the first channel layer 111 and each of an upper surface of the second channel layer 112 and an upper surface of the third channel layer 113 may be about
To about
Within the range of (1).
An isolation region STI may be disposed in the substrate 100. An isolation region STI may be disposed between the first region I and the second region II in the substrate 100, and may separate the first region I from the second region II (e.g., at least partially isolate the first region I and the second region II from direct contact with each other) to electrically isolate at least a portion of the first region I from at least a portion of the second region II. An isolation region STI may be disposed between the second region II and the third region III in the substrate 100, and may separate the second region II from the third region III (e.g., at least partially isolate the second region II and the third region III from direct contact with each other) to electrically isolate at least a portion of the second region II from at least a portion of the third region III.
In addition, an isolation region STI may be disposed between the NMOS region N and the PMOS region P in the first region I, and may separate the NMOS region N and the PMOS region P. An isolation region STI may be disposed between the NMOS region N and the PMOS region P in the second region II, and may separate the NMOS region N and the PMOS region P. An isolation region STI may be disposed between the NMOS region N and the PMOS region P in the third region III, and may separate the NMOS region N and the PMOS region P.
As described herein, some of the layers (e.g., insulating layer 102 and second silicon layer 103) in adjacent regions of the first through third regions I, II and III of the substrate 100 are isolated from directly contacting each other, but at least one of the layers (e.g., first silicon layer 101) in adjacent regions of the first through third regions I, II and III of the substrate 100 is not isolated, at least in part, from directly contacting each other (e.g., may remain at least partially in direct contact with each other and/or at least partially in direct contact with a portion of a single, entire, continuous layer), as shown in fig. 1, e.g., the first through third regions I, II and III may still be said to be isolated, at least in part, from directly contacting each other or "separated" from each other.
As described herein, some layers (e.g., insulating layer 102 and second silicon layer 103) in adjacent regions of the first through third regions I, II and III of the substrate 100 are electrically isolated from each other, but at least one layer (e.g., first silicon layer 101) in adjacent regions of the first through third regions I, II and III of the substrate 100 is at least partially not electrically isolated from each other (e.g., may remain at least partially in direct contact with each other and/or at least partially in direct contact with a portion of a single, entire, continuous layer), as shown in fig. 1, for example, the first through third regions I, II and III may still be referred to as having respective one or more portions that are electrically isolated from each other or "separated" from each other.
The isolation region STI for separating the first to third regions I, II and III may extend further into the substrate 100 than the isolation region STI for separating the NMOS region and the PMOS region.
The width of the isolation region STI for separating the first to third regions I, II and III in the first direction X (e.g., the horizontal direction) may be greater than the width of the isolation region STI for separating the NMOS region and the PMOS region in the first direction X. The first direction X may be parallel to the upper surface 100a of the substrate 100.
The isolation region STI may comprise, for example, silicon oxide (SiO)2) Silicon nitride (SiN), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON) and/or silicon oxycarbonitride (SiOCN).
The isolation region STI may be formed of a single layer as shown in fig. 1, but the inventive concept is not limited thereto. For example, the isolation region STI may be formed of multiple layers (e.g., may at least partially include multiple layers).
The first gate structure 120 may be disposed on the second silicon layer 103 in the first region I. The first gate structure 120 on the NMOS region N may constitute or constitute an NMOS transistor, while the first gate structure 120 on the PMOS region P may constitute or constitute a PMOS transistor.
The first gate structure 120 may include a first gate insulating layer 121, a first gate electrode 122, a first capping layer 123, and a first gate spacer 124.
In the first region I, a first gate insulating layer 121 may be disposed on the second silicon layer 103 in the NMOS region N and on the first channel layer 111 in the PMOS region P. The first gate insulating layer 121 may be formed by patterning a third oxide layer 173 described below.
The first gate electrode 122 may be disposed on the first gate insulating layer 121 on the first region I. A first capping layer 123 may be disposed on the first gate electrode 122 on the first region I.
The first source/drain regions 125 may be disposed on opposite sides of the first gate structure 120. The first source/drain region 125 may be disposed in each of the second silicon layer 103 in the NMOS region N and the first channel layer 111 in the PMOS region P. Accordingly, it should be understood that at least some of the first source/drain regions 125 may be in the first channel layer 111.
It will be understood that, herein, an element described as "in" other elements is at least partially located within a space defined by the outermost surfaces of the other elements. For example, in fig. 1, the first source/drain region 125 is at least partially within a space defined by an outermost surface (e.g., the upper surface 111a) of the first channel layer 111, and thus is understood to be "in" the first channel layer 111.
The first source/drain region 125 may protrude from the second silicon layer 103 in the NMOS region N and the first channel layer 111 in the PMOS region P in the second direction Y (e.g., a vertical direction), but the inventive concept is not limited thereto. The second direction Y may be perpendicular to the first direction X (i.e., perpendicular to the upper surface 100a of the substrate 100).
The second gate structure 130 may be disposed on the first silicon layer 101 of the second region II. The second gate structure 130 on the NMOS region N may include or constitute an NMOS transistor, and the second gate structure 130 on the PMOS region P may include or constitute a PMOS transistor.
The second gate structure 130 may include a second gate insulation layer 131, a second gate electrode 132, a second capping layer 133, and a second gate spacer 134.
In the second region II, a second gate insulating layer 131 may be disposed on the first silicon layer 101 in the NMOS region N and on the second channel layer 112 in the PMOS region P. As shown, the second channel layer 112 in the second region II of the substrate 100 may be located between the second source/drain regions 135. The second gate insulating layer 131 may include a first oxide layer 171 described below, a second oxide layer 172 on the first oxide layer 171, and a third oxide layer 173 on the second oxide layer 172. The second gate insulating layer 131 may be formed by patterning the first oxide layer 171, the second oxide layer 172, and the third oxide layer 173.
The second gate electrode 132 may be disposed on the second gate insulating layer 131 on the second region II. A second capping layer 133 may be disposed on the second gate electrode 132 on the second region II.
Second source/drain regions 135 may be disposed on opposite sides of the second gate structure 130. The second source/drain region 135 may be disposed in each of the first silicon layer 101 in the NMOS region N and the first silicon layer 101 in the PMOS region P. The second channel layer 112 may be disposed between the second source/drain regions 135 in the PMOS region P. It should be understood that at least some of the second source/drain regions 135 may be in the second region II of the substrate 100.
The third gate structure 140 may be disposed on the first silicon layer 101 in the third region III. The third gate structure 140 on the NMOS region N may include or constitute an NMOS transistor, and the third gate structure 140 on the PMOS region P may include or constitute a PMOS transistor.
The third gate structure 140 may include a third gate insulation layer 141, a third gate electrode 142, a third capping layer 143, and a third gate spacer 144.
In the third region III, a third gate insulating layer 141 may be disposed on the first silicon layer 101 in the NMOS region N and on the third channel layer 113 in the PMOS region P. The third gate insulating layer 141 may include a second oxide layer 172 and a third oxide layer 173 on the second oxide layer 172. The third gate insulating layer 141 may be formed by patterning the second oxide layer 172 and the third oxide layer 173.
The third gate electrode 142 may be disposed on the third gate insulating layer 141 on the third region III. A third capping layer 143 may be disposed on the third gate electrode 142 on the third region III.
Third source/drain regions 145 may be disposed on opposite sides of the third gate structure 140. The third source/drain region 145 may be disposed in each of the first silicon layer 101 in the NMOS region N and the first silicon layer 101 in the PMOS region P. It is to be understood that the third source/drain region 145 may be located in the third region III of the substrate 100. The third channel layer 113 may be disposed between the third source/drain regions 145 in the PMOS region P, and thus, may be in the third region III of the substrate 100 in addition to between the third source/drain regions 145.
The first thickness t1 of the first oxide layer 171 in the second direction Y may be greater than the second thickness t2 of the second oxide layer 172 in the second direction Y. In addition, a second thickness t2 of the second oxide layer 172 in the second direction Y may be greater than a third thickness t3 of the third oxide layer 173 in the second direction Y.
In other words, the thickness of the second gate insulating layer 131 in the second direction Y on the second region II in which the high voltage transistor is formed may be greater than the thickness of the third gate insulating layer 141 in the second direction Y on the third region III in which the medium voltage transistor is formed. Further, the thickness of the third gate insulating layer 141 in the second direction Y on the third region III in which the medium voltage transistor is formed may be greater than the thickness of the first gate insulating layer 121 in the second direction Y on the first region I in which the low voltage transistor is formed. It will be understood that the first direction X may be a horizontal direction extending parallel to the upper surface 100a and/or the bottom surface 100b of the substrate 100, and the second direction Y may be a vertical direction extending perpendicular to the upper surface 100a and/or the bottom surface 100b of the substrate 100.
The first to third oxide layers 171, 172 and 173 may each include silicon oxide (SiO)2). In some example embodiments, the first to third oxide layers 171, 172 and 173 may each include silicon nitride (SiN), silicon oxynitride (SiON), or a high-k dielectric material having a higher dielectric constant than silicon oxide.
The first to third gate electrodes 122, 132 and 142 may each include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum nitride (TiAlCN), titanium aluminum carbide (TiAl C), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (Moc), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), and/or vanadium (V).
In some example embodiments, the first to third gate electrodes 122, 132, 142 may each include, for example, a conductive metal oxide or a conductive metal oxynitride.
The first to third capping layers 123, 133 and 143 may each include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO)2) Silicon carbonitride (SiCN) and/or silicon oxycarbonitride (SiOCN).
The first to third gate spacers 124, 134 and 144 may each include, for example, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and/or air.
The interlayer insulating layer 150 may cover the first to third gate structures 120, 130 and 140 and the isolation region STI. The interlayer insulating layer 150 may include, for example, silicon oxide (SiO)2) Silicon nitride (SiN) and/or silicon oxynitride (SiON). The interlayer insulating layer 150 may be formed of a single layer. In some example embodiments, the interlayer insulating layer 150 may be formed of a plurality of layers.
In the example embodiment shown in fig. 1, the first region I of the substrate 100 includes a first silicon layer 101, an insulating layer 102, and a second silicon layer 103, which are sequentially stacked, and the second region II and the third region III of the substrate 100 may include a third silicon layer 104 coplanar with the first silicon layer 101, wherein the second channel layer 112 and the third channel layer 113 are both in the third silicon layer 104.
Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 are views illustrating stages in a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. It will be understood that, in some example embodiments, methods of manufacturing semiconductor devices according to some example embodiments may omit at least some of the operations shown in fig. 2 through 16, and/or may perform at least some of the operations shown in fig. 2 through 16 in a different order (e.g., sequence) than the order of the operations shown in fig. 2 through 16.
Referring to fig. 2, a substrate 100 including a first silicon layer 101, an insulating layer 102, and a second silicon layer 103 sequentially stacked (e.g., present at a given location for fabrication, wherein the given location is present at a particular fabrication facility, at a particular location with respect to a particular fabrication facility, etc.) may be provided. To reiterate, a substrate 100 comprising a sequential stack of a first silicon layer 101, an insulating layer 102 and a second silicon layer 103 may be provided. In some example embodiments, providing the substrate 100 may include forming the substrate 100, for example, based on sequentially forming the layers 101, 102, 103. The substrate 100 may include a first region I, a second region II, and a third region III adjacent to each other.
The pad oxide layer 10 may be conformally formed on the upper surface 100a of the substrate 100. That is, the pad oxide layer 10 may be conformally formed on the second silicon layer 103.
Referring to fig. 3, a first mask pattern M1 may be formed on the pad oxide layer 10. A portion of the pad oxide layer 10 and a portion of the second silicon layer 103 may be etched using the first mask pattern M1 as an etch mask to form a channel trench CT in the second silicon layer 103. The channel trench CT may be formed in each of the first to third regions I, II and III, but the inventive concept is not limited thereto. For example, the channel trench CT may be formed only in the first region I.
Referring to fig. 4, a first channel layer 111 may be formed in the channel trench CT. Accordingly, in the case where the channel trench CT is formed in the second silicon layer 103, the first channel layer 111 may be formed in the second silicon layer 103 such that the first channel layer 111 is at least partially coplanar with the second silicon layer 103, as shown at least in fig. 4-5. The first channel layer 111 may include or entirely include, for example, silicon germanium (SiGe). The first channel layer 111 may be formed based on epitaxial growth in the channel trench CT using silicon exposed on the sidewalls and bottom surface of the channel trench CT as a seed. For example, a silicon germanium layer SiGe as the first channel layer 111 may be epitaxially grown in the channel trench CT. As shown, the first channel layer 111 may be formed in different channel trenches CT located in the separate regions I, II and III of the substrate 100. In some example embodiments, each region of the substrate 100 may be defined to extend to the height of the upper surface 100a along the second direction Y; since the channel trench CT extends from the upper surface 100a to the inside of the substrate 100 and the first channel layer 111 is formed within the channel trench CT, the first channel layer 111 may be understood as being formed "in" the corresponding one or more regions of the substrate 100 in which the channel trench CT is formed. Accordingly, it will be understood that the first channel layer 111 may be formed in the first region I of the substrate 100, the second region II of the substrate 100, and/or the third region III of the substrate 100, for example, based on being formed in the respective channel trenches CT of the respective regions of the substrate 100. Accordingly, in some example embodiments, the formation of the first channel layer 111 may include: forming a channel trench CT in the substrate, for example as shown in fig. 3; and further forming the first channel layer 111 in the channel trench CT to partially or completely fill the channel trench CT, but example embodiments are not limited thereto.
The capping oxide layer 20 may be conformally formed on the first channel layer 111, the first mask pattern Ml, and sidewalls of the exposed channel trench CT.
Referring to fig. 5, an upper portion of the first channel layer 111 may be oxidized, and thus, silicon oxide (SiO) may be formed2) Film and may precipitate germanium (Ge). The precipitated germanium (Ge) may react with the second silicon layer 103 under the first channel layer 111 to form a silicon germanium (SiGe) film.
As a result, as shown in fig. 5, the upper surface of the first channel layer 111 may be lowered, and the lower surface of the first channel layer 111 may contact (e.g., directly contact) the insulating layer 102.
Referring to fig. 6, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to remove the first mask pattern M1 and a portion of the capping oxide layer 20 located on the first channel layer 111. The pad oxide layer 10 may serve as an etch stop layer during the planarization process.
Referring to fig. 7, a second mask pattern M2 may be formed on the pad oxide layer 10 and the capping oxide layer 20. A portion of the pad oxide layer 10, a portion of the capping oxide layer 20, a portion of the first channel layer 111, and the substrate 100 may be etched using the second mask pattern M2 as an etch mask to form an isolation trench sti in the substrate 100. The first through third regions I, II and III may be separated from each other (e.g., at least partially separated from direct contact with each other and/or have one or more portions electrically isolated from each other) by an isolation trench sting.
An isolation trench sting may be formed in each of the first to third regions I, II and III so that an NMOS region (see N of fig. 1) and a PMOS region (see P of fig. 1) may be separated.
The isolation material layer 30 may be formed on the second mask pattern M2 and may fill the isolation trench wait.
Referring to fig. 8, an additional planarization process (e.g., a CMP process) may be performed to remove a portion of the second mask pattern M2 and a portion of the isolation material layer 30.
The second mask pattern M2 may be removed, thereby forming the isolation region STI.
As shown in fig. 8, a portion of the isolation region STI may protrude in the second direction Y above the upper surface of the pad oxide layer 10, but the inventive concept is not limited thereto. In some example embodiments, an upper surface of the isolation region STI may be coplanar with an upper surface of the pad oxide layer 10. As shown, the isolation region STI may at least partially isolate the first region I and the second region II from being in direct contact with each other, may at least partially isolate the second region II and the third region III from being in direct contact with each other, etc. Thus, as shown at least in fig. 8, it will be understood that the method according to some of the example embodiments shown in fig. 2 to 16 may comprise forming an isolation region STI in the substrate 100 to at least partially isolate the first region I and the second region II from being in direct contact with each other. It will also be understood that the isolation region STI may be formed in the substrate 100 after the first channel layer 111 is formed.
As shown, the isolation region STI may electrically isolate a portion of the first region I (e.g., a portion of the insulating layer 102 and a portion of the second silicon layer 103 in the first region I) from a portion of the second region II (e.g., a portion of the insulating layer 102 and a portion of the second silicon layer 103 in the second region II), but may not electrically isolate a separate portion of the first region I (e.g., the first silicon layer 101) from a separate portion of the second region II (e.g., the first silicon layer 101). As shown, the isolation region STI may electrically isolate a portion of the second region II (e.g., a portion of the insulating layer 102 and a portion of the second silicon layer 103 in the second region II) from a portion of the third region III (e.g., a portion of the insulating layer 102 and a portion of the second silicon layer 103 in the third region III), but may not electrically isolate a separate portion of the second region II (e.g., the first silicon layer 101) from a separate portion of the third region III (e.g., the first silicon layer 101). Thus, as shown at least in fig. 8, it will be understood that the method according to some of the example embodiments shown in fig. 2 to 16 may comprise forming an isolation region STI in the substrate 100 to electrically isolate a portion of the first region I from a portion of the second region II. It will also be understood that the isolation region STI may be formed in the substrate 100 after the first channel layer 111 is formed.
Referring to fig. 9, an upper surface 100a of each of the second and third regions II and III of the substrate 100 may be etched to expose an upper surface of the first silicon layer 101. For example, the substrate 100 may be etched to a thickness of about
To about
In some example embodiments, the upper surface 100a of only one of the second region II or the third region III may be etched to expose the upper surface of the first silicon layer 101 in the etched region.
Specifically, the pad oxide layer 10, the capping oxide layer 20, the second silicon layer 103, the insulating layer 102, and a portion of the isolation region STI in each of the second and third regions II and III may be removed using the mask pattern formed on the first region I as an etching mask.
Referring to fig. 10, the protective layer 160 may be formed to cover the first to third regions I, II and III of the substrate 100. The protective layer 160 may comprise, for example, silicon nitride. As shown in fig. 10, the protective layer 160 may be formed on the first region I of the substrate 100 and the etched second region II of the substrate to cover (e.g., so as not to expose) the first channel layer 111 in the first region I of the substrate 100 and to cover the second region II of the substrate 100, so that the individual first to third portions 160-1, 160-2 and 160-3 of the protective layer 160 are formed on the individual respective regions I to III of the substrate 100. As shown in fig. 10, the protective layer 160 may be a single continuous uniform layer (e.g., a single integral portion) that may be understood to have separate portions 160-1, 160-2, 160-3 defined by separate respective regions I, II, III of the substrate 100, with the portions 160-1, 160-2, 160-3 being located directly or indirectly on the regions I, II, III, respectively. In some example embodiments, the protective layer 160 may be formed to cover only one or some regions of the substrate 100. For example, in some example embodiments, the protective layer 160 may be formed to cover the first and second regions I and II of the substrate 100, and not the third region III. In some example embodiments, for example, in the case where the substrate 100 omits the second region II and thus the first and third regions I and III are directly adjacent to each other, the protective layer 160 may be formed to cover the first and third regions I and III of the substrate 100 without covering the second region II.
Referring to fig. 11, a portion of the protective layer 160 located on the second and third regions II and III may be removed. Specifically, one or more portions 160-2 and 160-3 of the protection layer 160 located on each of the second and third regions II and III may be etched using the mask pattern formed on the first region I as an etching mask to remove them. As shown in fig. 11, the second portion 160-2 and the third portion 160-3 of the protective layer 160 may be removed, leaving only the first portion 160-1 of the protective layer 160 located on the first region I of the substrate 100. In some example embodiments, only the second portion 160-2 of the protective layer 160 located on the second region II of the substrate 100 is removed.
An impurity implantation process may be performed to implant impurities in the substrate 100, and thus an NMOS region N and a PMOS region P may be formed in each of the first to third regions I, II and III. In addition, through the impurity implantation process, the second source/drain region 135 may be formed in the upper surface of the first silicon layer 101 in the second region II, and the third source/drain region 145 may be formed in the upper surface of the first silicon layer 101 in the third region III. In some example embodiments, the second channel layer 112 may be formed in the first silicon layer 101 between the second source/drain regions 135 in the PMOS region P of the second region II, and the third channel layer 113 may be formed in the first silicon layer 101 between the third source/drain regions 145 in the PMOS region P of the third region III, through an impurity implantation process. Accordingly, after removing the second and third portions 160-2 and 160-3 of the protection layer 160, the second channel layer 112 may be formed at least in the second region II of the substrate 100, and the third channel layer 113 may be formed at least in the third region III of the substrate 100.
The first channel layer 111 may be formed by epitaxial growth as described with reference to fig. 4, and the second channel layer 112 and the third channel layer 113 may be formed by an impurity implantation process.
The second and third channel layers 112 and 113 may include, for example, silicon germanium, but the inventive concept is not limited thereto.
The protective layer 160 may prevent the first channel layer 111 from being oxidized, and may prevent germanium (Ge) from being precipitated from the first channel layer 111.
Referring to fig. 12 to 14, a gate insulating material layer (e.g., a first oxide layer 171 and a second oxide layer 172) may be formed to cover the protective layer 160 on the first region I, the first silicon layer 101 in the second region II, and the first silicon layer 101 in the third region III. In some example embodiments, only one gate insulating material layer (e.g., only one of the first oxide layer 171 or the second oxide layer 172, e.g., only the first oxide layer 171) may be formed on the protective layer 160 and on the second region II of the substrate 100.
Referring to fig. 12, a first oxide layer 171 may be conformally formed as a gate insulating material layer to cover the protective layer 160 on the first region I, the first silicon layer 101 in the second region II, and the first silicon layer 101 in the third region III. The first oxide layer 171 may be formed on the isolation region STI, the second source/drain region 135, the third source/drain region 145, the second channel layer 112, and the third channel layer 113. As shown in fig. 12, the first oxide layer 171 can be a single continuous uniform layer (e.g., a single integral portion) that can be understood to have individual portions 171-1, 171-2, 171-3 defined by individual respective regions I, II, III of the substrate 100, with the portions 171-1, 171-2, 171-3 being located directly or indirectly on the regions I, II, III of the substrate 100, respectively.
Referring to fig. 13, the first oxide layer 171 (e.g., the third portion 171-3 of the first oxide layer 171) on the third region III may be removed using the mask pattern formed on the first oxide layer 171 on the first and second regions I and II as an etching mask. Accordingly, a layer of gate insulating material as the first oxide layer 171 may be formed on the remaining first portion 160-1 of the protective layer 160 and on the exposed second region II of the substrate 100 (e.g., the upper surface 101u of the second region II of the substrate 100) such that the first oxide layer 171 is a continuous layer including the first portion 171-1 and the second portion 171-2, wherein the first portion 171-1 is in direct contact with at least one surface (e.g., the upper surface 160u and/or the side surface 160s) of the remaining first portion of the protective layer 160 and the second portion 171-2 is in direct contact with the upper surface 101u of at least the second region II of the substrate 100.
Although at least fig. 11-13 show a small amount of the protective layer 160 extending over the boundary between the first region I and the second region II, the protective layer 160 shown in fig. 11-13 will be understood to include only the first portion 160-1 of the protective layer 160. Similarly, although fig. 13-16 illustrate a small amount of the first oxide layer 171 extending over the boundary between the second region III and the third region III, the first oxide layer 171 illustrated in fig. 13-16 will be understood to include only the first and second portions 171-1 and 171-2 of the first oxide layer 171. In some example embodiments, the first oxide layer 171 may be referred to as a gate insulating material layer, and the first portion 171-1, the second portion 171-2, and the third portion 171-3 of the first oxide layer 171 may be referred to as first, second, and third portions of the gate insulating material layer, respectively.
Referring to fig. 14, a second oxide layer 172, which is a separate gate insulating material layer, may be conformally formed to cover the first oxide layer 171 on the first region I, the first oxide layer 171 on the second region II, and the first silicon layer 101 in the third region III. The second oxide layer 172 may be formed on the exposed isolation region STI, the third source/drain region 145, and the third channel layer 113. As shown in fig. 14, the second oxide layer 172 may be a single continuous uniform layer (e.g., a single integral portion) that may be understood to have individual portions 172-1, 172-2, 172-3 defined by individual respective regions I, II, III of the substrate 100, with the portions 172-1, 172-2, 172-3 being located directly or indirectly over the regions I, II, III, respectively, of the substrate 100.
Thus, forming the layer of gate insulating material may include: removing a third portion 171-3 of the first oxide layer 171 on the third region III of the substrate 100; and forming a second oxide layer 172 on at least the remaining first and second portions 171-1 and 171-2 of the first oxide layer 171 and on the exposed third region III of the substrate 100 (e.g., the upper surface 101u of the third region III of the substrate 100) such that the second oxide layer 172 is a continuous layer including the first, second, and third portions 172-1, 172-2, 172-3, the first portion 172-1 being in direct contact with at least one surface 171s of the remaining first portion 171-1 of the first oxide layer 171, the second portion 172-2 being in direct contact with at least one surface 171s of the remaining second portion 171-2 of the first oxide layer 171, and the third portion 172-3 being in direct contact with at least the upper surface 101u of the third region III of the substrate 100. The second oxide layer 172 may omit the third portion 172-3. In some example embodiments, the first oxide layer 171 and the second oxide layer 172 may be collectively referred to as a gate insulating material layer.
It will be understood that in some example embodiments, the second region II may be omitted such that the third region III of the substrate 100 is referred to as the second region of the substrate.
The second oxide layer 172 can be formed thinner than the first oxide layer 171 such that the first oxide layer 171 has a substantially uniform thickness 171T in the second direction Y (e.g., up to 10% deviation from a recited magnitude of the thickness 171T on horizontal surfaces extending parallel to the upper surface 100a of the substrate), the second oxide layer 172 has a substantially uniform thickness 172T in the second direction Y (e.g., up to 10% deviation from a recited magnitude of the thickness 172T on horizontal surfaces extending parallel to the upper surface 100a of the substrate), and the thickness 171T of the first oxide layer 171 is greater than the thickness 172T of the second oxide layer 172.
Although the gate insulating material layer (e.g., the first oxide layer 171 and the second oxide layer 172) is formed at a high temperature, the protective layer 160 may prevent the first channel layer 111 from being oxidized and may prevent germanium (Ge) from being precipitated from the first channel layer 111.
Referring to fig. 15, a third mask pattern M3 may be formed on the second oxide layer 172 on the second and third regions II and III. The third mask pattern M3 may be, for example, a photoresist pattern, but the inventive concept is not limited thereto.
The second oxide layer 172, the first oxide layer 171, the protective layer 160, the pad oxide layer 10, and the capping oxide layer 20 formed on the first region of the substrate may be sequentially removed using the third mask pattern M3 as an etch mask.
Specifically, the second oxide layer 172 and the first oxide layer 171 may be removed by a wet etching process. The protective layer 160 may prevent the isolation region STI in the first region I from being etched when the second oxide layer 172 and the first oxide layer 171 are removed by a wet etching process, and thus may prevent a dishing phenomenon from occurring in the isolation region STI.
The protective layer 160 may be removed by a dry etching process. In some example embodiments, the protective layer 160 may be removed by a wet etching process.
Accordingly, as shown in fig. 15, at least a first portion 160-1 of the protection layer 160 and a first portion 171-1 of the first oxide layer 171 (e.g., a first portion of the gate insulating material layer) located on the first region I of the substrate 100 may be removed.
The pad oxide layer 10 and the capping oxide layer 20 may be removed by a wet etching process.
Through the foregoing process, the upper surface of the first channel layer 111 and the upper surface of the second silicon layer 103 in the first region I may be exposed.
Referring to fig. 16, after removing the third mask pattern M3, a third oxide layer 173 as a gate insulating material layer may be conformally formed on the first to third regions I, II and III of the substrate 100. Specifically, the third oxide layer 173 may be formed on the exposed isolation region STI, the second silicon layer 103, the first channel layer 111, and the second oxide layer 172. The third oxide layer 173 may be formed thinner than the second oxide layer 172. The third oxide layer 173 may be formed thinner than the first oxide layer 171.
Referring again to fig. 1, a first gate structure 120 may be formed on the second silicon layer 103 and the first channel layer 111 in the first region I. A second gate structure 130 may be formed on the first silicon layer 101 and the second channel layer 112 in the second region II. A third gate structure 140 may be formed on the first silicon layer 101 and the third channel layer 113 in the third region III.
The first to third gate structures 120, 130 and 140 may be formed through a gate-first process.
A first source/drain region 125 may be formed in the first channel layer 111 and the second silicon layer 103 at opposite sides of the first gate structure 120. An interlayer insulating layer 150 may be formed to cover the first to third gate structures 120, 130 and 140 and the substrate 100.
Accordingly, the semiconductor device shown in fig. 1 can be manufactured by the above-described process.
In the method of manufacturing a semiconductor device according to some example embodiments, by forming the protective layer 160 on the silicon germanium channel (SiGe) layer in the region where the low-voltage transistor is formed during the high-temperature process, the silicon germanium channel (SiGe) layer may be prevented from being oxidized and germanium may be prevented from being precipitated from the silicon germanium channel (SiGe) layer.
In the method of manufacturing a semiconductor device according to some example embodiments, when a wet etching process is performed on a region where a high voltage transistor is formed, a dishing phenomenon may be prevented from occurring in an isolation region STI in a region where a low voltage transistor is formed by forming a protection layer 160 on a silicon germanium channel layer (SiGe) in the region where the low voltage transistor is formed.
Methods of manufacturing semiconductor devices according to some example embodiments are described with reference to fig. 17. Differences between the method of manufacturing a semiconductor device shown in fig. 1 to 16 and the method of manufacturing a semiconductor device of fig. 17 are described.
Fig. 17 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts.
Referring to fig. 17, after performing the processes described with reference to fig. 2 to 16, a first gate structure 220 may be formed on the second silicon layer 103 and the first channel layer 111 in the first region I. A second gate structure 230 may be formed on the first silicon layer 101 and the second channel layer 112 in the second region II. A third gate structure 240 may be formed on the first silicon layer 101 and the third channel layer 113 in the third region III.
The first to third gate structures 220, 230 and 240 may be formed through a gate last process.
The first gate structure 220 may include a first gate insulation layer 221, a first gate electrode 222, a first capping layer 223, a first gate spacer 224, and a first high-k dielectric layer 226.
A first gate insulating layer 221 may be formed on the second silicon layer 103 in the NMOS region N in the first region I and on the first channel layer 111 in the PMOS region P in the first region I.
A first gate spacer 224 defining a first gate trench GT1 may be formed on the first gate insulating layer 221. The first high-k dielectric layer 226 may be formed along sidewalls and a bottom surface of the first gate trench GT 1. The first gate electrode 222 and the first capping layer 223 may be sequentially formed on the first high-k dielectric layer 226 and may fill the first gate trench GT 1.
The second gate structure 230 may include a second gate insulation layer 231, a second gate electrode 232, a second capping layer 233, a second gate spacer 234, and a second high-k dielectric layer 236.
The second gate insulating layer 231 may be formed on the first silicon layer 101 in the NMOS region N in the second region II and on the second channel layer 112 in the PMOS region P in the second region II, and thus, the second gate insulating layer 231 may be located on the second region II of the substrate 100.
A second gate spacer 234 defining a second gate trench GT2 may be formed on the second gate insulating layer 231. The second high-k dielectric layer 236 may be formed along sidewalls and a bottom surface of the second gate trench GT 2. The second gate electrode 232 and the second capping layer 233 may be sequentially formed on the second high-k dielectric layer 236 and may fill the second gate trench GT 2.
The third gate structure 240 may include a third gate insulation layer 241, a third gate electrode 242, a third capping layer 243, a third gate spacer 244, and a third high-k dielectric layer 246.
The third gate insulating layer 241 may be formed on the first silicon layer 101 in the NMOS region N in the third region III and on the third channel layer 113 in the PMOS region P in the third region III, and thus, the third gate insulating layer 241 may be located on the third region III of the substrate 100.
A third gate spacer 244 defining a third gate trench GT3 may be formed on the third gate insulating layer 241. The third high-k dielectric layer 246 may be formed along sidewalls and a bottom surface of the third gate trench GT 3. The third gate electrode 242 and the third capping layer 243 may be sequentially formed on the third high-k dielectric layer 246 and may fill the third gate trench GT 3.
Fig. 18 and 19 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. Differences between the method of manufacturing a semiconductor device as shown in fig. 1 to 16 and the method of manufacturing a semiconductor device of fig. 18 and 19 are mainly described.
Referring to fig. 18 and 19, a pad oxide layer 10 may be conformally formed on the upper surface 300a of the bulk silicon substrate 300.
Next, after performing processes similar to those described with reference to fig. 3 to 16, the manufacturing process as shown in fig. 1 may be performed to manufacture the semiconductor device of fig. 19.
For example, the second region II and the third region III of the bulk silicon substrate 300 may each have a post-etch thickness 300T greater than
And is equal to or less thanIn the order of
The inventive concept is not so limited. In some example embodiments, the process of etching each of the second and third regions II and III of the bulk silicon substrate 300 may be omitted. That is, the respective upper surfaces 300a of the first to third regions I, II and III of the bulk silicon substrate 300 may be coplanar with each other.
Fig. 20 is a view illustrating a semiconductor device according to some example embodiments of the inventive concepts. Differences between the method of manufacturing the semiconductor device shown in fig. 1 to 19 and the method of manufacturing the semiconductor device of fig. 20 are mainly described.
Referring to fig. 20, a pad oxide layer 10 may be formed on an upper surface 400a of a substrate 400 (see fig. 18).
Next, after performing processes similar to those described with reference to fig. 3 to 16, a process as shown in fig. 17 may be performed to manufacture the semiconductor device of fig. 20.
Fig. 21, 22 and 23 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. Differences between the method of manufacturing a semiconductor device as shown in fig. 1 to 16 and the method of manufacturing a semiconductor device of fig. 21 to 23 are mainly described.
Referring to fig. 21, a substrate 100 including a first silicon layer 101, an insulating layer 102, and a second silicon layer 103 sequentially stacked may be provided. A channel material layer 510 may be conformally formed on the upper surface 100a of the substrate 100.
The channel material layer 510 may be formed based on epitaxial growth on the substrate 100 using the upper surface of the second silicon layer 103 as a seed.
Referring to fig. 22, the channel material layer 510 may be etched using the mask pattern formed on the channel material layer 510 as an etch mask to form a first channel layer 511 on the upper surface 100a of each of the first to third regions I, II and III of the substrate 100. Accordingly, it will be understood that forming the first channel layer 511 may include: forming a channel material layer 510 on the substrate 100; and patterning the channel material layer 510 to form a first channel layer 511.
The capping oxide layer 20 may be conformally formed to cover the exposed upper surface 100a of the substrate 100 and the first channel layer 511.
After the processes described with reference to fig. 7 to 16 are performed, the process as shown in fig. 1 may be performed to manufacture the semiconductor device of fig. 23.
Fig. 24, 25 and 26 are views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. Differences between the method of manufacturing a semiconductor device as illustrated in fig. 1 to 16 and the method of manufacturing a semiconductor device of fig. 24 to 26 are described.
Referring to fig. 24, a channel material layer 610 may be conformally formed on an upper surface 600a of a bulk silicon substrate 600. The channel material layer 610 may be formed by epitaxial growth using the upper surface 600a of the bulk silicon substrate 600 as a seed.
Referring to fig. 25, the channel material layer 610 may be etched using the mask pattern formed on the channel material layer 610 as an etching mask to form a first channel layer 611 on the upper surface 600a of each of the first to third regions I, II and III of the bulk silicon substrate 600.
The capping oxide layer 20 may be conformally formed to cover the exposed upper surface 600a of the bulk silicon substrate 600 and the first channel layer 611.
After performing processes similar to those described with reference to fig. 7 to 16, the process as shown in fig. 1 may be performed to manufacture the semiconductor device of fig. 26.
While the present inventive concept has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as set forth in the following claims.
Claims (20)
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first channel layer in a first region of a substrate, the substrate including the first region and a second region;
forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region;
etching an upper surface of the second region of the substrate;
forming a protective layer covering the first channel layer in the first region of the substrate and covering the second region of the substrate;
removing the protective layer on the second region of the substrate;
forming a gate insulating material layer on the protective layer and on the second region of the substrate; and
removing the gate insulating material layer and the protective layer on the first region of the substrate.
2. The method of claim 1, wherein forming the first channel layer comprises:
forming a channel trench in the substrate; and
forming the first channel layer in the channel trench.
3. The method of claim 2, wherein the first channel layer is formed based on epitaxial growth in the channel trench.
4. The method of claim 1, wherein forming the first channel layer comprises:
forming a channel material layer on the substrate; and
patterning the channel material layer to form the first channel layer.
5. The method of claim 4, wherein the channel material layer is formed on the substrate based on epitaxial growth on the substrate.
6. The method of claim 1, wherein the substrate comprises a first silicon layer, an insulating layer, and a second silicon layer sequentially stacked.
7. The method of claim 6, wherein the first channel layer is formed in the second silicon layer.
8. The method of claim 7, wherein the first channel layer directly contacts the insulating layer.
9. The method of claim 6, wherein,
the thickness of the insulating layer is within
To
Within a range of, and
the second silicon layer has a thickness of
To
Within the range of (1).
10. The method of claim 1, wherein the substrate is a bulk silicon substrate.
11. The method of claim 10, wherein the second region of the substrate has an etched thickness greater than
And is equal to or less than
12. The method of claim 1, wherein forming the layer of gate insulating material comprises:
forming a first oxide layer to cover the protective layer on the first region and to cover the second region of the substrate;
removing the first oxide layer on the second region of the substrate; and
forming a second oxide layer on the first oxide layer and on the second region of the substrate.
13. The method of claim 12, wherein a thickness of the first oxide layer is greater than a thickness of the second oxide layer.
14. A method of manufacturing a semiconductor device, the method comprising:
forming a first channel layer in a first region of a substrate, the substrate including the first region and a second region, the first channel layer including silicon germanium;
etching an upper surface of the second region of the substrate;
forming a protective layer covering the first channel layer in the first region of the substrate and covering the second region of the substrate;
removing the protective layer on the second region of the substrate;
forming a second channel layer in the second region of the substrate;
forming a layer of gate insulating material to cover the protective layer and to cover the second region of the substrate; and
removing the gate insulating material layer and the protective layer on the first region of the substrate,
wherein the substrate includes a first silicon layer, an insulating layer, and a second silicon layer sequentially stacked,
wherein the first channel layer is formed in the second silicon layer.
15. The method of claim 14, further comprising:
forming an isolation region in the substrate after forming the first channel layer,
wherein the isolation region electrically isolates a portion of the first region from a portion of the second region.
16. The method of claim 14, wherein forming the first channel layer comprises:
forming a channel trench in the substrate; and
forming the first channel layer in the channel trench based on epitaxial growth.
17. The method of claim 14, wherein forming the layer of gate insulating material comprises:
forming a first oxide layer to cover the protective layer on the first region and to cover the second region of the substrate;
removing the first oxide layer and the protective layer on the first region of the substrate; and
forming a second oxide layer on the first oxide layer of the second region of the substrate.
18. A semiconductor device, comprising:
a substrate comprising a first region, a second region, and a third region;
an isolation region in the substrate, the isolation region electrically isolating respective portions of the first, second, and third regions from one another;
a first channel layer located in the first region of the substrate;
a first gate insulating layer on the first channel layer;
a second gate insulating layer on the second region of the substrate;
a third gate insulating layer on the third region of the substrate;
a first source/drain region in the first channel layer;
a second source/drain region in the second region of the substrate;
a second channel layer located in the second region of the substrate and between the second source/drain regions;
a third source/drain region in the third region of the substrate; and
a third channel layer located in the third region of the substrate and between the third source/drain regions,
wherein an upper surface of the first channel layer is distal from a bottom surface of the substrate relative to both an upper surface of the second channel layer and an upper surface of the third channel layer.
19. The semiconductor device of claim 18,
the first channel layer includes silicon germanium, and
the second channel layer and the third channel layer include silicon.
20. The semiconductor device of claim 18,
a thickness of the first gate insulating layer in a vertical direction extending perpendicular to an upper surface of the substrate is smaller than a thickness of the third gate insulating layer in the vertical direction, and
a thickness of the second gate insulating layer in the vertical direction is greater than the thickness of the third gate insulating layer in the vertical direction.
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| CN117690927A (en) * | 2024-02-04 | 2024-03-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| WO2024098707A1 (en) * | 2022-11-11 | 2024-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor, and memory |
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| US11183429B2 (en) | 2021-11-23 |
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