CN111739788A - Method for preparing germanium-silicon semiconductor material layer and germanium-silicon semiconductor material layer - Google Patents
Method for preparing germanium-silicon semiconductor material layer and germanium-silicon semiconductor material layer Download PDFInfo
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- H01L21/02518—Deposited layers
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Abstract
A method for preparing a germanium-silicon semiconductor material layer, the method comprising: providing a semiconductor substrate; forming a plurality of superlattice layers covering the semiconductor substrate; wherein each superlattice layer comprises a single layer of superlattice SixGe1‑xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1‑xMaterial layer and superlattice Ge materialThe material layers are alternately formed; x is more than 0 and less than or equal to 0.2. The invention can reduce the dislocation density in the germanium-silicon semiconductor material layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for preparing a germanium-silicon semiconductor material layer and the germanium-silicon semiconductor material layer.
Background
Semiconductor wafers are typically prepared from a single crystal ingot (e.g., a silicon ingot) that, after trimming and grinding, can be sliced into individual wafers. Although reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to fabricate the semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of group III and group V elements such as gallium nitride or indium phosphide, or alloys of group II and group IV elements such as cadmium sulfide or zinc oxide.
In the prior art, semiconductor wafers (e.g. silicon wafers) can also be used for producing composite layer structures, for example also silicon-on-insulator or germanium-on-insulator substrates, or substrates on which epitaxial layers (Epilayer) are grown. The Silicon On Insulator (SOI) structure may generally include a handle wafer or layer, a device layer, and an insulating layer (e.g., an Oxide layer) between the handle layer and the device layer, which is helpful for implementing dielectric isolation of devices in an integrated circuit, eliminating a parasitic latch-up effect in a Complementary Metal Oxide Semiconductor (CMOS) circuit, and has the characteristics of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and the like.
The technology is currently expanding from traditional single crystal silicon materials to a new generation of silicon-based materials, such as silicon germanium (SiGe) materials, which are receiving much attention due to their high mobility and other characteristics. Further, the germanium-silicon material can also be applied to other places of a semiconductor device as a semiconductor material.
In the existing method for preparing the germanium-silicon semiconductor material layer, a germanium concentration gradient increasing growth method can be adopted to prepare a germanium-silicon layer on the surface of a silicon substrate, however, the production cost is too high due to the thicker thickness (several micrometers) of the wafer, and the device performance is easily affected due to the poor thermal conductivity between germanium and silicon.
In another prior method of forming a layer of silicon germanium semiconductor material, the SiGe layer may be formed by ion implantation techniques. Specifically, a SiGe layer may be grown directly on a Si substrate, and then subjected to an ion implantation and annealing process to strain relax the SiGe layer. However, since the depth of ion implantation has a large influence on the dislocation density of SiGe, it needs to be strictly controlled within a reasonable implantation depth range to reduce the dislocation density, thereby significantly increasing the difficulty of research and development and the complexity of the process, and being not favorable for controlling the production cost.
In another conventional method for preparing a germanium-silicon semiconductor material layer, a germanium buffer layer can be grown at a low temperature, mainly for relieving stress, and then a germanium epitaxial layer can be grown at a high temperature, so that the dislocation density in the epitaxial film can be controlled from 1E9/cm2Reduced to 5E7/cm2However, for some precision devices, the requirements are still not met.
The inventor of the invention finds that in the existing silicon-germanium material layer, the lattice mismatch of silicon and germanium reaches 4.18%, and the difficulty of silicon-based germanium epitaxy lies in how to overcome a large amount of misfit dislocation caused by lattice mismatch.
There is a need for a method of fabricating a sige semiconductor material layer that can reduce the dislocation density, reduce the leakage channel of the device, and reduce the dark current of the device.
Disclosure of Invention
The invention aims to provide a method for preparing a germanium-silicon semiconductor material layer and the germanium-silicon semiconductor material layer, which can reduce the dislocation density in the germanium-silicon semiconductor material layer.
To solve the above technical problem, an embodiment of the present invention provides a method for preparing a sige semiconductor material layer, including: providing a semiconductor substrate; forming a plurality of superlattice layers stacked on the substrateThe semiconductor substrate; wherein each superlattice layer comprises a single layer of superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layers and the superlattice Ge material layers are alternately formed; x is more than 0 and less than or equal to 0.2.
Optionally, the superlattice Si is formed by RPCVD processxGe1-xA material layer and the superlattice Ge material layer.
Optionally, the superlattice Si is formed by using one or more of the following process parameters of the RPCVD processxGe1-xA material layer, and forming the superlattice Ge material layer: the pressure is 15 to 35 Torr; the temperature is 650-700 ℃; the thickness is 3-10 nm.
Optionally, each layer of superlattice SixGe1-xThe thickness of the material layer is 3-10 nm; and/or the thickness of each superlattice Ge material layer is 3-10 nm.
Optionally, the pressure in the RPCVD process is 15-35 Torr.
Optionally, the number of the superlattice layers is 10-20.
Optionally, in each superlattice layer, the single superlattice Ge material layer is located at a single superlattice Si layerxGe1-xA surface of the material layer.
Optionally, before forming the multi-layer superlattice layer, the method for preparing the silicon germanium semiconductor material layer further includes: forming a Ge buffer layer on the surface of the semiconductor substrate; wherein, the multiple layers of superlattice layers are formed on the surface of the Ge buffer layer.
Optionally, the Ge buffer layer is formed by using an RPCVD process.
Optionally, after the forming the multilayer superlattice layer, the method for manufacturing a silicon germanium semiconductor material layer further includes: and forming a Ge epitaxial layer on the surface of the multilayer superlattice layer.
Optionally, the Ge epilayer is formed by an RPCVD process.
Optionally, the method for preparing the silicon germanium semiconductor material layer further includes: and annealing the semiconductor substrate by adopting an annealing process.
Optionally, the process parameters of the annealing process are selected from one or more of the following: the annealing temperature is 850 ℃ to 900 ℃; the annealing time is 120s to 600 s.
Optionally, the semiconductor substrate is a silicon substrate; before forming the multilayer superlattice layer, the method for preparing the silicon germanium semiconductor material layer further comprises the following steps: after the silicon substrate is conveyed to a chamber for forming the multilayer superlattice layer, baking the silicon substrate by adopting one or more of the following process parameters: the baking temperature is 850 ℃ to 950 ℃; the baking time is 120s to 300 s.
To solve the above technical problem, an embodiment of the present invention provides a sige semiconductor material layer, including: a semiconductor substrate; a plurality of superlattice layers stacked on the semiconductor substrate; wherein each superlattice layer comprises a single layer of superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layers and the superlattice Ge material layers are alternately formed; x is more than 0 and less than or equal to 0.2.
Optionally, the superlattice SixGe1-xThe material layer and the superlattice Ge material layer are formed by an RPCVD process. Optionally, each layer of superlattice SixGe1-xThe thickness of the material layer is 3-10 nm; and/or the thickness of each superlattice Ge material layer is 3-10 nm.
Optionally, the number of the superlattice layers is 10-20.
Optionally, in each superlattice layer, the single superlattice Ge material layer is located at a single superlattice Si layerxGe1-xA surface of the material layer.
Optionally, the silicon germanium semiconductor material layer further includes: the Ge buffer layer is positioned on the surface of the semiconductor substrate; wherein the multilayer superlattice layer is positioned on the surface of the Ge buffer layer.
Optionally, the Ge buffer layer is formed by using an RPCVD process.
Optionally, the thickness of the Ge buffer layer is 80-120 nm.
Optionally, the silicon germanium semiconductor material layer further includes: and the Ge epitaxial layer is positioned on the surface of the multilayer superlattice layer.
Optionally, the Ge epitaxial layer is formed by using an RPCVD process.
Optionally, the thickness of the Ge epitaxial layer is 680-860 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in embodiments of the invention, by forming multiple superlattice layers, each superlattice layer comprises at least a single layer of superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layer and the superlattice Ge material layer are alternately formed, the superlattice layer can be used for preventing bottom layer dislocation from penetrating outwards, for example, when the germanium-silicon semiconductor material layer further comprises a Ge buffer layer and a Ge epitaxial layer, dislocation of the Ge buffer layer can be prevented from penetrating towards the Ge epitaxial layer, and therefore dislocation density in the germanium-silicon semiconductor material layer is reduced.
Further, forming the superlattice Si by using an RPCVD processxGe1-xDue to the fact that the RPCVD process has the characteristic of low pressure, the material layer and the superlattice Ge material layer are beneficial to reducing the proportion of active material Ge oxidized at an interface, and compared with the situation that dislocation defect rate is increased due to the fact that a large amount of GeO is formed in the prior art, by adopting the scheme of the embodiment of the invention, the oxygen content is beneficial to being reduced (for example, the oxygen content is controlled to be below 0.1 ppm), and the interface state of a Ge film is enhanced; further, the superlattice Si may be controlled using an RPCVD processxGe1-xThe material layer and the superlattice Ge material layer have slower growth speed and better film quality, so that the thickness of the superlattice layer is more accurately controlled.
Further, controlling the superlattice SixGe1-xThe material layer and the superlattice Ge material layer are 3-10 nm in thickness, and the number of dislocation defects is reduced due to the fact that the material layer and the superlattice Ge material layer are thin in thickness, so that the superlattice Ge material layer is beneficial to reducing the number of dislocation defectsThe dislocation density in the silicon germanium semiconductor material layer is further reduced.
Furthermore, the number of the multilayer superlattice layers is 10-20, and dislocation of the Ge buffer layer can be effectively prevented from penetrating into the Ge epitaxial layer by arranging a large number of superlattice layers, so that dislocation density in the germanium-silicon semiconductor material layer is reduced.
Further, in each superlattice layer, the single superlattice Ge material layer is positioned on the single superlattice Si layerxGe1-xThe surface of the material layer can enable the surface of the superlattice layer to be Ge, so that a base layer is provided for the subsequent growth of a Ge epitaxial layer, and the dislocation density in the germanium-silicon semiconductor material layer is further reduced.
Furthermore, a Ge buffer layer is formed on the surface of the semiconductor substrate to release stress, and the Ge buffer layer is formed by adopting an RPCVD process, so that the semiconductor substrate is beneficial to adopting a consistent CVD process from a chamber entering to a chamber exiting, the production efficiency is improved, and the production cost is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a SiGe semiconductor material layer in the prior art;
FIG. 2 is a flow chart of a method of fabricating a SiGe semiconductor material layer in an embodiment of the present invention;
fig. 3 to fig. 4 are schematic cross-sectional views of devices corresponding to steps in a method for preparing a sige semiconductor material layer according to an embodiment of the present invention.
Detailed Description
As previously mentioned, there is currently a growing interest in the development of traditional single crystal silicon materials to a new generation of silicon-based materials, such as silicon germanium materials. However, in the existing method for preparing the germanium-silicon semiconductor material layer, the problems that the dislocation density is high and the dark current of the device cannot meet the requirements of the device generally exist.
Specifically, in an existing method for preparing a germanium-silicon semiconductor material layer, a germanium-silicon layer may be prepared on the surface of a silicon substrate by using a germanium concentration gradient growth method, but the production cost is too high due to the thicker thickness (several micrometers) of the wafer, and the device performance is easily affected due to the poor thermal conductivity between germanium and silicon.
In another prior method of forming a layer of silicon germanium semiconductor material, the SiGe layer may be formed by ion implantation techniques. Specifically, a SiGe layer may be grown directly on a Si substrate, and then subjected to an ion implantation and annealing process to strain relax the SiGe layer. However, since the depth of ion implantation has a large influence on the dislocation density of SiGe, it needs to be strictly controlled within a reasonable implantation depth range to reduce the dislocation density, thereby significantly increasing the difficulty of research and development and the complexity of the process, and being not favorable for controlling the production cost.
In another conventional method for preparing a germanium-silicon semiconductor material layer, a germanium buffer layer can be grown at a low temperature, mainly for relieving stress, and then a germanium epitaxial layer can be grown at a high temperature, so that the dislocation density in the epitaxial film can be controlled from 1E9/cm2Reduced to 5E7/cm2However, for some precision devices, the requirements are still not met.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a sige semiconductor material layer in the prior art.
As shown in fig. 1, a semiconductor substrate 100 is provided, a Ge buffer layer 110 is formed on the surface of the semiconductor substrate 100, and a Ge epitaxial layer 120 is formed on the surface of the Ge buffer layer 110.
The Ge buffer layer 110 may be used to relieve stress, thereby helping to reduce dislocation density in the subsequently formed Ge epilayer 120.
The inventor of the invention finds that in the existing silicon-germanium material layer, the lattice mismatch of silicon and germanium reaches 4.18%, and the difficulty of silicon-based germanium epitaxy lies in how to overcome the problem of high dislocation density caused by a large amount of misfit dislocations caused by lattice mismatch.
In embodiments of the invention, by forming multiple superlattice layers, each superlattice layer comprises at least a single layer of superlattice SixGe1-xMaterial layer and single layer superlattice Ge materialLayer, wherein superlattice Si in said multi-layer superlatticexGe1-xThe material layer and the superlattice Ge material layer are alternately formed, the superlattice layer can be used for preventing bottom layer dislocation from penetrating outwards, for example, when the germanium-silicon semiconductor material layer further comprises a Ge buffer layer and a Ge epitaxial layer, dislocation of the Ge buffer layer can be prevented from penetrating towards the Ge epitaxial layer, and therefore dislocation density in the germanium-silicon semiconductor material layer is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a flowchart of a method for preparing a silicon germanium semiconductor material layer according to an embodiment of the present invention. The method for preparing the germanium-silicon semiconductor material layer may include steps S21 to S22:
step S21: providing a semiconductor substrate;
step S22: forming a plurality of superlattice layers stacked on the semiconductor substrate; wherein each superlattice layer at least comprises a single superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layers and the superlattice Ge material layers are alternately formed; x is more than 0 and less than or equal to 0.2.
The above steps will be described with reference to fig. 3 to 4.
Fig. 3 to fig. 4 are schematic cross-sectional views of devices corresponding to steps in a method for preparing a sige semiconductor material layer according to an embodiment of the present invention.
Referring to fig. 3, a semiconductor substrate 200 is provided, a Ge buffer layer 210 is formed on a surface of the semiconductor substrate 200, and a plurality of superlattice layers 230 are formed on a surface of the Ge buffer layer 210, each superlattice layer including a single layer of superlattice SixGe1-x A material layer 231 and a single layer superlattice Ge material layer 232.
Wherein the superlattice Si of each superlattice layerxGe1-xThe material layers 231 and the superlattice Ge material layers 232 may be alternately formed.
The semiconductor substrate 200 may be a silicon (Si) substrate, or the material of the semiconductor substrate 200 may further include germanium (Ge), silicon germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In an embodiment of the present invention, the semiconductor substrate 200 may be subjected to a standard wet chemical clean (e.g., RCA clean), followed by a 200:1 HF rinse (e.g., 120s rinse), and then into a chemical vapor deposition chamber.
Further, the superlattice Si may be formed using an RPCVD processxGe1-x A material layer 231 and the superlattice Ge material layer 232.
Wherein, the adopted Reduced Pressure Chemical Vapor Deposition (RPCVD) process can better control the process parameters such as Pressure, and the like, and because the Pressure is related to the film growth speed, the Reduced Pressure is helpful to adopt a slower speed to generate the film, thereby having the characteristics of good film forming quality, high efficiency, good cost control, and the like.
Further, each layer of superlattice SixGe1-xThe thickness of the material layer can be 3-10 nanometers (nm); and/or, each layer of superlattice SixGe1-xThe thickness of the material layer can be 3-10 nm.
It is noted that the thickness should not be too large, which would require longer time to generate superlattice SixGe1-xThe material layer 231 and the superlattice Ge material layer 232 cause too low production efficiency and increase production cost; the thickness should not be too small, which has a limited effect on reducing the dislocation density and makes it difficult to achieve the desired effect.
As a non-limiting example, a thickness of 3 to 10nm, for example, 3nm, may be provided.
In the embodiment of the invention, the superlattice Si is controlledxGe1-xThe thickness of the material layer and the thickness of the superlattice Ge material layer are 3-10 nm, and the number of dislocation defects is reduced due to the fact that the material layer and the superlattice Ge material layer are thin, so that dislocation density in the germanium-silicon semiconductor material layer is further reduced.
Further, the pressure in the RPCVD process may be 15 to 35Torr (Torr).
It should be noted that the pressure should not be excessive, which would lower the superlattice SixGe1-xThe growth rate of the material layer 231 and the superlattice Ge material layer 232 causes too low production efficiency and increased production cost; the pressure should not be too low, which would raise the superlattice SixGe1-xThe growth rate of material layer 231 and superlattice Ge material layer 232 results in a reduced growth quality and an increased dislocation density.
As a non-limiting example, the pressure may be set to 15 to 35Torr, and for example, the pressure may be set to 25 Torr.
Further, forming the superlattice Si using an RPCVD processxGe1-xThe process parameters of the material layer may include one or more of: the raw material is GeH with the concentration of 10 percent and the flow rate of 100 sccm-300 sccm4And SiH at a flow rate of 30 Standard Cubic center per Minute (sccm) to 70sccm4(ii) a The carrier gas is H with the flow rate of 10slm to 30slm2(ii) a The temperature is 650-700 ℃; the process parameters for forming the superlattice Ge material layer by using the RPCVD process comprise one or more of the following: the raw material is GeH with the concentration of 10 percent and the flow rate of 100 sccm-300 sccm4(ii) a The carrier gas is H with the flow rate of 10slm to 30slm2(ii) a The temperature is 650-700 ℃.
Wherein, 10% germane is used for indicating that the germane source (source) is a mixed gas of germane and hydrogen, and the molar volume ratio of germane to hydrogen is 1: 9.
It is noted that the temperature should not be too high, which would raise the superlattice SixGe1-xThe growth rate of material layer 231 and superlattice Ge material layer 232 results in reduced growth quality and increased dislocation density; the temperature should not be too low, which would lower the superlattice SixGe1-xThe growth rate of the material layer 231 and the superlattice Ge material layer 232 causes the production efficiency to be too low and the production cost to be increased.
As a non-limiting example, a temperature of 650 to 700 deg.C may be set.
In specific implementations, GeH may be employed4And SiH4As the starting material, H is used2As a carrier gas, the superlattice Si is generatedxGe1-x A material layer 231; and/or, GeH can be used4As the starting material, H is used2As a carrier gas, the superlattice Ge material layer 232 is generated.
As a non-limiting example, 10%, 100sccm to 300sccm of GeH can be used4And SiH of 30sccm to 70sccm4As a raw material, 10slm to 30slm of H is used2As a carrier gas, the superlattice Si is generatedxGe1-xA layer of material 231.
In one embodiment of the present invention, 10% GeH of 200sccm can be used4And 40sccm SiH4As starting material, 20slm of H was used2As a carrier gas to cause the formation of superlattice SixGe1-xMaterial layer 231 is more desirable.
As a non-limiting example, 10%, 100sccm to 300sccm of GeH can be used4As a raw material, 10slm to 30slm of H is used2As a carrier gas, the superlattice Ge material layer 232 is generated.
In one embodiment of the present invention, 10% GeH of 200sccm can be used4As starting material, 20slm of H was used2As a carrier gas to make the resulting superlattice Ge material layer 232 more desirable.
In an embodiment of the present invention, the superlattice Si is formed by using an RPCVD processxGe1-xThe material layer 231 and the superlattice Ge material layer 232 are beneficial to reducing the oxidation proportion of active material Ge at the interface due to the low-pressure characteristic of the RPCVD process, and compared with the dislocation defect rate increase caused by the formation of a large amount of GeO in the prior art, the scheme provided by the embodiment of the invention is beneficial to reducing the oxygen content (for example, controlling the oxygen content to be below 0.1 ppm) and enhancing the interface state of a Ge film; further, the superlattice Si may be controlled using an RPCVD processxGe1-xGrowth rate of material layer 231 and the superlattice Ge material layer 232Slower, better film quality, and thus more precise control of the thickness of the superlattice layer 230.
Further, the number of the superlattice layers 230 may be set to 10 to 20.
It should be noted that the number of the superlattice layer 230 should not be too small, and too small may have a limited effect on reducing the dislocation density, so that the desired effect is difficult to achieve; the number of layers of the superlattice layer 230 should not be too large, which may result in an excessive total thickness of the superlattice layer 230, affect the quality of the germanium-silicon semiconductor material layer, and increase the production cost.
As a non-limiting example, the number of layers of the multi-layered superlattice layer may be set to 10 to 20, and the total thickness of the superlattice layer 230 may be controlled as much as possible.
In the embodiment of the invention, the number of the multilayer superlattice layers is 10-20, and the dislocation of the Ge buffer layer can be effectively prevented from penetrating into the Ge epitaxial layer by arranging a large number of superlattice layers, so that the dislocation density in the germanium-silicon semiconductor material layer is reduced.
It should be noted that, in the embodiment of the present invention, by using the RPCVD process, the process parameters such as pressure and the like may be effectively adjusted to generate the superlattice layer 230 with a relatively thin thickness (e.g., 1nm to 5nm), and then a relatively large number (e.g., 10 to 20) of superlattice layers may be set, so that the dislocations of the Ge buffer layer are effectively prevented from penetrating into the Ge epitaxial layer, the dislocation density in the germanium-silicon semiconductor material layer is reduced, and the total thickness of the superlattice layer 230 is effectively controlled and controlled.
Further, in each superlattice layer, the single superlattice Ge material layer 232 is located on a single superlattice SixGe1-xThe surface of material layer 231, i.e., superlattice Ge material layer 232, is stacked on superlattice SixGe1-xOver material layer 231.
In an embodiment of the present invention, the single layer superlattice Ge material layer 232 is located on the single layer superlattice Si in each superlattice layerxGe1-xThe surface of the material layer 231 may be Ge-doped on the surface of the top superlattice layer 230, thereby providing a base layer for the subsequent Ge epilayer growth and further reducing germaniumDislocation density in a layer of silicon semiconductor material.
Further, before forming the multi-layered superlattice layer 230, a Ge buffer layer 210 may be formed on the surface of the semiconductor substrate 200, wherein the multi-layered superlattice layer 230 may be formed on the surface of the Ge buffer layer 210.
In the embodiment of the invention, by forming the Ge buffer layer 210 on the surface of the semiconductor substrate 200, the stress can be effectively reduced, and the dislocation density can be further reduced.
Still further, the Ge buffer layer may be formed using an RPCVD process.
In the embodiment of the invention, the Ge buffer layer 210 is formed on the surface of the semiconductor substrate to release stress, and the RPCVD process is adopted to form the Ge buffer layer 210, so that the semiconductor substrate is beneficial to adopting a uniform CVD process from the chamber entering to the chamber exiting, the production efficiency is improved, and the production cost is reduced.
As a non-limiting example, the process parameters for forming the Ge buffer layer using an RPCVD process include one or more of: the raw material is GeH with the concentration of 10 percent and the flow rate of 100 sccm-300 sccm4(ii) a The carrier gas is H with the flow rate of 30slm to 50slm2(ii) a The pressure is 15 to 35 Torr; the temperature is 330-370 ℃; the thickness is 80-120 nm.
In one embodiment of the present invention, 10% GeH of 200sccm can be used4As the starting material, 40slm of H was used2As a carrier gas, the Ge buffer layer 210 is generated, and the Ge buffer layer 210 may be formed by using one or more of the following RPCVD processes: the pressure was 25 Torr; the temperature is 330-370 ℃; the thickness is 80-120 nm.
Further, the semiconductor substrate 200 may be provided as a silicon substrate; before forming the multi-layered superlattice layer 230, the method for preparing the silicon germanium semiconductor material layer may further include: after the silicon substrate is conveyed to a chamber for forming the multilayer superlattice layer, baking the silicon substrate by adopting one or more of the following process parameters: the baking temperature is 850 ℃ to 950 ℃; the baking time is 120 seconds(s) to 300 s.
In the embodiment of the invention, the step of baking the silicon substrate is arranged, so that water vapor and a thin oxide layer on the surface of the silicon substrate can be effectively removed, and the quality of a germanium-silicon semiconductor material layer formed in the subsequent process is improved.
Referring to fig. 4, a Ge epitaxial layer 220 is formed on the surface of the multi-layered superlattice layer 230.
Further, the Ge epilayer 220 may be formed using an RPCVD process.
In the embodiment of the present invention, the Ge epitaxial layer 220 is formed on the surface of the multi-layer superlattice layer 230, and the Ge epitaxial layer 220 is formed by using an RPCVD process, which is beneficial to enabling the semiconductor substrate to adopt a uniform CVD process from the chamber entering to the chamber exiting, thereby improving the production efficiency and reducing the production cost.
As a non-limiting example, the process parameters for forming the Ge epilayer using an RPCVD process include one or more of: the raw material is GeH with the concentration of 10 percent and the flow rate of 50 sccm-150 sccm4(ii) a The carrier gas is H with the flow rate of 10slm to 30slm2(ii) a The pressure is 35to 45 Torr; the temperature is 650-700 ℃; the thickness is 680-860 nm.
In one embodiment of the present invention, 10% GeH of 100sccm can be used4As starting material, 20slm of H was used2As a carrier gas, the Ge epilayer 220 is generated; forming the Ge epilayer 220 using one or more of the RPCVD processes: the pressure was 40 Torr; the temperature is 650-700 ℃; the thickness is 680-860 nm.
Further, the method for preparing the silicon germanium semiconductor material layer may further include: the semiconductor substrate 200 is annealed using an annealing process.
It is understood that in the germanium-silicon semiconductor material layer shown in fig. 4, the semiconductor substrate 200 may further include a Ge buffer layer 210, a multi-layered superlattice layer 230, and a Ge epitaxial layer 220.
As a non-limiting example, the process parameters of the annealing process may be selected from one or more of the following: the annealing temperature is 850 ℃ to 900 ℃; the annealing time is 120s to 600 s.
In an embodiment of the present invention, a sige semiconductor material layer is further disclosed, and referring to fig. 4, the sige semiconductor material layer may include: a semiconductor substrate 200; a plurality of superlattice layers 230, the plurality of superlattice layers 230 being stacked on the semiconductor substrate 200; wherein each superlattice layer 230 comprises a single layer of superlattice SixGe1-x A material layer 231 and a single layer superlattice Ge material layer 232, wherein the superlattice Si in the multi-layer superlattice 230xGe1-xThe material layers 231 and the superlattice Ge material layers 232 are alternately formed; x is more than 0 and less than or equal to 0.2.
Further, the superlattice SixGe1-xThe material layer 231 and the superlattice Ge material layer 232 are formed using an RPCVD process.
Further, the superlattice SixGe1-xThe thickness of the material layer 231 is 3-10 nm, and the thickness of the superlattice Ge material layer 232 is 3-10 nm.
Further, the number of layers of the superlattice layer 230 is 10-20.
Further, in each superlattice layer 230, the single superlattice Ge material layer 232 is located on the single superlattice SixGe1-xThe surface of material layer 231.
Further, the silicon germanium semiconductor material layer further comprises: a Ge buffer layer 210 located on a surface of the semiconductor substrate; wherein the multi-layered superlattice layer 230 is located on a surface of the Ge buffer layer 210.
Further, the Ge buffer layer 210 is formed using an RPCVD process.
Further, the thickness of the Ge buffer layer 210 is 80-120 nm.
Further, the silicon germanium semiconductor material layer further comprises: ge epilayer 220
Further, the Ge epilayer 220 is formed using an RPCVD process.
Further, the thickness of the Ge epitaxial layer 220 is 680-860 nm.
For the principle, specific implementation and beneficial effects of the sige semiconductor material layer, please refer to the description related to the method for preparing the sige semiconductor material layer shown in fig. 2 to fig. 4, which is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (24)
1. A method for preparing a germanium-silicon semiconductor material layer is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a plurality of superlattice layers stacked on the semiconductor substrate;
wherein each superlattice layer comprises a single layer of superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layers and the superlattice Ge material layers are alternately formed;
0＜x≤0.2。
2. the method for preparing the SiGe semiconductor material layer according to claim 1, wherein the superlattice Si is formed by an RPCVD processxGe1-xA material layer and the superlattice Ge material layer.
3. The method of claim 2, wherein each layer of superlattice Si is selected from the group consisting ofxGe1-xThe thickness of the material layer is 3-10 nm;
and/or the thickness of each superlattice Ge material layer is 3-10 nm.
4. The method for preparing the SiGe semiconductor material layer according to claim 2, wherein the pressure in the RPCVD process is 15-35 Torr.
5. The method for preparing the germanium-silicon semiconductor material layer according to claim 1, wherein the number of layers of the superlattice layer is 10-20.
6. The method of claim 1 wherein said single layer of superlattice Ge material is located in a single layer of superlattice Si in each superlattice layerxGe1-xA surface of the material layer.
7. The method of claim 1, further comprising, prior to forming the multi-layered superlattice layer:
forming a Ge buffer layer on the surface of the semiconductor substrate;
wherein, the multiple layers of superlattice layers are formed on the surface of the Ge buffer layer.
8. The method of claim 7, wherein the Ge buffer layer is formed by an RPCVD process.
9. The method for forming a germanium-silicon semiconductor material layer according to claim 1, further comprising, after said forming a multilayer superlattice layer:
and forming a Ge epitaxial layer on the surface of the multilayer superlattice layer.
10. The method of claim 9, wherein the Ge epilayer is formed using an RPCVD process.
11. The method for preparing a silicon germanium semiconductor material layer according to any one of claims 1 to 10, further comprising:
and annealing the semiconductor substrate by adopting an annealing process.
12. The method for preparing the germanium-silicon semiconductor material layer according to claim 11, wherein the process parameters of the annealing process are selected from one or more of the following:
the annealing temperature is 850 ℃ to 900 ℃;
the annealing time is 120s to 600 s.
13. The method for preparing the germanium-silicon semiconductor material layer according to claim 1, wherein the semiconductor substrate is a silicon substrate;
before forming the multilayer superlattice layer, the method further comprises the following steps:
after the silicon substrate is conveyed to a chamber for forming the multilayer superlattice layer, baking the silicon substrate by adopting one or more of the following process parameters:
the baking temperature is 850 ℃ to 950 ℃;
the baking time is 120s to 300 s.
14. A silicon germanium semiconductor material layer, comprising:
a semiconductor substrate;
a plurality of superlattice layers stacked on the semiconductor substrate;
wherein each superlattice layer comprises a single layer of superlattice SixGe1-xA material layer and a single layer superlattice Ge material layer, wherein the superlattice Si in the multi-layer superlatticexGe1-xThe material layers and the superlattice Ge material layers are alternately formed;
0＜x≤0.2。
15. the layer of silicon germanium semiconductor material of claim 14, wherein said superlattice Si is selected from the group consisting ofxGe1-xThe material layer and the superlattice Ge material layer are formed by an RPCVD process.
16. The silicon germanium semiconductor material layer of claim 14,
superlattice Si per layerxGe1-xThe thickness of the material layer is 3-10 nm;
and/or the thickness of each superlattice Ge material layer is 3-10 nm.
17. The SiGe semiconductor material layer according to claim 14, wherein the number of layers of the superlattice layer is 10-20.
18. The layer of germanium-silicon semiconductor material of claim 14, wherein in each superlattice layer, said single superlattice Ge material layer is located in a single superlattice SixGe1-xA surface of the material layer.
19. The silicon germanium semiconductor material layer of claim 14 further comprising:
the Ge buffer layer is positioned on the surface of the semiconductor substrate;
wherein the multilayer superlattice layer is positioned on the surface of the Ge buffer layer.
20. The layer of germanium-silicon semiconductor material of claim 19, wherein said Ge buffer layer is formed using an RPCVD process.
21. The SiGe semiconductor material layer of claim 20, wherein the Ge buffer layer has a thickness of 80-120 nm.
22. The silicon germanium semiconductor material layer of claim 14 further comprising:
and the Ge epitaxial layer is positioned on the surface of the multilayer superlattice layer.
23. The layer of silicon-germanium semiconductor material of claim 22, wherein said Ge epilayer is formed using a RPCVD process.
24. The SiGe semiconductor material layer of claim 23, wherein the Ge epitaxial layer has a thickness of 680-860 nm.
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