CN111737183A - Server and communication fault processing method and system of I2C bus - Google Patents
Server and communication fault processing method and system of I2C bus Download PDFInfo
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Abstract
The application discloses communication fault handling method of I2C bus, is applied to any I2C controller on I2C bus, and I2C bus and target interface multiplex, includes: after the communication of the I2C bus is identified to have a fault, switching the I2C bus to a target mode to enable the SDA in the I2C bus to be used as a first pin of a target interface and enable the SCL in the I2C bus to be used as a second pin of the target interface; after determining that the first pin of the target interface is at a low level, controlling a second pin of the target interface to output N clock signals; wherein N is a positive integer not less than 9; the target mode is restored to I2C bus mode. By applying the scheme of the application, the communication fault processing of the I2C bus is effectively realized, and the implementation is facilitated without adding hardware. The application also provides a server and a communication fault processing system of the I2C bus, and the server and the communication fault processing system have corresponding technical effects.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a server and a communication fault processing method and system of an I2C bus.
Background
The I2C bus is a bidirectional two-wire synchronous serial bus that requires only two wires to transfer information between devices connected to the bus. I.e. only one Data line SDA (Serial Data line) and one Clock line SCL (Serial Clock line) are required. SDA and SCL are both bidirectional I/O lines, and an interface circuit is open-drain output and needs to be connected with a power supply VCC through a pull-up resistor. When the bus is idle. The two lines are high-level, the same devices connected with the bus are CMOS devices, the output stage is also an open-drain circuit, and the structure can realize the line and the function.
The master device is used to initiate the bus to transfer data and generate a clock to open up the transferred devices when any addressed device is considered a slave device. The relationship of master and slave, send and receive on the bus is not constant, but depends on the direction of data transfer at the moment. If the master wants to send data to the slave, the master addresses the slave first, then actively sends data to the slave, and finally the master terminates data transmission. If the host wants to receive the data of the slave, the host addresses the slave firstly, then the host receives the data sent by the slave, and finally the host terminates the receiving process. Furthermore, when multiple hosts need to use the I2C bus, the current host may be determined through an arbitration mechanism.
According to the requirements of the specification manual of I2C-bus specification and user manual v.6, hereinafter referred to as the specification manual of I2C, when data signals are transmitted, the SDA of I2C can be changed only when the SCL is low, the SDA needs to be held when the SCL is high, and corresponding to the chip design, the sampling and the change of the falling edge are shown in fig. 1.
Due to the hardware characteristics of the I2C bus, such as open drain output, pull-up resistance, and wire and logic, it is determined that as long as any device on the I2C bus pulls SDA or SCL low, no other device can drive them up, i.e., all devices are seen as low. Therefore, if one device does not release the bus, the communication on the whole bus is blocked, and other devices see that the bus is busy, so that normal communication failure is caused. As defined by the I2C specification manual, when the SDA of the I2C bus is pulled low all the way down, the master may send 9 clk signals to cause the slave to release the I2C bus. Many processors will have an associated register address of the I2C controller, providing the user with an associated interface to control the high and low of the SDA, SCL signals, such as the x86 architecture processor. However, some types of processors do not have a relevant register to directly control the high and low of the SDA and SCL signals, so that when the I2C bus pulls the SDA low all the time, the bus cannot be restored by sending 9 clk signals. For this type of processor, the current processing scheme is addressed by the CPLD, which sends 9 clks when it senses that the I2C bus is hung. However, such a scheme may occupy CPLD resources, especially, a board needs to be re-punched on a board that is not originally reserved for a CPLD, and when the number of I2C controllers on the I2C bus is large, the implementation cost of such a scheme is very high, the complexity of design may also be increased, and the impedance of the I2C bus may also be changed, which affects the communication quality. In another processing scheme, a slave reset circuit is added, and when the slave pulls down the SDA, the reset is realized through hardware, so that the complexity of hardware design is increased, and the hardware cost of the scheme is increased.
In summary, how to effectively handle the communication failure of the I2C bus, reduce the cost, and reduce the complexity of the design is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a server, and a communication fault processing method and a system of an I2C bus, so as to effectively process communication fault processing of the I2C bus, reduce cost and reduce complexity of design.
In order to solve the technical problems, the invention provides the following technical scheme:
a communication fault processing method of an I2C bus is applied to any I2C controller on an I2C bus, and the I2C bus is multiplexed with a target interface, and comprises the following steps:
after recognizing that the communication of the I2C bus has a fault, switching the I2C bus to a target mode to use a serial data line (SDA) in the I2C bus as a first pin of the target interface and a Serial Clock Line (SCL) in the I2C bus as a second pin of the target interface;
after the first pin of the target interface is determined to be at a low level, controlling a second pin of the target interface to output N clock signals; wherein N is a positive integer not less than 9;
the target mode is restored to the I2C bus mode such that the first pin of the target interface is used as the serial data line SDA in the I2C bus and the second pin of the target interface is used as the serial clock line SCL in the I2C bus.
Preferably, the method further comprises the following steps:
after the first pin of the target interface is determined to be at a high level, controlling a second pin of the target interface to output a high level signal lasting for a preset first duration, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
Preferably, the method further comprises the following steps:
after controlling the second pin of the target interface to output N clock signals, controlling the second pin of the target interface to output a high level signal lasting for a preset first duration, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
Preferably, the period of the clock signal is T, and T is equal to the inverse of the current communication frequency.
Preferably, the first duration is equal to half of the inverse of the current communication frequency.
Preferably, the target interface is a GPIO interface, and the target mode is a GPIO mode;
correspondingly, after determining that the first pin of the target interface is at a low level, controlling the second pin of the target interface to output N clock signals includes:
setting a first pin of the target interface as an input mode, and judging whether the first pin of the target interface is at a low level;
and if so, setting a second pin of the target interface to be in an output mode, and controlling the second pin of the target interface to output N clock signals.
Preferably, the processor corresponding to any I2C controller on the I2C bus is an ft2000+ processor.
A communication fault processing system of an I2C bus is applied to any I2C controller on an I2C bus, and the I2C bus is multiplexed with a target interface, and comprises:
the multiplexing switching module is used for switching the I2C bus into a target mode to enable a serial data line SDA in the I2C bus to be used as a first pin of the target interface and enable a serial clock line SCL in the I2C bus to be used as a second pin of the target interface after the communication of the I2C bus is identified to have a fault;
the clock signal output module is used for controlling a second pin of the target interface to output N clock signals after the first pin of the target interface is determined to be at a low level; wherein N is a positive integer not less than 9;
a multiplexing recovery module, configured to recover the target mode to an I2C bus mode, so that a first pin of the target interface is used as a serial data line SDA in the I2C bus, and a second pin of the target interface is used as a serial clock line SCL in the I2C bus.
Preferably, the method further comprises the following steps:
the first STOP signal simulation module is used for controlling a second pin of the target interface to output a high level signal lasting for a preset first duration after determining that a first pin of the target interface is a high level, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and the STOP signal second simulation module is used for controlling the first pin and the second pin of the target interface to output high level signals after the first time length, lasting for a preset second time length, and executing the operation of restoring the target mode to the I2C bus mode after the second time length.
A server comprises the communication fault processing system of the I2C bus.
By applying the technical scheme provided by the embodiment of the invention, the implementation is not required to be realized by an additional CPLD as in the traditional scheme, the scheme of the invention does not increase the hardware cost and the complexity of hardware design, and the scheme is convenient to deploy. Specifically, the I2C bus and the target interface are multiplexed, so after any I2C controller recognizes that the communication of the I2C bus has a fault, the scheme of the present application switches the I2C bus to the target mode, that is, the serial data line SDA in the I2C bus is used as the first pin of the target interface, and the serial clock line SCL in the I2C bus is used as the second pin of the target interface. At this time, if it is determined that the first pin of the target interface is at a low level, that is, it indicates that the SDA is pulled down, the I2C controller controls the second pin of the target interface to output N clock signals, that is, output N clk signals, of course, N needs to be a positive integer not less than 9, and after the N clock signals are output, the SDA may be pulled up, that is, a communication fault condition caused by the SDA being pulled down in the I2C bus is solved, and then the target mode may be restored to the I2C bus mode. In summary, the scheme of the application effectively realizes communication fault processing of the I2C bus, and does not need to add hardware, which is beneficial to reducing implementation cost of the scheme and reducing complexity of design.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a timing diagram illustrating the need for SCL to be low for SDA data change during data signal transmission;
FIG. 2 is a flowchart of an embodiment of a communication fault handling method of an I2C bus according to the present invention;
FIG. 3 is a timing diagram illustrating the SDA pulling down during an ACK signal;
fig. 4 is a schematic structural diagram of a communication fault handling system of an I2C bus according to the present invention.
Detailed Description
The core of the invention is to provide a communication fault processing method of an I2C bus, which effectively realizes the communication fault processing of the I2C bus, does not need to increase hardware, is beneficial to reducing the implementation cost of a scheme and reduces the complexity of design.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a flowchart illustrating an implementation of a communication fault handling method for an I2C bus according to the present invention, where the communication fault handling method for an I2C bus can be applied to any I2C controller on an I2C bus, and the I2C bus is multiplexed with a target interface, the communication fault handling method for an I2C bus may include the following steps:
step S101: after recognizing that the communication of the I2C bus has a fault, the I2C bus is switched to the target mode to use the serial data line SDA in the I2C bus as the first pin of the target interface and the serial clock line SCL in the I2C bus as the second pin of the target interface.
In practical applications, a common communication failure of the I2C bus is that the SDA is pulled down, for example, when the master writes data or writes an address to the slave, the slave sends an ACK signal, and pulls down the SDA during the 9 th CLK period, referring to fig. 3, a timing diagram of pulling down the SDA during the ACK signal is shown, and fig. 3 is a timing diagram of normal operation. For example, in the case of the ACK signal, an abnormal condition occurs, for example, the master is plugged and unplugged once, so that the slave does not receive the CLK signal, the SDA is pulled low all the time, and a communication failure of the I2C bus is caused. Of course, other time periods when the SDA is low, other than during the slave sending the ACK signal, may cause the slave to hang up the I2C bus, i.e., pull SDA low, due to the slave not receiving the CLK signal due to the exception.
The I2C bus of the application is multiplexed with the target interface, the specific type of the target interface can be set and selected according to actual needs, and the operation of subsequent steps can be realized only based on the target interface, namely, the selected target interface can realize the purpose of the application. For example, in a specific embodiment of the present invention, the purpose of the present application may be well achieved in consideration that the GPIO interface may set an input mode or an output mode, so that in the specific implementation, the target interface may be selected as the GPIO interface, and accordingly, the target mode is the GPIO mode.
Any I2C controller on the I2C bus can execute the scheme of the present application, but generally speaking, when the I2C controller acts as a host, the communication of the I2C bus is recognized to have a fault, and the scheme process of the present application is executed. For example, when a master fails to communicate with a sensor or an intelligent battery serving as a slave, the master can determine that communication of the I2C bus has a fault, and when the master detects that the I2C bus is in a busy state for a long time, the master can determine that communication of the I2C bus has a fault.
After recognizing that there is a failure in communication of the I2C bus, the host switches the I2C bus to the target mode to use the serial data line SDA in the I2C bus as the first pin of the target interface and use the serial clock line SCL in the I2C bus as the second pin of the target interface, i.e., to use the I2C bus as the target interface.
For example, the target interface is a GPIO interface, the target mode is a GPIO mode, and for example, for an I2C bus, the SCL of the I2C bus is multiplexed with the B0 pin of the GPIO interface, and the SDA of the I2C bus is multiplexed with the B1 pin of the GPIO interface. It should be emphasized that, in practical applications, there may be a plurality of I2C buses, and for different I2C buses, corresponding target interfaces may be configured to be multiplexed with the I2C bus.
Step S102: after determining that the first pin of the target interface is at a low level, controlling a second pin of the target interface to output N clock signals; wherein N is a positive integer not less than 9.
After the I2C bus is used as the target interface, it is necessary to determine whether the first pin of the target interface is low. For example, when the target interface is a GPIO interface and the target mode is a GPIO mode, step S102 may specifically include:
setting a first pin of a target interface as an input mode, and judging whether the first pin of the target interface is at a low level or not;
if yes, setting the second pin of the target interface to be in an output mode, and controlling the second pin of the target interface to output N clock signals.
For example, in the foregoing example, SCL of the I2C bus is multiplexed with the B0 pin of the GPIO interface, SDA of the I2C bus is multiplexed with the B1 pin of the GPIO interface, the pin B1 is set to the input mode, and it is determined whether the pin B1 is at the low level. If the slave is in the standby state, it can be stated that the communication failure of the I2C bus is caused by the SDA being hung up by the slave, that is, pulled down by the slave, and in order to release the SDA by the slave, the second pin of the target interface is controlled to output N clock signals, so that the slave releases the SDA. In this example, control pin B0 outputs N clock signals.
It should be noted that, when communication is based on I2C, the communication is formed by adding one bit of ACK signal to one byte, that is, 9 bits in total, and if an abnormality occurs during the first bit of communication and the slave pulls down the SDA, the master needs to output 9 clk signals, which can cause the slave to release the SDA, and if a communication abnormality occurs during sending the ACK signal and the slave pulls down the SDA, the master only needs to output 1 clk signal to cause the slave to release the SDA. That is, in general, the master outputs at most 9 clk signals, so that the slave releases the SDA, and therefore in the solution of the present application, N needs to be set to a positive integer not less than 9, and in practical applications, N is usually set to 9. Of course, the object of the present application can be achieved when N is greater than 9.
The period of the clock signal can be set according to actual needs, and in an embodiment of the present invention, the period of the clock signal is T, and T is equal to the inverse of the current communication frequency. For example, if the current communication frequency is 100khz, the period T of the clock signal is 10 us. Then in the previous example, configuration B0 is high, delayed by 5us, reconfigured B0 is low, delayed by 5us, and repeated 9 times to generate 9 clock signals.
In this embodiment, when the period of the clock signal is set to T, the current communication frequency is considered, and it is avoided that the clock signal is not processed from the machine in time when the period of the clock signal is too short, that is, the clock signal is not recognized, and certainly, if the period of the clock signal is too long, the execution time consumption of the scheme of the present application is prolonged.
Step S103: the target mode is restored to the I2C bus mode such that the first pin of the target interface is used as the serial data line SDA in the I2C bus and the second pin of the target interface is used as the serial clock line SCL in the I2C bus.
After the second pin of the control target interface outputs N clock signals, the slave releases the SDA, and the communication of the I2C bus can be recovered to normal, so that the target mode can be recovered to the I2C bus mode, that is, the target interface is recovered to the I2C bus for use, and the I2C bus mode described in the step indicates that the target interface is used as the I2C bus instead of the target interface.
In an embodiment of the present invention, the method may further include:
after the first pin of the target interface is determined to be the high level, controlling the second pin of the target interface to output a high level signal lasting for a preset first duration, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
The applicant finds that in practical application, after the communication of the I2C bus is identified to have a fault and the I2C bus is switched to the target mode, the first pin of the target interface is identified as high level. After analysis, the abnormal condition is found that the slave does not pull the SDA down, but the level of the I2C bus is jittered due to plugging and unplugging of devices and the like, so that the I2C controller judges that bus arbitration is lost, and waits for a STOP signal on the bus, and thus the I2C controller does not send any data to the bus any more before the I2C controller receives the STOP signal. Such an abnormal situation occurs particularly in multi-host communication.
Therefore, in this embodiment, after determining that the first pin of the target interface is at the high level, the second pin of the target interface is controlled to output the high level signal lasting for the preset first duration, and the first pin of the target interface is controlled to output the low level signal lasting for the preset first duration. Also taking the pin B0 and B1 as examples, control B0 and B1 are both in output mode, and control B0 is high and control B1 is low for the first duration.
The specific value of the first duration can be set according to actual needs, for example, the first duration can be equal to half of the reciprocal of the current communication frequency, which ensures that the I2C controller losing arbitration can correctly receive and recognize the STOP signal. For example, if the current communication frequency is 100khz, the first duration is 5 us.
After the first time length, controlling both B1 and B0 to output high level signals, and continuing for a preset second time length, wherein the specific value of the second time length can be set according to actual needs. After the second length of time, operation in the I2C bus mode may resume. After the I2C bus mode is restored, the arbitration can be resumed to execute the normal communication flow.
In addition, in practical applications, after step S102, the STOP signal may be transmitted according to the above-described embodiment, that is, the method may further include:
after the second pin of the control target interface outputs N clock signals, the second pin of the control target interface outputs a high level signal lasting for a preset first duration, and the first pin of the control target interface outputs a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
In this embodiment, whether SDA is pulled low or I2C controller loses arbitration, the STOP signal is sent, which is advantageous to simplify the program design.
The specific type of each I2C controller on the I2C bus may also be set and selected according to actual needs, for example, in an embodiment of the present invention, the processor corresponding to any I2C controller on the I2C bus may be an ft2000+ processor.
The ft2000+ processor is typically a 64-bit ft2000+ processor having integrated therein 64 autonomously developed ARMv8 instruction set compatible processor cores FTC662 employing a parallel-on-chip system architecture. By integrating the efficient processor core, a large-scale one-dimensional storage architecture based on data affinity and a hierarchical two-dimensional Mesh interconnection network, the storage access delay is optimized, and the advanced computing performance, the access bandwidth and the IO expansion capability are provided. The method can be applied to the field of high-performance and high-throughput servers, such as large business hosts, high-performance server systems, large internet data centers and the like in industries with high requirements on processing capacity and throughput capacity.
By applying the technical scheme provided by the embodiment of the invention, the implementation is not required to be realized by an additional CPLD as in the traditional scheme, the scheme of the invention does not increase the hardware cost and the complexity of hardware design, and the scheme is convenient to deploy. Specifically, the I2C bus and the target interface are multiplexed, so after any I2C controller recognizes that the communication of the I2C bus has a fault, the scheme of the present application switches the I2C bus to the target mode, that is, the serial data line SDA in the I2C bus is used as the first pin of the target interface, and the serial clock line SCL in the I2C bus is used as the second pin of the target interface. At this time, if it is determined that the first pin of the target interface is at a low level, that is, it indicates that the SDA is pulled down, the I2C controller controls the second pin of the target interface to output N clock signals, that is, output N clk signals, of course, N needs to be a positive integer not less than 9, and after the N clock signals are output, the SDA may be pulled up, that is, a communication fault condition caused by the SDA being pulled down in the I2C bus is solved, and then the target mode may be restored to the I2C bus mode. In summary, the scheme of the application effectively realizes communication fault processing of the I2C bus, and does not need to add hardware, which is beneficial to reducing implementation cost of the scheme and reducing complexity of design.
Corresponding to the above method embodiments, the embodiment of the present invention further provides a communication fault handling system of I2C bus, which can be referred to in correspondence with the above. The communication fault handling system of I2C bus can be applied to any I2C controller on I2C bus, and the I2C bus is multiplexed with the target interface, as shown in fig. 4, including:
a multiplexing switching module 401, configured to switch the I2C bus to a target mode to use the serial data line SDA in the I2C bus as a first pin of a target interface and use the serial clock line SCL in the I2C bus as a second pin of the target interface after recognizing that there is a failure in communication of the I2C bus;
a clock signal output module 402, configured to control a second pin of the target interface to output N clock signals after determining that the first pin of the target interface is at a low level; wherein N is a positive integer not less than 9;
and a multiplexing recovery module 403, configured to recover the target mode to the I2C bus mode, so that the first pin of the target interface is used as the serial data line SDA in the I2C bus, and the second pin of the target interface is used as the serial clock line SCL in the I2C bus.
In an embodiment of the present invention, the method may further include:
the first STOP signal simulation module is used for controlling a second pin of the target interface to output a high level signal lasting for a preset first duration after determining that a first pin of the target interface is a high level, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and a STOP signal second analog module, configured to control the first pin and the second pin of the target interface to output high level signals after the first duration, and continue for a preset second duration, and trigger the multiplexing recovery module 403 after the second duration.
In a specific embodiment of the present invention, after the clock signal output module 402 outputs N clock signals at the second pin of the control target interface, the first STOP signal analog module may be further triggered, where the first STOP signal analog module is configured to control the second pin of the control target interface to output a high level signal lasting for a preset first duration, and control the first pin of the control target interface to output a low level signal lasting for the preset first duration;
the STOP signal second analog module is configured to control the first pin and the second pin of the target interface to output high level signals after the first duration, and continue for a preset second duration, and trigger the multiplexing recovery module 403 after the second duration.
In one embodiment of the present invention, the period of the clock signal is T, and T is equal to the inverse of the current communication frequency.
In one embodiment of the invention, the first time period is equal to half the inverse of the current communication frequency.
In a specific embodiment of the present invention, the target interface is a GPIO interface, and the target mode is a GPIO mode;
correspondingly, the clock signal output module 402 is specifically configured to:
setting a first pin of a target interface as an input mode, and judging whether the first pin of the target interface is at a low level or not;
if yes, setting the second pin of the target interface to be in an output mode, and controlling the second pin of the target interface to output N clock signals.
In one embodiment of the present invention, the processor corresponding to any I2C controller on the I2C bus is an ft2000+ processor.
Corresponding to the above method and system embodiments, embodiments of the present invention further provide a server, a communication failure processing system that may include the I2C bus in any of the above embodiments, and reference may be made to the above in correspondence with each other, and a description thereof is not repeated here.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (8)
1. A communication fault processing method of an I2C bus is characterized in that the method is applied to any I2C controller on an I2C bus, and the I2C bus is multiplexed with a target interface, and the method comprises the following steps:
after recognizing that the communication of the I2C bus has a fault, switching the I2C bus to a target mode to use a serial data line (SDA) in the I2C bus as a first pin of the target interface and a Serial Clock Line (SCL) in the I2C bus as a second pin of the target interface;
after the first pin of the target interface is determined to be at a low level, controlling a second pin of the target interface to output N clock signals; wherein N is a positive integer not less than 9;
restoring the target mode to an I2C bus mode to use a first pin of the target interface as a serial data line (SDA) in the I2C bus and a second pin of the target interface as a Serial Clock Line (SCL) in the I2C bus;
further comprising:
after the first pin of the target interface is determined to be at a high level, controlling a second pin of the target interface to output a high level signal lasting for a preset first duration, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
2. The method for handling the communication fault of the I2C bus according to claim 1, further comprising:
after controlling the second pin of the target interface to output N clock signals, controlling the second pin of the target interface to output a high level signal lasting for a preset first duration, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and after the first time length, controlling the first pin and the second pin of the target interface to output high level signals for a preset second time length, and after the second time length, executing the operation of restoring the target mode to the I2C bus mode.
3. The method of claim 1, wherein the period of the clock signal is T, and the T is equal to the inverse of the current communication frequency.
4. The method for handling the communication fault of the I2C bus according to claim 1 or 2, wherein the first time period is equal to half of the reciprocal of the current communication frequency.
5. The communication fault handling method of the I2C bus according to any one of claims 1 to 3, wherein the target interface is a GPIO interface, and the target mode is a GPIO mode;
correspondingly, after determining that the first pin of the target interface is at a low level, controlling the second pin of the target interface to output N clock signals includes:
setting a first pin of the target interface as an input mode, and judging whether the first pin of the target interface is at a low level;
and if so, setting a second pin of the target interface to be in an output mode, and controlling the second pin of the target interface to output N clock signals.
6. The method for processing the communication fault of the I2C bus as claimed in claim 1, wherein the processor corresponding to any I2C controller on the I2C bus is an ft2000+ processor.
7. A communication fault processing system of an I2C bus, which is applied to any I2C controller on an I2C bus, and the I2C bus is multiplexed with a target interface, and comprises:
the multiplexing switching module is used for switching the I2C bus into a target mode to enable a serial data line SDA in the I2C bus to be used as a first pin of the target interface and enable a serial clock line SCL in the I2C bus to be used as a second pin of the target interface after the communication of the I2C bus is identified to have a fault;
the clock signal output module is used for controlling a second pin of the target interface to output N clock signals after the first pin of the target interface is determined to be at a low level; wherein N is a positive integer not less than 9;
a multiplexing recovery module, configured to recover the target mode to an I2C bus mode, so that a first pin of the target interface is used as a serial data line SDA in the I2C bus, and a second pin of the target interface is used as a serial clock line SCL in the I2C bus;
further comprising:
the first STOP signal simulation module is used for controlling a second pin of the target interface to output a high level signal lasting for a preset first duration after determining that a first pin of the target interface is a high level, and controlling the first pin of the target interface to output a low level signal lasting for the preset first duration;
and the STOP signal second simulation module is used for controlling the first pin and the second pin of the target interface to output high level signals after the first time length, lasting for a preset second time length, and executing the operation of restoring the target mode to the I2C bus mode after the second time length.
8. A server, characterized by a communication failure handling system comprising the I2C bus of claim 7.
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