CN111736871A - FPGA chip upgrading method, device and system - Google Patents

FPGA chip upgrading method, device and system Download PDF

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Publication number
CN111736871A
CN111736871A CN202010576202.6A CN202010576202A CN111736871A CN 111736871 A CN111736871 A CN 111736871A CN 202010576202 A CN202010576202 A CN 202010576202A CN 111736871 A CN111736871 A CN 111736871A
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fpga
upgrading
fpga chip
chip
target
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王家祥
刘云峰
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Tianjin Meiteng Technology Co Ltd
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Tianjin Meiteng Technology Co Ltd
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Priority to CN202010576202.6A priority Critical patent/CN111736871A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters 

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  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The application provides an upgrading method, a device and a system of an FPGA chip, the method is applied to an operation and maintenance server, the server is connected with a VPN server, the VPN server is connected with at least one FPGA device, the device comprises a gateway and at least one FPGA board, the board comprises the FPGA chip and an Ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identification distributed to the gateway by the VPN server and establishes connection with the FPGA chip through the Ethernet interface on the FPGA board, the operation and maintenance server stores upgrading programs corresponding to various FPGA chips and responds to an upgrading request aiming at a target FPGA chip; establishing an upgrading link with a target FPGA chip; and sending an upgrading program to the target FPGA chip to complete the upgrading of the FPGA chip, and realizing the remote upgrading of the FPGA chips in the plurality of FPGA devices based on the VPN network.

Description

FPGA chip upgrading method, device and system
Technical Field
The present application relates to the field of FPGA technologies, and in particular, to a method, an apparatus, and a system for upgrading an FPGA chip.
Background
The core of a control system of an intelligent Dry Separator (TDS) is an FPGA board, usually, a plurality of control devices using the FPGA board as core control are arranged in one TDS device, and only one set of codes is needed in the design of each type of FPGA chip. If the upgrading optimization of the FPGA function needs to be realized, the code updating function needs to be applied. Aiming at the currently used circular series chips of ALTERA company, the existing program upgrading solution is to upgrade by matching with a programmer carried by QUARTUS through a JTAG interface.
The upgrading mode needs to disassemble equipment and upgrade the FPGA chip on the FPGA board, so that the operation is complex; in addition, 3-5 FPGA boards are usually arranged in the TDS, the TDS is distributed in provinces of the whole country at present, if the TDS is upgraded one by one and one by one chip, a lot of manpower is consumed, the upgrading efficiency is low, and the rapid optimization of functions cannot be guaranteed, so that a great amount of cost is consumed.
Disclosure of Invention
In view of this, an object of the present application is to provide an upgrade method, apparatus and system for an FPGA chip, which can implement remote upgrade of the FPGA chip in multiple FPGA devices based on a VPN network, improve upgrade efficiency, and reduce upgrade cost.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides an upgrade method for an FPGA chip, where the method is applied to an operation and maintenance server, the operation and maintenance server is connected to a VPN server, the VPN server is connected to at least one FPGA device, the FPGA device includes a gateway and at least one FPGA board, the FPGA board includes an FPGA chip and an ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier allocated to the gateway by the VPN server, and establishes a connection with the FPGA chip through the ethernet interface on the FPGA board, and the operation and maintenance server pre-stores upgrade programs corresponding to a plurality of FPGA chips, and the method includes: responding an upgrading request aiming at a target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip; establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip; and sending an upgrading program to the target FPGA chip through the upgrading link so that the target FPGA chip calls the upgrading program to complete the upgrading of the FPGA chip.
Further, the step of establishing an upgrade link with the target FPGA chip based on the identifier of the target FPGA chip includes: and sending a data frame for establishing the link to the target FPGA chip based on the identification of the target FPGA chip so as to enable the target FPGA chip to establish an upgrading link with the operation and maintenance server based on the data frame.
In a second aspect, an embodiment of the present application provides a method for upgrading an FPGA chip, where the method is applied to the FPGA chip, and the FPGA chip establishes a connection with an operation and maintenance server through an ethernet interface on an FPGA board where the FPGA chip is located, a gateway in an FPGA device to which the FPGA chip belongs, and a VPN server connected to the FPGA device, and the method includes: establishing an upgrading link with an operation and maintenance server; receiving an upgrading program sent by an operation and maintenance server based on an upgrading link; and calling an upgrading program to upgrade the FPGA chip.
Further, after the step of receiving the upgrade program sent by the operation and maintenance server based on the upgrade link, the method further includes: the received upgrade program is stored in the memory.
In a third aspect, an embodiment of the present application provides a method and an apparatus for upgrading an FPGA chip, where the apparatus is applied to an operation and maintenance server, the operation and maintenance server is connected to a VPN server, the VPN server is connected to at least one FPGA device, the FPGA device includes a gateway and at least one FPGA board, the FPGA board includes an FPGA chip and an ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier allocated to the gateway by the VPN server, and establishes a connection with the FPGA chip through the ethernet interface on the FPGA board, and the operation and maintenance server prestores upgrading programs corresponding to a plurality of FPGA chips, and the apparatus includes: the request response module is used for responding an upgrading request aiming at the target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip; the link establishing module is used for establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip; and the program sending module is used for sending the upgrading program to the target FPGA chip through the upgrading link so as to enable the target FPGA chip to call the upgrading program and finish the upgrading of the FPGA chip.
In a fourth aspect, an embodiment of the present application provides an apparatus for upgrading an FPGA chip, where the apparatus is applied to the FPGA chip, the FPGA chip establishes a connection with an operation and maintenance server through an ethernet interface on an FPGA board where the FPGA chip is located, a gateway in an FPGA device to which the FPGA chip belongs, and a VPN server connected to the FPGA device, and the apparatus includes: the link establishing module is used for establishing an upgrading link with the operation and maintenance server; the program receiving module is used for receiving the upgrading program sent by the operation and maintenance server based on the upgrading link; and the chip upgrading module is used for calling an upgrading program to upgrade the FPGA chip.
In a fifth aspect, an embodiment of the present application provides an upgrade system for an FPGA chip, where the system includes an operation and maintenance server, a VPN server, and at least one FPGA device, where the FPGA device includes a gateway and at least one FPGA board, the FPGA board includes an FPGA chip, an ethernet interface, and a memory, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier allocated to the gateway by the VPN server, and establishes a connection with the FPGA chip through the ethernet interface on the FPGA board, and the operation and maintenance server prestores upgrade programs corresponding to a plurality of FPGA chips respectively; the operation and maintenance server is used for executing the method in the first aspect; the FPGA chip is configured to perform the method of the second aspect.
Further, the FPGA device is a TDS intelligent dry separator.
In a sixth aspect, an embodiment of the present application provides an electronic device, including: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the steps of the method according to the first or second aspect.
In a seventh aspect, this application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the method in the first aspect or the second aspect.
The method for upgrading the FPGA chip is applied to an operation and maintenance server, the operation and maintenance server is connected with a VPN server, the VPN server is connected with at least one FPGA device, the FPGA device comprises a gateway and at least one FPGA board, the FPGA board comprises an FPGA chip and an Ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identification distributed to the gateway by the VPN server and establishes connection with the FPGA chip through the Ethernet interface on the FPGA board, upgrading programs respectively corresponding to various FPGA chips are prestored in the operation and maintenance server, and the operation and maintenance server responds to an upgrading request aiming at a target FPGA chip under the condition that the operation and maintenance server and the FPGA chip establish connection through a VPN network and the network chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip; then establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip; and finally, sending an upgrading program to the target FPGA chip through an upgrading link so that the target FPGA chip calls the upgrading program to complete the upgrading of the FPGA chip. By the method, the FPGA chips in the FPGA devices can be remotely upgraded based on the VPN network, the upgrading efficiency is improved, and the upgrading cost is reduced.
Additional features and advantages of the disclosure will be set forth in the description which follows, or in part may be learned by the practice of the above-described techniques of the disclosure, or may be learned by practice of the disclosure.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a block diagram illustrating an upgrade system of an FPGA chip provided in an embodiment of the present application;
fig. 2 shows a flowchart of an upgrade method for an FPGA chip according to an embodiment of the present application;
fig. 3 is a flowchart illustrating an upgrade method for an FPGA chip according to an embodiment of the present application;
fig. 4 is a block diagram illustrating an upgrade apparatus for an FPGA chip according to an embodiment of the present disclosure;
FIG. 5 is a block diagram of an apparatus for upgrading an FPGA chip according to an embodiment of the present disclosure;
fig. 6 shows a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Considering that the existing FPGA chip upgrading mode needs to disassemble equipment, the FPGA chip on the FPGA board is upgraded, and the operation is complex; in addition, 3-5 FPGA boards are usually arranged in the TDS, the TDS is distributed in provinces of the whole country at present, if the TDS is upgraded one by one and one by one chip, a lot of manpower is consumed, the upgrading efficiency is low, and the rapid optimization of functions cannot be guaranteed, so that a great amount of cost is consumed. To improve this problem, embodiments of the present application provide an upgrade method, an upgrade device, and an upgrade system for an FPGA chip, and for convenience of understanding, first, embodiments of the system of the present application are described in detail below.
Referring to fig. 1, a block diagram of an upgrade system for an FPGA chip provided in an embodiment of the present application is shown, where the system includes an operation and maintenance server, a VPN server, and at least one FPGA device, where the FPGA device includes a gateway and at least one FPGA board, the FPGA board includes an FPGA chip, an ethernet interface, and a memory, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier allocated to the gateway by the VPN server, and establishes a connection with the FPGA chip through the ethernet interface on the FPGA board, and the operation and maintenance server prestores upgrade programs corresponding to multiple FPGA chips respectively.
Above-mentioned FPGA equipment can be the multiple equipment that loads the FPGA board, for example TDS intelligence dry separation machine, and in the system that this application embodiment provided, through setting up long-range VPN network, the FPGA upgrading scheme based on gigabit Ethernet combines, can be with the FPGA board in hundreds of TDSs through long-range VPN network connection to a LAN to realize the code and update. In the embodiment of the application, the interaction process of the operation and maintenance server and the FPGA chip refers to the following method embodiments.
Fig. 2 is a flowchart of an upgrade method for an FPGA chip according to an embodiment of the present application, where the method is applied to an operation and maintenance server, and a plurality of upgrade programs corresponding to the FPGA chips are prestored in the operation and maintenance server, and the method includes the following steps:
step S202, responding to an upgrading request aiming at a target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip;
in this embodiment, in a power-on state of the FPGA device, the FPGA chips on the FPGA boards in the FPGA device are already connected to the local area network through the ethernet interfaces on the FPGA boards, and then are further connected to the VPN server through the gateways in the FPGA-board device, so as to establish connection with the operation and maintenance server.
In practical application, an operator can initiate an upgrade request at a client of the operation and maintenance server, for example, can select an FPGA chip to be upgraded, that is, a target FPGA chip and an upgrade program corresponding to the target FPGA chip, which are usually binary files, and then click an upgrade option, at this time, the operation and maintenance server will respond to the upgrade request for the target FPGA chip.
Here, the target FPGA chip may be multiple or one, and the identifier of the target FPGA chip may include: the port number of the Ethernet interface on the FPGA board where the target FPGA chip is located and the IP number of the FPGA device to which the FPGA board belongs. When the gateway requests to connect the VPN server, the VPN server can allocate an IP number to the TDS, and the operation and maintenance server can access the gateway through the IP number, then access the local area network of the TDS, then be connected to the gigabit Ethernet interface of the FPGA board through the port number, and further establish connection with the FPGA chip on the FPGA. The operation and maintenance server can make sure to which FPGA chip the upgrade data should be sent through the identification of the target FPGA chip so as to upgrade the FPGA chip.
And step S204, establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip.
Specifically, based on the identifier of the target FPGA chip, a data frame for establishing a link is sent to the target FPGA chip, that is, a protocol for establishing an upgrade link is sent, so that the target FPGA chip establishes the upgrade link with the operation and maintenance server based on the data frame, which facilitates data transmission between the two parties.
And step S206, sending an upgrading program to the target FPGA chip through the upgrading link so that the target FPGA chip calls the upgrading program to complete the upgrading of the FPGA chip.
After the upgrade link is established, the operation and maintenance server sends the corresponding upgrade program to the target FPGA chip, and after the target FPGA chip receives the upgrade program, the program is called to complete the upgrade.
It should be noted that, an operator may select a certain FPGA chip in a certain TDS to perform upgrading, or may select a plurality of FPGA chips in a certain TDS to perform upgrading.
In the method provided by this embodiment, each FPGA device, in a powered-on state, may connect the FPGA chip on each FPGA board therein to the local area network through the ethernet interface, and then further connect to the VPN server through the gateway in the device, thereby establishing a connection with the operation and maintenance server. Under the condition of establishing connection, the operation and maintenance server can respond to an upgrade request aiming at the target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip; then establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip; and finally, sending an upgrading program to the target FPGA chip through an upgrading link so that the target FPGA chip calls the upgrading program to complete the upgrading of the FPGA chip. By the method, the FPGA chips in the FPGA devices can be remotely upgraded based on the VPN network, the upgrading efficiency is improved, and the upgrading cost is reduced.
According to the method and the system, the FPGA program in each FPGA device is remotely upgraded on the operation and maintenance server by building the VPN network, and hundreds or even thousands of FPGA chips are upgraded in a few minutes, so that the efficiency of program upgrading is greatly improved. For example, after the TDS is powered on, the interior gateway can initiate a request through the Internet to actively connect with the VPN server, the VPN server can distribute a network IP to each TDS after receiving the request, the operation and maintenance server can upgrade the related FPGA chip through different port numbers through the network IP of each TDS, only the TDS equipment is needed to be connected with the Internet, and the upgrading efficiency is obviously improved.
Based on the above method embodiment, the present application embodiment also provides an upgrade method for an FPGA chip, where the method is applied to the FPGA chip, and the FPGA chip establishes a connection with an operation and maintenance server through an ethernet interface on an FPGA board where the FPGA chip is located, a gateway in an FPGA device to which the FPGA chip belongs, and a VPN server connected to the FPGA device. Referring to fig. 3, the method comprises the steps of:
step S302, establishing an upgrading link with an operation and maintenance server;
step S304, receiving an upgrading program sent by the operation and maintenance server based on an upgrading link;
after the step of receiving the upgrade program sent by the operation and maintenance server based on the upgrade link, the received upgrade program may also be stored in the memory.
And step S306, calling an upgrading program to upgrade the FPGA chip.
The process of establishing the upgrade link is the same as the method embodiment, and is not described herein again. After receiving the upgrade program, the FPGA chip may call the upgrade program, or execute the program, to complete the upgrade of the function.
The FPGA chip is upgraded through the gigabit Ethernet interface, namely a program does not pass through a JTAG (joint test action group), only an operation and maintenance server sends data to the FPGA chip, the FPGA chip writes the data into a FLASH memory, and after the power is off and on, the program is automatically loaded into the FPGA chip, namely the program in the FPGA chip is updated through only one network interface, so that the online upgrading function is necessary for a mature product.
The FPGA chip used in the embodiment of the application is a CYCLONE series chip of an altera company, and two Ipcores under the altera are needed in the process of receiving an upgrade program and completing upgrade: the method comprises an Altera Remote Update and an Altera ASMI Parallel, wherein the Altera Remote Update completes the setting of a Remote Update function register (such as a starting address, a watchdog and an enabling), and the Altera ASMI Parallel completes the updating of FLASH program data to realize the reading and writing of FLASH data. And electrifying the FPGA chip again to finish upgrading.
Compared with the prior art, when the FPGA equipment is upgraded by combining the gigabit Ethernet FPGA upgrading scheme carrying the VPN network, the FPGA chips of all the FPGA equipment can be upgraded remotely without opening the shell of the FPGA equipment or even on the site of the equipment, and the upgrading is more convenient.
In the method embodiment of the operation and maintenance server side, the embodiment of the present application further provides a device for upgrading an FPGA chip, the device is applied to an operation and maintenance server, the operation and maintenance server is connected to a VPN server, the VPN server is connected to at least one FPGA device, the FPGA device includes a gateway and at least one FPGA board, the FPGA board includes an FPGA chip and an ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier allocated to the gateway by the VPN server, and establishes a connection with the FPGA chip through the ethernet interface on the FPGA board, the operation and maintenance server prestores upgrading programs corresponding to a plurality of FPGA chips, as shown in fig. 4, and the device includes:
a request response module 42, configured to respond to an upgrade request for a target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip;
a link establishing module 44, configured to establish an upgrade link with a target FPGA chip based on an identifier of the target FPGA chip;
and the program sending module 46 is configured to send an upgrade program to the target FPGA chip through the upgrade link, so that the target FPGA chip calls the upgrade program to complete the upgrade of the FPGA chip.
In the method embodiment of the FPGA chip side, the present application embodiment further provides an apparatus for upgrading an FPGA chip, where the apparatus is applied to the FPGA chip, and the FPGA chip establishes a connection with an operation and maintenance server through an ethernet interface on an FPGA board where the FPGA chip is located, a gateway in an FPGA device to which the FPGA chip belongs, and a VPN server connected to the FPGA device, as shown in fig. 5, the apparatus includes:
the link establishing module 52 is used for establishing an upgrade link with the operation and maintenance server;
a program receiving module 54, configured to receive an upgrade program sent by the operation and maintenance server based on the upgrade link;
and the chip upgrading module 56 is used for calling an upgrading program to upgrade the FPGA chip.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
An example electronic device for implementing the method, apparatus and system for upgrading an FPGA chip of embodiments of the present application is described with reference to fig. 6.
Fig. 6 is a schematic structural diagram of an electronic device, where the electronic device includes a processor 61 and a memory 60, where the memory 60 stores computer-executable instructions capable of being executed by the processor 61, and the processor 61 executes the computer-executable instructions to implement the method provided by the embodiment in the present application.
In the embodiment shown in fig. 6, the electronic chip further comprises a bus 62 and a communication interface 63, wherein the processor 61, the communication interface 63 and the memory 60 are connected by the bus 62.
The Memory 60 may include a high-speed Random Access Memory (RAM) and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 63 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used. The bus 62 may be an ISA (Industry standard Architecture) bus, a PCI (Peripheral component interconnect) bus, an EISA (Extended Industry standard Architecture) bus, or the like. The bus 62 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 6, but that does not indicate only one bus or one type of bus.
The processor 61 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 61. The Processor 61 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and the processor 61 reads information in the memory and, in combination with its hardware, performs the steps of the method of the following embodiments.
Exemplary electronic devices for implementing the method and apparatus for upgrading an FPGA chip according to the embodiments of the present application may be implemented on smart terminals such as a monitoring device, a smart phone, a tablet computer, a computer, and the like.
The present embodiment also provides a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program performs the steps of the method provided by the above-mentioned method embodiment.
The computer program product of the method and the device for upgrading the FPGA chip provided in the embodiments of the present application includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiments, and specific implementation may refer to the method embodiments, and is not described herein again.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer chip (which may be a personal computer, a server, or a network chip) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. The method for upgrading the FPGA chip is applied to an operation and maintenance server, the operation and maintenance server is connected with a VPN (virtual private network) server, the VPN server is connected with at least one FPGA device, the FPGA device comprises a gateway and at least one FPGA board, the FPGA board comprises the FPGA chip and an Ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP (Internet protocol) identifier distributed to the gateway by the VPN server and establishes connection with the FPGA chip through the Ethernet interface on the FPGA board, and various upgrading programs respectively corresponding to the FPGA chips are prestored in the operation and maintenance server, and the method comprises the following steps:
responding an upgrading request aiming at a target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip;
establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip;
and sending the upgrading program to the target FPGA chip through the upgrading link so that the target FPGA chip calls the upgrading program to complete the upgrading of the FPGA chip.
2. The method of claim 1, wherein the step of establishing an upgrade link with the target FPGA chip based on the identification of the target FPGA chip comprises:
and sending a data frame for establishing a link to the target FPGA chip based on the identification of the target FPGA chip so as to enable the target FPGA chip to establish an upgrading link with the operation and maintenance server based on the data frame.
3. An FPGA chip upgrading method is characterized in that the method is applied to an FPGA chip, the FPGA chip is connected with an operation and maintenance server through an Ethernet interface on an FPGA board where the FPGA chip is located, a gateway in FPGA equipment where the FPGA chip belongs, and a VPN server connected with the FPGA equipment, and the method comprises the following steps:
establishing an upgrading link with the operation and maintenance server;
receiving an upgrading program sent by the operation and maintenance server based on the upgrading link;
and calling the upgrading program to upgrade the FPGA chip.
4. The method of claim 3, wherein after the step of receiving the upgrade program sent by the operation and maintenance server based on the upgrade link, the method further comprises:
storing the received upgrade program in a memory.
5. The device is characterized in that the device is applied to an operation and maintenance server, the operation and maintenance server is connected with a VPN (virtual private network) server, the VPN server is connected with at least one FPGA (field programmable gate array) device, the FPGA device comprises a gateway and at least one FPGA board, the FPGA board comprises an FPGA chip and an Ethernet interface, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP (Internet protocol) identifier distributed to the gateway by the VPN server and establishes connection with the FPGA chip through the Ethernet interface on the FPGA board, and the operation and maintenance server is prestored with upgrading programs corresponding to various FPGA chips respectively, and the device comprises:
the request response module is used for responding an upgrading request aiming at the target FPGA chip; the upgrading request carries an identification of the target FPGA chip and an upgrading program corresponding to the target FPGA chip;
the link establishing module is used for establishing an upgrading link with the target FPGA chip based on the identification of the target FPGA chip;
and the program sending module is used for sending the upgrading program to the target FPGA chip through the upgrading link so as to enable the target FPGA chip to call the upgrading program and finish the upgrading of the FPGA chip.
6. The utility model provides an upgrading device of FPGA chip, its characterized in that, the device is applied to the FPGA chip, the FPGA chip is through the ethernet interface on its FPGA board, and the gateway in the FPGA equipment that belongs to, and with the VPN server of FPGA equipment connection, establish the connection with fortune dimension server, the device includes:
the link establishing module is used for establishing an upgrading link with the operation and maintenance server;
the program receiving module is used for receiving the upgrading program sent by the operation and maintenance server based on the upgrading link;
and the chip upgrading module is used for calling the upgrading program to upgrade the FPGA chip.
7. The FPGA chip upgrading system is characterized by comprising an operation and maintenance server, a VPN server and at least one FPGA device, wherein the FPGA device comprises a gateway and at least one FPGA board, the FPGA board comprises an FPGA chip, an Ethernet interface and a memory, the operation and maintenance server accesses a local area network of the FPGA device corresponding to the gateway through an IP identifier distributed to the gateway by the VPN server and establishes connection with the FPGA chip through the Ethernet interface on the FPGA board, and various upgrading programs respectively corresponding to the FPGA chips are prestored in the operation and maintenance server;
the operation and maintenance server is used for executing the method of claim 1 or 2;
the FPGA chip is used for executing the method of claim 3 or 4.
8. The system of claim 7, wherein the FPGA device is a TDS intelligent dry separator.
9. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the steps of the method according to any one of claims 1 to 4.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of the claims 1 to 4.
CN202010576202.6A 2020-06-22 2020-06-22 FPGA chip upgrading method, device and system Pending CN111736871A (en)

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