CN111726104A

CN111726104A - Decision feedback equalizer

Info

Publication number: CN111726104A
Application number: CN201910222504.0A
Authority: CN
Inventors: 刘熙恩; 闵绍恩; 谢依峻
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-03-22
Filing date: 2019-03-22
Publication date: 2020-09-29

Abstract

The invention discloses a decision feedback equalizer, which is provided with a first path and a second path. The first path includes a first sampling circuit for generating a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and a first latch circuit for generating a first digital signal according to an output of the first sampling circuit. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal, and the second latch circuit is used for generating a second digital signal according to the output of the second sampling circuit.

Description

Decision feedback equalizer

Technical Field

The invention relates to a decision feedback equalizer.

Background

A Decision Feedback Equalizer (DFE) is a technique often used at a receiving end of a high-speed cable transmission system to compensate channel loss or channel reflection (channel reflection) of a transmission signal due to various transmission processes, and its main operation principle is to eliminate Inter-symbol interference (ISI) that is known to affect a following signal through a set of tap parameters (tap coefficients) obtained by an adaptive algorithm (adaptation) and a currently received digital signal. In analog circuits of high speed decision feedback equalizers, the most difficult part to implement is the feedback of the first tap (first tap), since in principle the delay of the feedback signal through the sampler (sampler), the propagation delay of the feedback path and the summer delay have to be prepared before the next data, especially at higher speeds the timing constraints are tighter.

To solve this problem, some patent technologies (for example, US7869498 and US8477833) and papers propose related decision feedback equalization circuit architectures, however, these technologies have temperature drift problems in the design of the junction parameters, and therefore, the junction parameters must be adjusted depending on background correction (background calibration), thereby increasing the instability and complexity of the circuit.

Disclosure of Invention

Therefore, one of the objectives of the present invention is to provide a decision feedback equalizer having the advantages of high speed, low temperature effect, low power consumption, no need of background correction to adjust the tap parameter …, etc., so as to solve the problems in the prior art.

In one embodiment of the present invention, a decision feedback equalizer is disclosed having a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit is used for generating a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal, and the first latch circuit is used for generating a first digital signal according to the first setting signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second setting signal and the second resetting signal according to the input signal, the first setting signal and the first resetting signal, and the second latch circuit is used for generating a second digital signal according to the second setting signal and the second resetting signal.

Drawings

Fig. 1 is a schematic diagram of a decision feedback equalizer according to an embodiment of the invention.

Fig. 2 is a timing diagram of a plurality of signals within a decision feedback equalizer.

Fig. 3 is a circuit architecture diagram of a first path and a second path according to an embodiment of the invention.

FIG. 4 is a diagram of a sampling circuit according to a first embodiment of the present invention.

FIG. 5 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 4.

FIG. 6 is a diagram of a sampling circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 6.

Description of the symbols

100 decision feedback equalizer

102. 112, 122 summing circuit

108 multiplexer

110 first path

114. 124, 314, 324 sampling circuit

120 second path

316. 326 latch circuit

410. 610 sense amplifier

412. 414, 612, 614 inverters

420. 620 regulating circuit

CK. CKB clock signal

D _ odd first digital signal

D _ even second digital signal

Dout output digital signal

M1-M13 transistor

S _ odd first setting signal

S _ even second setting signal

R _ odd first reset signal

R _ even second reset signal

Vin input signal

Vin ', Vin ' +, Vin ' -adjusted input signal

Feedback signals of VFB1_ even, VFB1_ odd and VFB2

Voltage of Vh1

VCM common mode Voltage

Detailed Description

Fig. 1 is a diagram of a decision feedback equalizer 100 according to an embodiment of the invention. As shown in fig. 1, the dfe 100 includes a summing circuit 102, a first path 110, a second path 120, and a multiplexer 108, wherein the first path 110 includes a summing circuit 112 and a sampling circuit 114, and the second path 120 includes a summing circuit 122 and a sampling circuit 124.

The dfe 100 shown in fig. 1 employs two paths and half-rate (half-rate) multiplexing to achieve the purpose of reducing the operation delay. Specifically, referring to the timing diagram of fig. 2, in the operation of the dfe 100, the summing circuit 102 subtracts a feedback signal VFB2 from the input signal Vin to generate an adjusted input signal Vin ', and then the summing circuit 112 in the first path 110 subtracts a feedback signal VFB1_ even from the adjusted input signal Vin' and samples the signal with a clock signal CK through the sampling circuit 114 to generate a first digital signal D _ odd; and the summing circuit 122 in the second path 120 subtracts a feedback signal VFB1_ odd from the adjusted input signal Vin' and samples the subtracted signal with a clock signal CKB by the sampling circuit 124 to generate a second digital signal D _ even. Then, the multiplexer 108 outputs the first digital signal D _ odd and the second digital signal D _ even alternately as the output digital signal Dout of the decision feedback equalizer 100 through the control of the clock signal CKB. For example, assuming that the input signal Vin sequentially includes the bit A, B, C, D, E, the clock signals CK and CKB have a frequency half of the frequency of the input signal Vin, the first digital signal D _ odd generated by the sampling circuit 114 includes A, C, E, and the second digital signal D _ even generated by the sampling circuit 124 includes B, D, i.e., the first digital signal D _ odd is used as the odd bits of the output digital signal Dout, and the second digital signal D _ even is used as the even bits of the output digital signal Dout.

In fig. 1, the feedback signal VFB2 is generated by adjusting the output digital signal Dout according to the tap parameter h2, the feedback signal VFB1_ even is generated by adjusting the second digital signal D _ even according to the tap parameter h1, and the feedback signal VFB1_ odd is generated by adjusting the first digital signal D _ odd according to the tap parameter h 1. As described in the prior art, in the high-speed decision feedback equalizer, the most difficult part to implement is the feedback of the first tap (i.e., the related operations of the feedback signal VFB1_ even and the feedback signal VFB1_ odd), so in order to reduce the feedback delay, the present invention embeds the feedback function in the sampling circuit, and the specific implementation manner thereof is as follows.

Fig. 3 is a circuit architecture diagram of the first path 110 and the second path 120 according to an embodiment of the invention. In fig. 3, the first path 110 includes a sampling circuit 314 and a latch circuit (SR latch) 316, wherein the sampling circuit 314 is a sampling circuit with a feedback function embedded therein, i.e., the sampling circuit 314 includes part of the functions of the summing circuit 112, the tap parameter h1 and the sampling circuit 114 shown in fig. 1; similarly, the second path 120 includes a sampling circuit 324 and a latch circuit 326, wherein the sampling circuit 324 is a sampling circuit with built-in feedback function, i.e. the sampling circuit 324 includes part of the functions of the summing circuit 122, the tap parameter h1 and the sampling circuit 124 shown in fig. 1. In the embodiment shown in fig. 3, the sampling circuit 314 generates a first setting signal S _ odd and a first reset signal R _ odd according to the adjusted input signal Vin', a second setting signal S _ even and a second reset signal R _ even, and the latch circuit 316 generates a first digital signal D _ odd according to the first setting signal S _ odd and the first reset signal R _ odd; similarly, the sampling circuit 324 generates the second setting signal S _ even and the second reset signal R _ even according to the adjusted input signal Vin', the first setting signal S _ odd, and the first reset signal R _ odd, and the latch circuit 326 generates the second digital signal D _ even according to the second setting signal S _ even and the second reset signal R _ even. In fig. 3, the first setting signal S _ odd and the first reset signal R _ odd may correspond to the feedback signal VFB1_ odd shown in fig. 1, and the second setting signal S _ even and the second reset signal R _ even may correspond to the feedback signal VFB1_ even shown in fig. 1.

Fig. 4 is a schematic diagram of a sampling circuit 314 according to a first embodiment of the invention. As shown in FIG. 4, the sampling circuit 314 comprises a sense amplifier 410 and an adjusting circuit 420, wherein the sense amplifier 410 comprises transistors M1 and M2 for receiving the adjusted input signal Vin ' (including the differential signals Vin ' +, Vin ' -), a transistor M3 as a sense amplifying switch, a plurality of transistors M4-M9 coupled to the supply voltage VDD, and two

inverters

412 and 414; the adjusting circuit 420 includes two transistors M10 and M11 as a first differential amplifier, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW 2. In the present embodiment, the transistors M1 and M2 are used for receiving the adjusted input signal Vin ' to generate the amplified input signal at the nodes N1 and N2, and the drains of the transistors M4 and M5 are used for outputting the signals S ' and R ', wherein the signals S ' and R ' are respectively operated by the

inverters

412 and 414 to generate the first setting signal S _ odd and the first reset signal R _ odd. The drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier. In addition, in the adjusting circuit 420, the first differential amplifier (i.e., the transistors M10, M11) is connected to the transistor M3 as a sense amplifying switch through the switch SW1, wherein the switch SW1 is controlled by the second setting signal S _ even, i.e., the first differential amplifier is selectively enabled according to the second setting signal S _ even to generate a first adjusting signal to the terminals N1, N2 according to a differential voltage signal (VCM + Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the component corresponding to the voltage Vh1 is added or subtracted to the terminals N1, N2); in addition, the second differential amplifier (i.e., the transistors M12, M13) is connected to the transistor M3 as a sense amplifier switch through a switch SW2, wherein the switch SW2 is controlled by the second reset signal R _ even, i.e., the second differential amplifier is selectively enabled according to the second reset signal R _ even to generate a second adjustment signal to the terminals N1, N2 according to a differential voltage signal (VCM + Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the component corresponding to the voltage Vh1 is added or subtracted to the terminals N1, N2). The source of the transistor of the first differential amplifier is connected to the sense amplifying switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifying switch through a second switch, wherein the first switch and the second switch are controlled by the second setting signal and the second resetting signal respectively.

The architecture of the sampling circuit 324 is similar to that of the sampling circuit 314 shown in FIG. 4, except that the output of the sampling circuit 410 needs to be changed from the first set signal S _ odd and the first reset signal R _ odd to the second set signal S _ even and the second reset signal R _ even, and the switches SW1 and SW2 are respectively controlled by the first set signal S _ odd and the first reset signal R _ odd. Since a person skilled in the art can understand how to implement the sampling circuit 324 after reading the above embodiments, the related details are not described in detail.

As shown in the circuit architectures of fig. 3 and 4, since the first setting signal S _ odd and the first resetting signal R _ odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324, and similarly the second setting signal S _ even and the second resetting signal R _ even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, and the overall circuit delay is almost the same as the amplification time of the sense amplifier 410 and the delay time of the

inverters

412 and 414, the feedback delay problem in the conventional architecture can be effectively reduced. As illustrated in the timing diagram of fig. 5, after the sampling circuit 324 generates the second setting signal S _ even and the second reset signal R _ even to determine the bit B, the second setting signal S _ even and the second reset signal R _ even can be rapidly inputted to the adjusting circuit 420 in the sampling circuit 314 of fig. 4, so that the sampling circuit 314 can generate the first setting signal S _ odd and the first reset signal R _ odd to determine the bit C.

In this example, the common-mode voltage VCM of the differential signal received by the first differential amplifier (i.e., the transistors M10, M11) and the second differential amplifier (i.e., the transistors M12, M13) in the adjusting circuit 420 is the same as the common-mode voltage of the adjusted input signal Vin ' (including the differential signals Vin ' +, Vin ' -), so that the sense amplifier 410 and the adjusting circuit 420 have the same/similar variation under the different process, temperature, and voltage (voltage), i.e., the adjusting signal generated by the adjusting circuit 420 can actually have the voltage Vh1 without being varied with the temperature. On the other hand, since the voltage Vh1 does not vary with temperature, the adaptive algorithm of the connector parameter h1 can be executed without background when the electronic device is powered on, thereby indirectly reducing the system complexity.

FIG. 6 is a diagram of a sampling circuit 314 according to a second embodiment of the invention. As shown in FIG. 6, the sampling circuit 314 comprises a sense amplifier 610 and an adjusting circuit 620, wherein the sense amplifier 610 comprises transistors M1 and M2 for receiving the adjusted input signal Vin ' (including the differential signals Vin ' +, Vin ' -), a transistor M3 as a sense amplifying switch, a plurality of transistors M4-M9 coupled to the supply voltage VDD, and two

inverters

612 and 614; the adjusting circuit 620 includes two transistors M10 and M11 as a first differential amplifier, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW 2. In the present embodiment, the transistors M1 and M2 are used for receiving the adjusted input signal Vin ' to generate the amplified input signal at the nodes N1 and N2, and the drains of the transistors M4 and M5 are used for outputting the signals S ' and R ', wherein the signals S ' and R ' are respectively operated by the

inverters

612 and 614 to generate the first setting signal S _ odd and the first reset signal R _ odd. In addition, in the adjusting circuit 620, the first differential amplifier (i.e., the transistors M10, M11) is connected to the ground voltage through the switch SW1, wherein the switch SW1 is controlled by the second setting signal S _ even AND the clock signal CK (e.g., an AND gate (AND gate, output after receiving the second setting signal S _ even AND the clock signal CK)), that is, the first differential amplifier is selectively enabled according to the second setting signal S _ even AND the clock signal, so as to generate a first adjusting signal to the terminals N1, N2 according to a differential voltage signal (VCM + Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the components corresponding to the voltages Vh1 are added or subtracted at the terminals N1, N2); in addition, the second differential amplifier (i.e., the transistors M12, M13) is connected to the ground voltage through the switch SW2, wherein the switch SW2 is controlled by the second reset signal R _ even AND the clock signal CK (e.g., the output of the AND gate (AND gate) after receiving the second reset signal R _ even AND the clock signal CK), i.e., the second differential amplifier is selectively enabled according to the second reset signal R _ even to generate a second adjustment signal to the terminals N1, N2 according to a differential voltage signal (VCM + Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the component corresponding to the voltage Vh1 is added or subtracted to the terminals N1, N2). The source of the transistor of the first differential amplifier is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch is controlled by the second setting signal and the clock signal at the same time, and the second switch is controlled by the second resetting signal and the clock signal at the same time.

The architecture of the sampling circuit 324 is similar to that of the sampling circuit 314 shown in FIG. 6, except that the output of the sampling circuit 410 needs to be changed from the first set signal S _ odd and the first reset signal R _ odd to the second set signal S _ even and the second reset signal R _ even, and the switches SW1 and SW2 are respectively controlled by the first set signal S _ odd and the first reset signal R _ odd. Since a person skilled in the art can understand how to implement the sampling circuit 324 after reading the above embodiments, the related details are not described in detail.

As shown in the circuit architectures of fig. 3 and fig. 6, since the first setting signal S _ odd and the first resetting signal R _ odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324, and similarly the second setting signal S _ even and the second resetting signal R _ even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, and the overall circuit delay is almost the same as the amplification time of the sense amplifier 410 and the delay time of the

inverters

412 and 414, the feedback delay problem in the conventional architecture can be effectively reduced. As illustrated in the timing diagram of fig. 7, after the sampling circuit 324 generates the second setting signal S _ even and the second reset signal R _ even to determine the bit B, the second setting signal S _ even and the second reset signal R _ even can be rapidly inputted to the adjusting circuit 420 in the sampling circuit 314 of fig. 4, so that the sampling circuit 314 can generate the first setting signal S _ odd and the first reset signal R _ odd to determine the bit C.

In this example, the common-mode voltage VCM of the differential signal received by the first differential amplifier (i.e., the transistors M10, M11) and the second differential amplifier (i.e., the transistors M12, M13) in the adjusting circuit 620 is the same as the common-mode voltage VCM of the adjusted input signal Vin ' (including the differential signals Vin ' +, Vin ' -), so that the sensing amplifier 610 and the adjusting circuit 620 have the same/similar variation under the different process, temperature, and voltage variations, i.e., the adjusting signal generated by the adjusting circuit 620 can actually reflect the voltage Vh1 without variation with temperature. On the other hand, since the voltage Vh1 does not vary with temperature, the adaptive algorithm of the connector parameter h1 can be executed without background when the electronic device is powered on, which indirectly reduces the complexity of the system.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A decision feedback equalizer comprising:

a first path comprising:

a first sampling circuit for generating a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal; and

a first latch circuit, coupled to the sampling circuit, for generating a first digital signal according to the first set signal and the first reset signal; and

a second path comprising:

a second sampling circuit for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal; and

a second latch circuit, coupled to the second sampling circuit, for generating a second digital signal according to the second setting signal and the second reset signal;

wherein the first sampling circuit comprises:

a sense amplifier for receiving the input signal and generating an amplified input signal at an end; and

an adjusting circuit, coupled to the terminal of the sense amplifier, for generating an adjusting signal to the terminal according to the second setting signal and the second resetting signal to adjust the voltage level of the amplified input signal;

wherein the first setting signal and the first reset signal are generated according to the amplified input signal.

2. The dfe of claim 1, wherein the first digital signal is used as odd bits of an output digital signal of the dfe, and the second digital signal is used as even bits of the output digital signal of the dfe.

3. The dfe of claim 1, wherein the adjusting circuit comprises:

a first differential amplifier selectively enabled according to the second setting signal to generate a first adjusting signal to the terminal according to a first differential voltage signal to adjust the voltage level of the amplified input signal; and

a second differential amplifier selectively enabled according to the second reset signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal.

4. The dfe of claim 3, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage.

5. The dfe of claim 3, wherein the sense amplifier comprises a sense amplifier switch controlled by a clock signal to determine whether the sense amplifier switch is enabled or not, the source of the transistor of the first differential amplifier is connected to the sense amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifier switch through a second switch, wherein the first switch and the second switch are controlled by the second setting signal and the second resetting signal, respectively.

6. The dfe of claim 5, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier.

7. The dfe of claim 1, wherein the adjusting circuit comprises:

a first differential amplifier selectively enabled according to the second setting signal and a clock signal to generate a first adjusting signal to the terminal according to a first differential voltage signal to adjust a voltage level of the amplified input signal; and

a second differential amplifier selectively enabled according to the second reset signal and the clock signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal.

8. The dfe of claim 7, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal, and the second differential voltage signal have the same common mode voltage.

9. The dfe of claim 7, wherein the sense amplifier comprises a sense amplifier switch controlled by a clock signal to determine whether to enable or disable, the source of the transistor of the first differential amplifier is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch is controlled by the second setting signal and the clock signal at the same time, and the second switch is controlled by the second resetting signal and the clock signal at the same time.

10. The dfe of claim 9, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier.