CN111725998A - Dead time optimization control device and method - Google Patents
Dead time optimization control device and method Download PDFInfo
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- CN111725998A CN111725998A CN201910219242.2A CN201910219242A CN111725998A CN 111725998 A CN111725998 A CN 111725998A CN 201910219242 A CN201910219242 A CN 201910219242A CN 111725998 A CN111725998 A CN 111725998A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention relates to a dead time optimization control device and a method thereof, wherein the method comprises the following steps: outputting a switching control signal for turning off a first power switching device connected to a voltage output terminal of the dc-dc converter in a prescribed order to a first port connected to a first switching driver; simultaneously outputting first and second short pulses having different pulse widths through second and third ports connected to second and third switch drivers, respectively, in order to turn on a second power switching device in advance after outputting a switch control signal and before alternately switching the second power switching device; and outputting a switching control signal for alternately switching the second power switching devices to a fourth port connected to the fourth switching driver, so that a dead time interval occurring due to the alternate switching of the 2 power switching devices is minimized, and after the second power switching devices reach a threshold voltage, applying only 1 short pulse to smooth a falling slope of a voltage drop at the output terminal of the inverter, thereby minimizing switching noise.
Description
Technical Field
The present invention relates to a direct current-direct current (DC-DC) converter, and more particularly, to a control apparatus and method for suppressing electromagnetic interference (EMI) noise and optimizing dead-time (dead-time) in a DC-DC converter.
Background
The DC-DC converter includes: a voltage conversion unit that generates an output voltage converted from an input voltage by switching a switching device; and a control section for controlling switching of the switching device to stabilize an output voltage of the voltage conversion section. The dc-dc converter having such a structure is a component generally used in a portable electronic device using a battery as a voltage source.
Dc-dc converters can be classified into Synchronous (Synchronous) and Asynchronous (Asynchronous), and in order to improve efficiency, an Asynchronous method using switches and diodes is being changed to a Synchronous method using 2 switches.
However, when designing a synchronous converter, if a condition occurs in which 2 switches are simultaneously turned on, a large power loss occurs. Therefore, in the case of designing the dc-dc converter in a synchronous manner, it is necessary to form a section to prevent simultaneous driving between the switches, which is generally referred to as a dead time section.
The driving during the dead time interval maintains the inductor current through the parasitic diode of the switch. That is, the power loss in the dead time zone occurs due to the parasitic diode, and the power loss increases as the dead time increases since it occurs through the diode channel like the asynchronous dc-dc converter.
Therefore, in the synchronous dc-dc converter, as a scheme for maximizing efficiency, it is necessary to reduce the dead time period, and for this purpose, a technique (adaptive dead time control) for minimizing the dead time is proposed.
The proposed adaptive dead time control method is a method of driving a constituent switch of a dc-dc converter by detecting a current flow signal of an inductor through a parasitic diode, that is, a method of using a switch driver. In order to reduce the dead time, it is necessary to increase the size of the switch driver, but in this case, hard-switching occurs, and thus the occurrence of electromagnetic interference noise is relatively large, thereby having an influence on an external Integrated Circuit (IC) or the environment. Therefore, when the proposed "adaptive dead time control method" is used, the trade-off (trade-off) relationship between the dead time zone and the electromagnetic interference noise cannot be removed, and the minimum dead time zone cannot be secured.
Documents of the prior art
Patent document
Patent document 1: korean granted patent publication No. 10-1367607
Patent document 2: united states granted patent No. US6294954
Disclosure of Invention
Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a dead time optimization control apparatus and method thereof that can minimize electromagnetic interference noise by minimizing a dead time zone and preventing hard switching from occurring.
In the dead time optimization control apparatus according to an embodiment of the present invention for solving the above-described problems, the dc-dc converter includes an inductor and first and second power switching devices, the inductor is connected to an input power source, and the first and second power switching devices are connected in parallel to the inductor, and the dead time optimization control apparatus includes: a pulse generator simultaneously outputting a plurality of short pulses having different pulse widths from each other to turn on the second power switching device when detecting a turn-off time point of a switching control signal applied to the first power switching device connected to a voltage output terminal of the dc-dc converter; a first switch driver outputting a switch control signal for turning on the second power switching device within a pulse width section of a first short pulse output from the pulse generator; a second switch driver which outputs a switch control signal for turning on the second power switching device in a pulse width section of a second short pulse output from the pulse generator; and a pulse width modulation controller that alternately switches the first power switching device and the second power switching device according to a pulse width modulation duty ratio to raise an output voltage of the dc-dc converter from an input voltage level to a target level.
Further, in the dc-dc converter having the above configuration, the pulse generator generates and outputs the first short pulse and the second short pulse after a predetermined time is delayed after detecting an off time point of a switching control signal applied to the first power switching device to minimize a dead time period, and a value of a pulse width of the second short pulse generated and output simultaneously with the first short pulse is larger than a value of a pulse width of the first short pulse.
Furthermore, the dead time optimization control method of the embodiment of the invention can be executed in a pulse width modulation controller of the DC-DC converter, the dead time optimization control device of the DC-DC converter comprises an inductor, a first power switching device, a second power switching device and a pulse width modulation controller, the inductor is connected to an input power source, the first and second power switching devices are connected in parallel with the inductor, the PWM controller alternately switches the first and second power switching devices according to a PWM duty cycle to increase an output voltage of the DC-DC converter from an input voltage level to a target level, the dead time optimization control method of the DC-DC converter is characterized by comprising the following steps: outputting a switching control signal for turning off the first power switching device connected to the voltage output terminal of the dc-dc converter in a predetermined order to a first port connected to a first switching driver; a step of simultaneously outputting first and second short pulses having different pulse widths through second and third ports connected to different second and third switch drivers, respectively, in order to turn on the second power switching device in advance after outputting the switch control signal and before alternately switching the second power switching device; and outputting a switching control signal for alternately switching the second power switching device to a fourth port connected to a fourth switching driver.
The present invention is characterized in that, in such a control method, a value of a pulse width of the second short pulse generated and output simultaneously with the first short pulse is larger than a value of a pulse width of the first short pulse.
According to the solution to the problem, the present invention is characterized in that dead time sections occurring due to alternately switching 2 power switching devices are minimized, and after the second power switching device reaches the threshold voltage, the falling slope of the voltage drop of the inverter output terminal is made gentle (i.e., to have a double slope) by applying only 1 short pulse (1 switching driver), thereby minimizing switching noise.
Drawings
Fig. 1 is a diagram illustrating a structure of a dc-dc converter including a dead time optimization control apparatus according to an embodiment of the present invention.
Fig. 2 is a signal timing diagram for illustrating the operation of the dead time optimization control apparatus according to an embodiment of the present invention.
Fig. 3 is an exemplary diagram of a signal output flow for explaining a dead time optimization control method according to another embodiment of the present invention.
Detailed Description
The specific structural and functional descriptions of the embodiments based on the inventive concept disclosed in the present specification are provided for illustrative purposes only to illustrate the embodiments based on the inventive concept, and the embodiments based on the inventive concept can be embodied in various forms without being limited to the embodiments described in the present specification.
Also, embodiments based on the concept of the present invention can implement various modifications and can have various forms, and thus will be exemplified in the drawings and described in detail in this specification. However, it is not intended that the embodiments based on the concept of the present invention be limited to the specific forms disclosed, but include all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.
In describing the present invention, when it is judged that a detailed description of related well-known functions, structures, and the like may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted.
First, fig. 1 illustrates a configuration diagram of a dc-dc converter including a dead time optimization control apparatus according to an embodiment of the present invention.
As shown in fig. 1, a dc-dc converter for converting dc power from one voltage to another voltage includes: an inductor L connected to an input power source VIN; and a first power switching device N1 and a second power switching device N2 connected in parallel with the inductor L. For convenience of explanation, a node at which one side of the inductor L is connected to the first power switching device N1 and the second power switching device N2 is referred to as a node LX hereinafter.
As shown, a P-channel metal oxide semiconductor (PMOS) transistor may be used as the first power switching device N1, and a channel metal oxide semiconductor (NMOS) transistor may be used as the second power switching device N2. These power switching devices N1, N2 are turned on and off according to a switching control signal applied to the gate terminals, and it is necessary to alternately (complementarily) turn on or off these switching devices. That is, only one switching device is turned on by a switching control signal output from the pulse width modulation controller 30 described later. For reference, a charging capacitor C is coupled between the first power switching device N1 and ground.
When the second power switching device N2 is in an on state, current flows in a clockwise direction through the inductor L and energy is stored by the inductor L. When the second power switching device N2 is in the off state and the first power switching device N1 is in the on state, the energy stored in the inductor L and the input dc voltage VIN charge the capacitor C through the first power switching device 310. Where the switching speed is sufficiently fast, the inductor L does not fully discharge when the capacitor C is charged. Therefore, when the second power switching device N2 is in the off state and the first power switching device N1 is in the on state, the output voltage VOUT of the load terminal connected in parallel with the capacitor C is always greater than the input voltage VIN.
As described above, when the second power switching device N2 is in the off state, the energy stored in the inductor L and the input dc voltage VIN are combined to charge the capacitor C, and then, when the second power switching device N2 is in the on state and the first power switching device N1 is in the off state, the capacitor C may provide the stored voltage and energy to the load terminal. That is, when the second power switching device N2 is in an off state and the first power switching device N1 is in an on state, the output voltage VOUT increases, and when the second power switching device N2 is in an on state and the first power switching device N1 is in an off state, the output voltage VOUT decreases.
A switching buffer 40 including a plurality of switching drivers SD1 to SD4 is connected to gate terminals of the first power switching device N1 and the second power switching device N2, and the switching buffer 40 is connected to a pulse width modulation controller 30 that alternately switches the first power switching device N1 and the second power switching device N2 in accordance with a pulse width modulation duty ratio to control the output voltage of the converter to increase from the input voltage level to a target level. The switching buffer 40 and the pwm controller 30 are referred to as a pwm driver as appropriate.
A first switching control signal for controlling the first power switching device N1 and the second power switching device N2 in an alternately switching manner is output from the pulse width modulation controller 30 and applied to the gate terminal of the first power switching device N1 through the first switching driver SD1, and a second switching control signal is also output from the pulse width modulation controller 30 and applied to the gate terminal of the second power switching device N2 through the second switching driver SD 4.
The first and second switch drivers SD1 and SD4 are switch drivers that drive the first and second power switching devices by receiving set (set) and reset (reset) signals generated by a pulse width modulation circuit, and are driven by receiving phase signals of the switch drivers SD2 and SD3 that are driven slower than short pulses to be described later, and function to pull up or pull down the phases of the gate terminals of the power switching devices that are high/low by the switch drivers SD2 and SD3 that are driven instantaneously.
In addition to the structure, the dc-dc converter may further include a mode conversion control part that linearly increases an output voltage of the dc-dc converter by supplying a current in a linear mode, performs a switching operation according to a pulse width modulation duty ratio in a switching mode to increase the output voltage to a target level, and determines whether to enter the switching mode in the linear mode.
As shown, the mode conversion control section includes an error amplifier 10, a lamp controller (not shown), and a comparator 20. The structure and operation of such a mode conversion control part are disclosed in detail in issued patent No. 10-1642761 previously filed and issued by the applicant of the present application, and thus a detailed description thereof will be omitted.
In addition to the above-described configuration, in order to minimize the dead time zone and prevent the occurrence of hard switching, the dc-dc converter according to an embodiment of the present invention further includes: a pulse generator 50 for simultaneously outputting a plurality of short pulses having pulse widths different from each other to turn on the second power switching device N2 upon detecting a turn-off time point of a switching control signal applied to a gate terminal of the first power switching device N1 connected to a voltage output terminal of the converter; a third switch driver SD2 that outputs a third switch control signal for turning on the second power switching device N2 in a pulse width interval of the first short pulse output from the pulse generator 50; and a fourth switch driver SD3 that outputs a fourth switch control signal for turning on the second power switching device N2 within a pulse width interval of the second short pulse output from the pulse generator 50.
The pulse generator 50 generates and outputs the first short pulse and the second short pulse having different pulse widths simultaneously after a predetermined time is delayed after detecting the off time point of the switching control signal applied to the first power switching device N1, and thus, in order to output the first short pulse and the second short pulse after being delayed by the predetermined time, an inverting device (not shown) for inverting the first switching control signal applied to the gate terminal of the first power switching device N1 is further included at an input terminal.
The first short pulse and the second short pulse have a pulse width in nanosecond (nano-sec) units, and a value of the pulse width of the second short pulse generated and output simultaneously with the first short pulse is larger than a value of the pulse width of the first short pulse. This is to slowly gradually reduce the output voltage variation slope of the LX node as the output terminal of the inductor L by reducing the number of switching control signals applied to the gate terminal of the second power switching device to reduce the switching noise.
Hereinafter, the operation of the dc-dc converter having the above-described configuration will be described in more detail with reference to fig. 2.
Fig. 2 illustrates a signal timing chart for explaining the operation of the dead time optimization control apparatus according to the embodiment of the present invention.
Referring to fig. 2, in a switching mode of alternately controlling the first power switching device N1 and the second power switching device N2, the pulse width modulation controller 30 outputs a first switching control signal for off-controlling the first power switching device N1 in turn from a low level to a high level, as shown in fig. 2. This first switch control signal is applied to the gate terminal of the first power switching device N1, and to the pulse generator 50, through port P1 and by means of the switch driver SD1 within the switch buffer 40.
The potential in the pulse generator 50 is provided with an inverting device, and thus, as shown in fig. 2, the first switching control signal that changes from a low level to a high level is inverted with a predetermined time delay timing. This is shown in fig. 2 as an inverted signal.
When a level change of such an inversion signal, that is, a level change from a high level to a low level is detected, the pulse generator 50 recognizes it as a turn-off instruction of the first power switching device, thereby simultaneously generating and outputting a first short pulse and a second short pulse synchronized with a level change time point of the inversion signal, the first short pulse and the second short pulse having a pulse width in nanosecond units, and generating and outputting a pulse having a value of the pulse width of the second short pulse larger than that of the first short pulse.
The first and second short pulses generated and output from the pulse generator 50 are applied to the gate terminal of the second power switching device N2 through the switching drivers SD2, SD3 in the switching buffer 40, respectively.
As described above, before the first short pulse and the second short pulse for turning on the second power switching device N2 by the switch drivers SD2 and SD3 are simultaneously applied to the gate terminal, LX as an output node of the inverter L exhibits a dead time interval (first) as shown in fig. 2, but in the interval (second) in which the signal level for turning on the second power switching device N2 is applied, the amount of electric charge of the gate terminal is changed, and the voltage level of the LX node is abruptly decreased (interval (second)).
On the other hand, since the pulse width of the first short pulse for turning on the second power switching device N2 is smaller than that of the second short pulse, the voltage level of the LX node sharply decreases at a slower slope than the interval (c) at the time point (interval (c)) when the on interval of the first short pulse ends, so that an effect of reducing switching noise can be obtained compared to before.
For reference, the interval in which the LX node has the falling slope (falling slope) is a miller plateau (millplateau) interval, and the interval is reached by charging the gate capacitor of the second power switching device. In the interval where the initial gate rises from 0[ V ] to the threshold voltage, the value is mainly the centimeter-gram-second (Cgs), and thus the corresponding value can be obtained by the size of the second power switching device N2. The amount of current applied to the gate terminal can be determined by the size of the switch driver, and the time required for the gate terminal to reach the threshold voltage can be determined by T ═ C × V)/I. This can be used to derive the time of entry into the vicinity of the miller stage and by implementing the first short pulse as a signal that is turned off immediately after the miller stage is reached, control of the dead time interval can be achieved by a two-pole configuration.
That is, the dead time optimization control apparatus of the embodiment of the invention rapidly outputs a plurality of short pulses for turning on the second power switching device in advance (rapidly bringing the gate voltage of the second power switching device to the threshold voltage through 2 switching drivers) before alternately switching the second power switching device by detecting the time point for turning off the first power switching device N1 in the switching mode, so that the dead time section occurring due to alternately switching the first power switching device and the second power switching device can be minimized,
after the second power switching device reaches the threshold voltage, only 1 short pulse (1 switching driver) is applied to smooth the falling slope of the voltage drop of the LX node, so that the switching noise can be minimized.
The second switch control signal, which is not illustrated in fig. 2, is a signal output from the pulse width modulation controller 30 in order to alternately switch the second power switching device N2 in the switching mode, representing a signal applied to the gate terminal of the second power switching device N2 through the port P2 and by means of the switch driver SD 4.
In the embodiment, a specific embodiment in which the dead time and the switching noise are minimized by providing a separate pulse generator is described, but the dead time and the switching noise may be minimized by outputting the first short pulse and the second short pulse from the pulse width modulation controller 30 in a designated order without providing a pulse generator. This will be explained with reference to fig. 3.
First, fig. 3 illustrates a signal output flowchart for explaining a dead time optimization control method according to another embodiment of the present invention.
As shown in fig. 3, the pwm controller 30, which alternately switches the first power switching device N1 and the second power switching device N2 according to the pwm duty ratio to increase the output voltage from the input voltage level to the target level, outputs a switching control signal for turning off the first power switching device N1 in a predetermined order to the first port P1 connected to the first switching driver (SD 1 in fig. 1) in the switching mode (step S10).
The pwm controller 30 simultaneously outputs first and second short pulses having different pulse widths through second and third ports (not shown in fig. 1) connected to the second and third switch drivers SD2 and SD3, respectively, in order to turn on the second power switch N2 in advance before alternately switching the second power switch N2 after outputting the switch control signal (step S20).
For reference, the time from the inversion time point of the switching control signal inverted to turn off the first power switching device N1 to the time point of simultaneously outputting the first and second short pulses should be set in consideration of a section for minimizing a dead time.
If the steps S10 and S20 are performed by the pwm controller 30, as described in the previous embodiment, a plurality of short pulses for turning on the second power switching device N2 in advance (the gate voltage of the second power switching device is rapidly brought to the threshold voltage by 2 switching drivers) are rapidly output before the second power switching device is alternately switched (step S30), so that the dead time period occurring due to the alternate switching of the first power switching device N1 and the second power switching device N2 (steps S10 and S30) can be minimized.
After the second power switching device N2 reaches the threshold voltage, only 1 short pulse (1 switching driver) is applied to make the falling slope of the voltage drop of the LX node gentle (i.e., to have a double slope), so that the switching noise can be minimized.
Therefore, the present invention can achieve the object of the present invention by changing the specific circuit design shown in fig. 1 or the drive control program of the switch driver.
While the invention has been described with reference to the embodiments shown in the drawings, the same is to be considered as illustrative and various modifications and equivalent other embodiments will be apparent to those skilled in the art. Therefore, the true technical scope of the present invention should be determined only by the appended claims.
Claims (6)
1. A dead time optimization control apparatus of a DC-DC converter including an inductor connected to an input power source and first and second power switching devices connected in parallel with the inductor,
it is characterized by comprising:
a pulse generator simultaneously outputting a plurality of short pulses having different pulse widths from each other to turn on the second power switching device when detecting a turn-off time point of a switching control signal applied to the first power switching device connected to a voltage output terminal of the dc-dc converter;
a first switch driver outputting a switch control signal for turning on the second power switching device within a pulse width section of a first short pulse output from the pulse generator;
a second switch driver which outputs a switch control signal for turning on the second power switching device in a pulse width section of a second short pulse output from the pulse generator; and
and a pulse width modulation controller that alternately switches the first power switching device and the second power switching device according to a pulse width modulation duty ratio to increase an output voltage of the dc-dc converter from an input voltage level to a target level.
2. The dead time optimization control device of a DC-DC converter according to claim 1,
the pulse generator generates and outputs the first and second short pulses after delaying a prescribed time after detecting an off time point of a switching control signal applied to the first power switching device to minimize a dead time interval.
3. The dead time optimization control device of a DC-DC converter according to claim 1 or 2,
the pulse generator further includes an inverting device for inverting the switching control signal applied to the first power switching device to generate and output the first and second short pulses after a delay of a prescribed time after detecting an off time point of the switching control signal applied to the first power switching device.
4. The dead time optimization control device of a DC-DC converter according to claim 1 or 2,
the second short pulse generated and output simultaneously with the first short pulse has a pulse width larger in value than that of the first short pulse.
5. A dead time optimization control method of a DC-DC converter including an inductor connected to an input power source, first and second power switching devices connected in parallel with the inductor, and a pulse width modulation controller alternately switching the first and second power switching devices according to a pulse width modulation duty ratio to raise an output voltage of the DC-DC converter from an input voltage level to a target level,
it is characterized by comprising:
outputting a switching control signal for turning off the first power switching device connected to the voltage output terminal of the dc-dc converter in a predetermined order to a first port connected to a first switching driver;
a step of simultaneously outputting first and second short pulses having different pulse widths through second and third ports connected to different second and third switch drivers, respectively, in order to turn on the second power switching device in advance after outputting the switch control signal and before alternately switching the second power switching device; and
and outputting a switching control signal for alternately switching the second power switching device to a fourth port connected to a fourth switching driver.
6. The dead time optimization control method of the DC-DC converter according to claim 5,
the second short pulse generated and output simultaneously with the first short pulse has a pulse width larger in value than that of the first short pulse.
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| CN101176049A (en) * | 2004-06-21 | 2008-05-07 | 艾斯泰克国际有限公司 | Dynamic optimization of efficiency using dead time and fet drive control |
| CN102904432A (en) * | 2011-07-28 | 2013-01-30 | 美芯晟科技（北京）有限公司 | Drive control circuit of synchronous switch power switching system |
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