CN111725086B - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device Download PDF

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Publication number
CN111725086B
CN111725086B CN202010110478.5A CN202010110478A CN111725086B CN 111725086 B CN111725086 B CN 111725086B CN 202010110478 A CN202010110478 A CN 202010110478A CN 111725086 B CN111725086 B CN 111725086B
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bare chip
imaging device
illumination
illumination device
control unit
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CN111725086A (en
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小桥英晴
保坂浩二
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)

Abstract

Provided are a semiconductor manufacturing apparatus and a semiconductor device manufacturing method capable of reflecting illumination light and preventing the illumination light from being input to a camera even when the flatness of the surface of a wafer or a bare chip cannot be maintained. The semiconductor manufacturing apparatus includes: an imaging device for imaging the bare chip; an illumination device that irradiates light to the bare chip at a predetermined angle with respect to an optical axis of the imaging device; and a control unit that controls the imaging device and the illumination device. The predetermined angle is an angle at which, when the bare chip is flat, light irradiated from the illumination device is not entered into the imaging device even if the light is directly reflected by the bare chip. The control unit is configured to move at least one of the imaging device, the illumination device, and the bare chip so that light irradiated from the illumination device is directly reflected by the bare chip without entering the imaging device when the bare chip is uneven.

Description

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
Technical Field
The present disclosure relates to a semiconductor manufacturing apparatus, and for example, to be applied to a chip mounter equipped with a camera that recognizes a bare chip.
Background
In some of the steps of manufacturing a semiconductor device, there are a step of mounting a semiconductor chip (hereinafter, simply referred to as a bare chip) on a wiring board, a lead frame, or the like (hereinafter, simply referred to as a board) to assemble a package, and a step of dividing the bare chip from a semiconductor wafer (hereinafter, simply referred to as a wafer) (dicing step) and a mounting step of mounting the divided bare chip on a board. The semiconductor manufacturing apparatus used in the mounting process is a chip mounter.
The die mounter is a device that mounts (mounts and adheres) a bare chip onto a substrate or a mounted bare chip using solder, gold plating, or resin as a bonding material. For example, in a die mounter that mounts a bare chip on a surface of a substrate, the following operations (operations) are repeated: the bare chip is sucked and picked up from the wafer by a suction nozzle called a collet, the bare chip is carried onto the substrate and given a pressing force, and the bonding material is heated, whereby mounting is performed. The collet has a suction hole, and the collet and the bare chip have the same size for sucking air to suck and hold the holder of the bare chip.
Before picking up the bare chip from the wafer or after attaching the bare chip to the substrate or the like, in order to check whether the wafer or the bare chip is damaged or foreign matter such as cracks or the like, the imaging is performed by a camera using an illumination device.
Prior art literature
Patent document 1: japanese patent laid-open No. 2017-117916
Disclosure of Invention
In general, a dark field method is preferably used when detecting a minute damage. The wafer surface is close to the mirror surface, and for performing inspection by the dark field method, oblique illumination, which is an illumination method for obliquely radiating light, may be used. In the dark field inspection method, it is demanded that the surface of a wafer or a bare chip serving as a background reflect illumination light and prevent the light from being input to a camera. Even if the reflection of the illumination light is not input to the camera when the flatness of the surface of the wafer or the bare chip can be maintained, the reflection of the illumination light may be generated and input to the camera when the wafer or the bare chip has warpage or the like and the flatness of the surface of the wafer or the bare chip cannot be maintained.
The subject of the present disclosure provides a technique capable of reflecting the illumination light and preventing it from being input to the camera even when the flatness of the surface of the wafer or the bare chip cannot be maintained.
Other problems and novel features will become apparent from the description and drawings.
A typical outline of the present disclosure will be described below.
That is, the semiconductor manufacturing apparatus includes: an imaging device for imaging the bare chip; an illumination device that irradiates light to the bare chip at a predetermined angle with respect to an optical axis of the imaging device; and a control unit that controls the imaging device and the illumination device. The predetermined angle is an angle at which, when the bare chip is flat, light irradiated from the illumination device is not entered into the imaging device even if the light is directly reflected by the bare chip. The control unit is configured to move at least one of the imaging device, the illumination device, and the bare chip so that light irradiated from the illumination device is directly reflected by the bare chip without entering the imaging device when the bare chip is uneven.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the semiconductor manufacturing apparatus, even when the flatness of the surface of the wafer or the bare chip cannot be maintained, the illuminated light can be reflected and not input to the camera.
Drawings
Fig. 1 is a diagram schematically showing coaxial illumination.
Fig. 2 is a diagram schematically showing oblique illumination.
Fig. 3 is a diagram schematically showing the states of incident light and reflected light of oblique illumination.
Fig. 4 is a diagram schematically showing states of incident light and reflected light in the case where the incident angle is smaller than that of fig. 3.
Fig. 5 is an example of an image taken by using the oblique light tube illumination of fig. 4.
Fig. 6 is a diagram illustrating a problem of oblique illumination.
Fig. 7 is a diagram illustrating a technique of the embodiment.
Fig. 8 is a flow chart illustrating a first method.
Fig. 9 is a flow chart illustrating a second method.
Fig. 10 is a diagram illustrating a case where a region where direct light reflection cannot be eliminated even if the field of view is moved.
Fig. 11 is a schematic plan view showing an exemplary configuration of the chip mounter of the embodiment.
Fig. 12 is a diagram illustrating a schematic configuration when viewed from the arrow a direction in fig. 11.
Fig. 13 is an external perspective view showing the configuration of the bare chip supply portion of fig. 11.
Fig. 14 is a schematic cross-sectional view showing a main part of the bare chip supply part of fig. 13.
Fig. 15 is a diagram showing the arrangement of the lighting device of the substrate recognition camera.
Fig. 16 is a block diagram showing a schematic configuration of the control system of the chip mounter of fig. 11.
Fig. 17 is a flowchart illustrating a die attach process of the die attach machine of fig. 11.
Fig. 18 is a flowchart mainly showing a process of photographing by the wafer recognition camera.
Fig. 19 is a flowchart mainly showing a process of photographing by the substrate recognition camera.
Fig. 20 is a diagram illustrating a method of measuring a warpage position (regular reflection region) of a bare chip.
Fig. 21 is a diagram illustrating the effect of oblique illumination on a specular object with respect to the optical axis with respect to the oblique illumination of fig. 7.
Fig. 22 is a schematic perspective view showing a substrate recognition camera and an illumination device in the first modification.
Fig. 23 is a schematic perspective view showing a substrate recognition camera and an illumination device in a second modification.
Fig. 24 is a schematic perspective view showing a wafer recognition camera and an illumination device in a third modification.
Wherein reference numerals are as follows:
10. chip mounter (semiconductor manufacturing device)
8. Control unit
D bare chip
S substrate
CMR camera (image pickup device)
OBL lighting device
OA optical axis
VF field of view
Detailed Description
Hereinafter, embodiments and examples will be described with reference to the drawings. In the following description, the same reference numerals are given to the same components in some cases, and redundant description thereof is omitted. In order to make the description more clear, the width, thickness, shape, and the like of each portion may be schematically shown in the drawings as compared with the actual case, but this is merely an example, and does not limit the explanation of the present invention.
When inspecting cracks in a bare chip with a dark field of oblique illumination, it is important to maintain a high detection rate in terms of illumination and the relative positional relationship between a camera (imaging device) and the bare chip. As described later, in oblique illumination, it is preferable that the illumination device be disposed so that the incident angle is as perpendicular as possible to the surface of the bare chip, and that the incident angle be at a limit at which light that is directly reflected (direct light) does not enter the camera. If the incident angle exceeds this, light from the light source specularly reflected on the surface of the bare chip is directly incident on the camera. Therefore, the bare chip surface becomes bright field in crack inspection. It becomes difficult to secure the contrast of the crack with the background, with the result that the detection rate is deteriorated.
The incident angle of illumination will be described with reference to fig. 1 to 4. Fig. 1 is a diagram schematically showing coaxial illumination. Fig. 2 is a diagram schematically showing oblique illumination. Fig. 3 is a diagram schematically showing the states of incident light and reflected light of oblique illumination. Fig. 4 is a diagram schematically showing states of incident light and reflected light in the case where the incident angle is smaller than that of fig. 3. Fig. 5 is an example of an image taken by using the oblique light tube illumination of fig. 4.
As shown in fig. 1, in the coaxial illumination, the illumination device CEI is configured to irradiate light to the surface of the bare chip D along the optical axis OA of the camera CMR and the lens LNS and the half mirror HM. Here, the optical axis OA is substantially perpendicular to the surface of the bare chip D, and the incident angle is substantially 0 degrees. Therefore, when the imaging is performed by the camera CMR using the illumination device CEI, the surface of the bare chip D becomes bright field with respect to the crack, the reflectance is also close, and it is difficult to compare, and as a result, the detection sensitivity does not become good.
As shown in fig. 2, in oblique illumination, the illumination device OBL is configured such that light is irradiated to the surface of the bare chip D at a predetermined angle with respect to the optical axis OA of the camera CMR and the lens LNS. Here, the incident angle with respect to the optical axis is set to θ. When the imaging is performed by the camera CMR using the illumination device OBL, the surface of the bare chip D becomes dark field with respect to the crack, and the reflectance is also different, so that the comparison is easy. The closer the incident angle of the illumination device OBL is to plumb (θ becomes smaller), the larger the contrast difference between the crack and the background becomes, the easier classification (binarization or the like) on the image becomes, and as a result, the detection sensitivity becomes better.
At this time, as shown in fig. 3, the light RL configured to be specularly reflected at the surface of the bare chip D to be inspected is not directly incident on the lens LNS. The incident angle at this time was set to θ1. However, if the incident angle of the illumination device OBL is too close to plumb, as shown in fig. 4, the light RL specularly reflected on the surface of the bare chip D enters the lens LNS. If the incident angle at this time is set to θ2, 0 < θ2 < θ1. Therefore, as shown in fig. 5, the reflected region RA becomes bright field, so that the detection sensitivity is deteriorated. Therefore, the positional relationship among the lighting device, the camera, and the bare chip is particularly important.
Next, the problem of oblique illumination will be described with reference to fig. 6. Fig. 6 (a) is a diagram schematically showing the state of incident light and reflected light of oblique illumination to the stacked bare chips. Fig. 6 (b) is an enlarged view of the stacked bare chips of fig. 6 (a). Fig. 6 (c) is an example of an image of the stacked bare chips of fig. 6 (a).
The above-described positional relationship of the illumination, the camera, and the bare chip is established when the flatness of the surface of the bare chip is flat to some extent. However, the flatness cannot be maintained due to the kind of bare chips stacked such as NAND flash memories. For example, as shown in fig. 6 (b), in the case of a method of stacking bare chips D1, D2, D3, and D4 while stacking them, there is a case where the area NSA where the lower layer is not supported is warped upward. As a result, as shown in fig. 6 (a), even if the incident angle of the illumination light of the illumination device OBL is θ1 as in fig. 3, the light (light whose reflection angle has changed) RL1 directly reflected by the upwardly warped region WA of the bare chip D4 enters the lens LNS, and as shown in fig. 6 (c), the area NSA (upwardly warped region WA) not supported by the lower layer becomes bright field, which results in deterioration of the detection sensitivity.
Next, a technique according to an embodiment for solving the above-described problems will be described with reference to fig. 7. Fig. 7 (a) is a diagram schematically showing the state of incident light and reflected light of oblique illumination to the stacked bare chips. Fig. 7 (b) is an example of an image of the stacked bare chips of fig. 7 (a) taken at the center of the field of view. Fig. 7 (c) is an example of an image taken of the stacked bare chips of fig. 7 (a) at a position offset from the center of the field of view.
In the embodiment, at least one of the camera CMR, the illumination device OBL, and the bare chip D is moved so that the reflected light of the upwardly warped surface of the bare chip D is not captured by the lens LNS.
For example, as shown in fig. 7 (a), by moving the camera CMR and the illumination device OBL in the same direction (the direction of the arrow) at the same time, the light RL1 reflected on the upwardly warped surface of the bare chip D is not captured by the lens. Here, the positional relationship among the lighting device OBL, the camera CMR, and the bare chip D (bare chip with maintained flatness) at the beginning (before movement) is, as shown in fig. 3, in a position where bright field does not appear on the surface of the bare chip D.
That is, as shown by the broken line in fig. 7 a, the illumination device OBL, the camera CMR, and the bare chip D are arranged, and the center of the bare chip D is placed at the center (optical axis OA) of the field of view VF of the camera CMR. In the case where the bare chip D is warped upward, the light RL1 directly reflected in the upward warped region of the bare chip D enters the lens LNS, and becomes bright field as shown in fig. 7 (b).
On the other hand, as shown in fig. 7 (a), by moving the camera CMR and the oblique illumination device OBL, the center of the field of view VF (optical axis OA) is shifted from the center of the bare chip D, so that the light RL1 directly reflected in the upwardly warped region WA of the bare chip D does not enter the lens LNS, and as shown in fig. 7 (c), bright field does not appear.
It is preferable to move the camera CMR and the illumination device OBL simultaneously. This is because the positional relationship between the camera CMR and the illumination device OBL is easily maintained. The bright field is not generated in the area where the bare chip is not warped, and only the illumination device OBL or only the camera CMR may be moved.
Instead of the movement of the camera CMR and/or the illumination device OBL, an object to be imaged may be moved. For example, the dicing tape is moved with the bare chip on the dicing tape warped, or the substrate is moved on a tape loading table.
In addition, it is preferable that the direction be opposite to the brightly light emitting surface when the camera CMR and the illumination device OBL are moved. Preferably, the direction of the surface that emits light brightly is the same when the subject is moving. In addition, the field of view is preferably about 2 times the size of the bare chip.
The camera position, the illumination position, or the object position is changed in consideration of warpage of the bare chip. In order to ensure inspection sensitivity, it is preferable that the incidence angle is set to the limit at which direct light after specular reflection is not received, and that the position adjustment is possible in accordance with the deformation of the subject, so that deterioration of the inspection sensitivity of die crack inspection due to the influence of warpage of the die can be suppressed to the minimum.
In addition, oblique illumination is generally formed in pairs face to face, for example, using oblique light tube illumination in two directions or oblique light tube illumination in four directions. The influence of oblique illumination (hereinafter referred to as opposite-side oblique illumination) on a specular object with respect to the optical axis OA, which is the oblique illumination of fig. 7 (a), will be described with reference to fig. 21. Fig. 21 (a) is a diagram schematically showing the state of incident light and reflected light of oblique illumination on the opposite side of a certain bare chip of warpage before moving to the field of view. Fig. 21 (b) is a diagram schematically showing the state of incident light and reflected light obliquely illuminating the opposite side of the bare chip without warpage. Fig. 21 (c) is a diagram schematically showing the state of incident light and reflected light of opposite side oblique illumination of a bare chip with warpage before and after moving to the field of view.
When oblique illumination in pairs facing each other is moved based on the field of view described so far, as shown in fig. 21 b, light directly reflected by the bare chip D without warpage (hereinafter, referred to as specular reflection light) enters the camera, and as a result, the bare chip D photographed is whitened. However, as shown in fig. 21 (c), since the slope of the reflected light also increases in the bare chip D having warpage, the influence is less likely to occur. In addition, when the illumination is in four directions, the light sources in orthogonal directions are not inherently affected by such warpage.
Next, a method in the case of moving the field of view relative to the object to be imaged will be described with reference to fig. 8 and 9. Fig. 8 is a flow chart illustrating a first method. Fig. 9 is a flow chart illustrating a second method.
The first method is a method of relatively moving the field of view for the bare chip D after confirming whether there is direct reflection of the irradiation light due to warpage. Relative field movement and re-inspection occurs when direct light reflection occurs. The moving direction of the field of view is determined according to the position on the bare chip where the direct reflected light is generated. Is suitable for coping with bare chips on wafers with unidentified warpage positions. Here, the relative field of view movement means that the field of view of the camera CMR for the bare chip D is moved by moving at least one of the camera CMR and the bare chip D. The center of the field of view of camera CMR is offset from the center of die D by the relative field of view movement.
As shown in fig. 8, after the component transportation (step S11) and the die positioning (step S12) by pattern matching, the illuminance of the surface of the die D is checked by an illuminometer incorporated in the camera CMR, and whether or not the specular reflection of the direct light of the light source (direct reflection of the irradiation light) is present is checked (step S13). In the presence of specular reflection of the direct light of the light source, a relative field of view movement is performed (step S14). If there is no specular reflection of the direct light of the light source, the bare chip D is inspected for cracks and foreign matter (step S15). In addition, the bare chip crack inspection may be initiated before confirming the presence of direct reflection of the non-light source light. In addition, an illuminometer may be provided in addition to the camera CMR to confirm the surface illuminance of the bare chip D.
The second method is as follows: when bare chips are stacked, the warp direction is determined, and a shift amount is defined by modeling or the like according to the number of stacked bare chips, so that the relative field of view is shifted in advance.
As shown in fig. 9, after the component transportation (step S11) and the die positioning (step S12) by pattern matching or the like, relative field movement is performed based on the number of layers of the positioning die (step S24). Since the warpage of the lower die is small and the warpage of the upper die is large, the amount of movement increases as the upper die becomes. Thereafter, the bare chip D is inspected for cracks and foreign matter (step S25). The method may further include a confirmation process of confirming whether or not there is direct reflection of the light source light, and readjusting the amount of movement.
Further, even if the relative field of view is moved, there are cases where the area of direct light reflection cannot be eliminated. This is described with reference to fig. 10. Fig. 10 (a) is a captured image before the movement of the field of view. Fig. 10 (b) is a captured image after the field of view has moved.
As shown in fig. 10 (a), the area filled with white (non-inspectable area) appears as a ring before the field of view moves. As shown in fig. 10 b, the white filled region (non-inspectable region) is reduced before the movement of the field of view, but remains at the corner of the bare chip. The white-filled areas are regarded as masks each time, and the fields of view are moved relatively to each other, so that the inspection area is ensured as a total. For example, by masking the non-inspectable area of fig. 10 (a), the inspectable area of the corner of the bare chip can be ensured as an inspection area, and by masking the non-inspectable area of fig. 10 (b), the non-inspectable area of fig. 10 (a) can be ensured as an inspection area. Therefore, the entire bare chip can be ensured to be an inspection area.
Examples
Fig. 11 is a schematic plan view showing the structure of the chip mounter of the embodiment. Fig. 12 is a diagram illustrating a schematic configuration when viewed from the arrow a direction in fig. 11.
The die mounter 10 generally has a die supply section 1 for supplying die D mounted on a substrate S printed with one or more product areas (hereinafter referred to as package areas P) that eventually become a package, a pickup section 2, an intermediate stage section 3, a mounting section 4, a carrying section 5, a substrate supply section 6, a substrate carrying-out section 7, and a control section 8 for monitoring and controlling operations of the respective sections. The Y-axis direction is the front-rear direction of the chip mounter 10, and the X-axis direction is the left-right direction. The bare chip supply part 1 is disposed at the front side of the chip mounter 10, and the mounting part 4 is disposed at the far side.
First, the bare chip supply unit 1 supplies a bare chip D mounted on a package region P of a substrate S. The bare chip supply section 1 includes a wafer holding stage 12 that holds a wafer 11, and a pushing unit 13 shown by a broken line that pushes the bare chip D from the wafer 11. The die supply section 1 moves in the XY direction by a driving mechanism, not shown, to move the die D to be picked up to the position of the ejector unit 13.
The pickup section 2 includes a pickup head 21 for picking up the bare chip D, a Y driving section 23 for moving the pickup head 21 in the Y direction, and driving sections, not shown, for lifting, rotating, and moving the collet 22 in the X direction. The pickup head 21 has a collet 22 (see also fig. 12) for holding the bare chip D pushed on the tip, picks up the bare chip D from the bare chip supply unit 1, and mounts it on the intermediate stage 31. The pickup head 21 has driving parts, not shown, for lifting and lowering the collet 22, rotating it, and moving it in the X direction.
The intermediate stage section 3 includes an intermediate stage 31 on which the bare chip D is temporarily placed, and a stage recognition camera 32 for recognizing the bare chip D on the intermediate stage 31.
The mounting unit 4 picks up the bare chip D from the intermediate stage 31 and mounts it on the package region P of the substrate S carried, or mounts it so as to be stacked on the bare chip mounted on the package region P of the substrate S. The mounting portion 4 includes a mounting head 41 having a collet 42 (see also fig. 12) for holding the bare chip D on the front end in a suction manner, a Y driving portion 43 for moving the mounting head 41 in the Y direction, a board recognition camera 44 for photographing a position recognition mark (not shown) of the package region P of the board S to recognize the mounting position, and an XY driving portion 45 for driving the board recognition camera 44 in the X-axis direction and the Y-axis direction, like the pickup head 21.
With this configuration, the mounting head 41 corrects the pickup position and posture based on the pickup data of the stage recognition camera 32, picks up the bare chip D from the intermediate stage 31, and mounts the bare chip D on the substrate S based on the pickup data of the substrate recognition camera 44.
The carrying section 5 includes a substrate carrying claw 51 for picking up and carrying the substrate S, and a carrying path 52 for moving the substrate S. The substrate S is moved by driving a nut, not shown, of the substrate conveyance claw 51 provided in the conveyance path 52 by a ball screw, not shown, provided along the conveyance path 52.
With this configuration, the substrate S is moved from the substrate supply unit 6 to the mounting position along the conveyance path 52, and after mounting, is moved to the substrate carrying-out unit 7, and the substrate S is delivered to the substrate carrying-out unit 7.
The control unit 8 includes a memory in which a program (software) for monitoring and controlling operations of the respective parts of the chip mounter 10 is stored, and a Central Processing Unit (CPU) for executing the program stored in the memory.
Next, the structure of the bare chip supply portion 1 will be described with reference to fig. 13 and 14. Fig. 13 is an external perspective view showing the configuration of the bare chip supply portion of fig. 11. Fig. 14 is a schematic cross-sectional view showing a main part of the bare chip supply part of fig. 13.
The bare chip supply section 1 has a wafer holding stage 12 that moves in the horizontal direction (XY direction) and a pushing unit 13 that moves in the up-down direction. The wafer holding stage 12 has an extension ring 15 for holding the wafer ring 14, and a support ring 17 for positioning a dicing tape 16, which is held by the wafer ring 14 and to which a plurality of bare chips D are bonded, in the horizontal direction. The pushing unit 13 is disposed inside the support ring 17.
When pushing the die D, the die supply unit 1 lowers the extension ring 15 holding the wafer ring 14. As a result, the dicing tape 16 held by the wafer ring 14 is stretched, the space between the die D is widened, and the die D is pushed from below by the pushing unit 13, thereby improving the pick-up property of the die D. In addition, as the thickness of the adhesive agent for bonding the die to the substrate is reduced, the adhesive agent is formed in a film form from a liquid state, and a film-like adhesive material called a Die Attach Film (DAF) 18 is attached between the wafer 11 and the dicing tape 16. In the wafer 11 having the die-attach film 18, dicing is performed on the wafer 11 and the die-attach film 18. Therefore, in the peeling step, the wafer 11 and the die attach film 18 are peeled from the dicing tape 16. After that, the peeling step is described regardless of the presence of the die attach film 18.
The die mounter 10 has a wafer recognition camera 24 that recognizes the posture and position of the bare chip D on the wafer 11, a stage recognition camera 32 that recognizes the posture and position of the bare chip D mounted on the intermediate stage 31, and a substrate recognition camera 44 that recognizes the mounting position on the mounting stage BS. The stage recognition cameras 32 related to pickup of the mounting head 41 and the substrate recognition cameras 44 related to mounting of the mounting head 41 to the mounting position are necessary to correct the posture shift between the recognition cameras. In the present embodiment, the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 collectively perform surface inspection of the bare chip D by using an illumination device described later.
Next, illumination for surface inspection will be described with reference to fig. 15. Fig. 15 is a diagram showing the arrangement of the lighting device of the substrate recognition camera.
The substrate recognition camera 44 is arranged vertically with respect to the surface of the bare chip D. That is, the optical axis is made perpendicular to the surface of the bare chip D. The oblique illumination device 46 is oblique illumination based on two directions of the oblique tube illumination devices 46a and 46b, and irradiates the bare chip D at a predetermined angle (θ1) with respect to the optical axis. The substrate recognition camera 44 and the oblique illumination devices 46a and 46b are fixed to the movable portion 45a, and the movable portion 45a can be moved in the X-axis direction by the X driving portion 45b, and the X driving portion 45b can be moved in the Y-axis direction by the Y driving portion 45 c. Here, the incident angle (θ1) is the same as fig. 6. The control unit 8 moves the substrate recognition camera 44 and the oblique illumination device 46 by the XY driving unit 45 so as to shift the center of the field of view from the center of the bare chip D, thereby preventing light directly reflected in the upwardly warped region of the bare chip D from entering the substrate recognition camera 44 and preventing bright field.
The illumination device of the wafer recognition camera 24 and the stage recognition camera 32 is also the same as that of the substrate recognition camera 44. Here, the wafer recognition camera 24 and its illumination device, and the stage recognition camera 32 and its illumination device may not be configured to be moved by a driving unit similar to the XY driving unit 45. The control unit 8 can prevent light directly reflected on the upwardly warped area of the bare chip D from entering the wafer recognition camera 24 or the stage recognition camera 32 without bright field by moving the wafer holding stage 12 or the intermediate stage 31 and shifting the center of the field of view from the center of the bare chip D without moving the wafer recognition camera 24 or the illumination device thereof.
Next, the control unit 8 will be described with reference to fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the control system of the chip mounter of fig. 11.
The control system 80 includes a control unit 8, a driving unit 86, a signal unit 87, and an optical system 88. The control unit 8 mainly includes a control/arithmetic device 81 composed of a CPU (Central Processor Unit: central processing unit), a storage device 82, an input/output device 83, a bus line 84, and a power supply unit 85. The storage device 82 includes a main storage device 82a made up of a RAM in which a processing program and the like are stored, and an auxiliary storage device 82b made up of an HDD, SSD, and the like in which control data and/or image data necessary for control are stored. The input/output device 83 includes a monitor 83a for displaying device status and/or information, a touch panel 83b for inputting an instruction from an operator, a mouse 83c for operating the monitor, and an image acquisition device 83d for acquiring image data from the optical system 88. The input/output device 83 includes: a motor control device 83e for controlling a driving unit 86 such as an XY stage (not shown) of the die supply unit 1, a ZY driving shaft of the mounting head stage, and an XY driving shaft of the substrate recognition camera; and an I/O signal control device 83f that acquires or controls various sensor signals or acquires or controls signals from a signal section 87 of a switch or the like of the lighting device or the like. The optical system 88 includes the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44. The control/operation device 81 acquires necessary data via the bus line 84, performs operation, controls the pickup head 21 and the like, and transmits information to the monitor 83a and the like.
The control unit 8 stores the image data captured by the wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 in the storage device 82 by the image acquisition device 83 d. The positioning of the package region P of the die D and the substrate S and the surface inspection of the die D and the substrate S are performed using the control/operation device 81 by software programmed based on the stored image data. The driving unit 86 is operated by the motor control device 83e based on the positions of the die D and the package region P of the substrate S calculated by the control/calculation device 81 by software. The bare chip D is mounted on the package region P of the substrate S by positioning the bare chip on the wafer by this process and operating the pickup unit 2 and the driving unit of the mounting unit 4. The wafer recognition camera 24, the stage recognition camera 32, and the substrate recognition camera 44 used are of a gradation, color, or the like, and the light intensity is digitized.
Next, a die attach process will be described with reference to fig. 17 to 19. Fig. 17 is a flowchart illustrating a die attach process of the die attach machine of fig. 11. Fig. 18 is a flowchart mainly showing a process of photographing by the wafer recognition camera. Fig. 19 is a flowchart mainly showing a process of photographing by the substrate recognition camera.
In the die attach process of the embodiment, first, as shown in fig. 17, the control unit 8 takes out the wafer ring 14 holding the wafer 11 from the wafer cassette and places the wafer ring on the wafer holding stage 12, and conveys the wafer holding stage 12 to the reference position where the pickup of the die D is performed (wafer loading (step P1)). Next, the control unit 8 performs fine adjustment (alignment) so that the arrangement position of the wafer 11 and the reference position thereof accurately coincide with each other, based on the image acquired by the wafer recognition camera 24.
Next, the control unit 8 moves the wafer holding stage 12 on which the wafer 11 is mounted at a predetermined pitch, and holds the wafer at a horizontal level, thereby placing the die D picked up first at the pick-up position (die transfer (step P2)). The pick-up position of the bare chip D is also the recognition position of the bare chip D by the wafer recognition camera 24. The wafer 11 is inspected for each die by an inspection device such as a prober, and map data indicating good and bad is generated for each die and stored in the storage device 82 of the control unit 8. The judgment of whether the bare chip D to be picked up is a good or a bad is performed by the map data. When the control unit 8 determines that the die D is defective, it moves the wafer holding stage 12 on which the wafer 11 is mounted at a predetermined pitch, and places the die D to be picked up next at the pickup position, skipping the defective die D.
Next, as shown in fig. 18, the control unit 8 sets the illumination output of the wafer recognition camera 24 to a value for die positioning (step S31). The control unit 8 captures an image of the main surface (upper surface) of the bare chip D to be picked up by the wafer recognition camera 24 (step S32). The position of the bare chip D is measured by calculating the amount of positional displacement between the pickup position and the bare chip D as the pickup target from the acquired image (step S33). The control unit 8 moves the wafer holding table 12 on which the wafer 11 is mounted based on the positional deviation amount, and accurately positions the die D to be picked up at the pick-up position (die positioning (step P3)).
Next, as shown in fig. 18, the control unit 8 changes the illumination output of the wafer recognition camera 24 to a value for die crack inspection (step S41). The control unit 8 captures an image of the main surface of the bare chip D to be picked up by the wafer recognition camera 24 (step S42). As described later, the control unit 8 checks the surface shading of the bare chip D from the acquired image, and detects whether or not a region where regular reflection is performed (step S43). When the specular reflection area exists, the control unit 8 moves the wafer holding table 12 in the direction of the specular reflection area (step S44). In the case where the illumination device is mounted on a different drive stage from the wafer recognition camera 24, only the illumination device may be moved. In the case where the lighting device is a tube type oblique light lighting, the affected side may be extinguished. The control section 8 acquires the camera image again. In step S43, die cracking and foreign matter inspection (surface inspection) is performed without the regular reflection region (step P4). Here, when it is determined that there is no problem on the surface of the bare chip D, the control unit 8 proceeds to the next step (step P9 described later), and when it is determined that there is a problem, it performs skip processing or error stop. The step P9 and subsequent steps of skipping the die D by skipping the processing are performed such that the wafer holding stage 12 on which the wafer 11 is mounted is moved at a predetermined pitch, and the die D to be picked up next is placed at the pick-up position.
The control unit 8 places the substrate S in the conveyance path 52 by the substrate supply unit 6 (substrate loading (step P5)). The control unit 8 moves the substrate transport claws 51 that grip and transport the substrate S to the mounting position (substrate transport (step P6)).
Next, as shown in fig. 19, the control unit 8 moves the substrate recognition camera 44 to an imaging position (mounting tag imaging position) of the mounting region P of the mounting object (step S71). The control unit 8 sets the illumination output of the substrate recognition camera 44 to a value for substrate positioning (step S72). The control section 8 captures an image of the substrate S by the substrate recognition camera 44 (step S73). The position of the package region P of the substrate S is measured by calculating the position shift amount from the acquired image (step S74). The control unit 8 moves the substrate S based on the positional deviation amount, and performs positioning (substrate positioning (step P7)) for accurately disposing the mounting region P of the mounting object at the mounting position.
Next, as shown in fig. 17, the control unit 8 performs surface inspection of the package region P of the substrate S based on the image acquired by the substrate recognition camera 44 (step P8). Here, the control unit 8 determines whether or not there is a problem in the surface inspection, and proceeds to the next step (step P9 described later) when it is determined that there is no problem on the surface of the package region P of the substrate S, and when it is determined that there is a problem, visually confirms the surface image, or further performs high-sensitivity inspection, inspection with changed lighting conditions, or the like, and when there is a problem, performs skip processing, and when there is no problem, performs processing of the next step. The skip processing skips the steps after the step P10 of conforming labels to the package region P of the substrate S, and the label is registered as a defective product in the substrate start-up information.
After the die supply unit 1 accurately positions the die D to be picked up at the pick-up position, the control unit 8 picks up the die D from the dicing tape 16 by the pick-up head 21 including the collet 22 (die processing (step P9)) and places the die D on the intermediate stage 31 (step P10). The control unit 8 detects the posture shift (rotational shift) of the die mounted on the intermediate stage 31 by capturing an image of the die by the stage recognition camera 32 (die position inspection (step P11)). When the posture shift is present, the control unit 8 causes the intermediate stage 31 to swivel on a surface parallel to the mounting surface having the mounting position by a swivel drive device (not shown) provided on the intermediate stage 31, thereby correcting the posture shift.
The control unit 8 performs surface inspection of the bare chip D based on the image acquired by the stage recognition camera 32 (step P12). Here, when it is determined that there is no problem on the surface of the bare chip D, the control unit 8 proceeds to the next step (step P13 described later), and when it is determined that there is a problem, it performs skip processing or error stop. The step P13 and subsequent steps of placing the die on a defective tray (not shown) and the die D are skipped, and the wafer holding stage 12 on which the wafer 11 is placed is moved at a predetermined pitch to place the die D to be picked up next at the pickup position.
The control section 8 picks up the bare chip D from the intermediate stage 31 by the mounting head 41 including the collet 42, and mounts the bare chip on the package region P of the substrate S or the bare chip already mounted on the package region P of the substrate S (die bonding ((step P13)).
Next, as shown in fig. 19, the control unit 8 moves the substrate recognition camera 44 to the imaging position of the mounted bare chip D (step S141). The control unit 8 sets the illumination output of the substrate recognition camera 44 to a value for die positioning (step S142). The control unit 8 captures an image of the bare chip D by the substrate recognition camera 44 (step S143). The position of the bare chip D is measured from the acquired image (step S144). After the die D is mounted, the control unit 8 detects whether or not the mounting position is accurate (relative position check of the die and the substrate (step P14)). In this case, the center of the die and the center of the tag are obtained in the same manner as the alignment of the die, and whether the relative position is correct is checked.
Next, the control unit 8 moves the substrate recognition camera 44 to the die crack inspection imaging position (step S151). In the case of a laminated product, the direction in which the offset occurs with lamination to the upper layer is determined in advance. In this case, too, since the warp direction is determined, if the movement amount of the field of view in which the regular reflection does not occur with respect to the warp direction is taught in advance and the movement is initially moved to a position including the offset amount at the time of inspection, the number of times of starting the movement of the field of view after confirming whether the reflection exists can be reduced. The control unit 8 changes the illumination output of the substrate recognition camera 44 to a value for die crack inspection (step S152). The control unit 8 captures an image of the bare chip D by the substrate recognition camera 44 (step S153). As will be described later, the control unit 8 checks the surface shading of the bare chip D from the acquired image, and detects the presence or absence of a region where regular reflection is occurring (step S154). When the regular reflection area exists, the control unit 8 moves the substrate recognition camera 44 in a direction opposite to the regular reflection area (step S155). As shown in a second modification described later, when the illumination device is mounted on a stage that is driven separately from the substrate recognition camera 44, only the illumination device may be moved. In the case where the lighting device is a tube type oblique light lighting, the affected side may be extinguished. The control unit 8 acquires the camera image again. In step S154, if there is no regular reflection region, die cracking and foreign matter inspection (surface inspection of the die D and the substrate S) are performed (step P15). Here, when it is determined that there is no problem on the surface of the bare chip D, the control unit 8 proceeds to the next step (step P9 described later), and when it is determined that there is a problem, it performs skip processing or error stop. In the skip processing, the substrate start-up information is registered as a defective product.
Thereafter, the bare chips D are attached to the package regions P of the substrate S one by one in the same order. When the mounting of one substrate is completed, the substrate S is moved to the substrate carrying-out section 7 by the substrate carrying claw 51 (substrate carrying-in step P16), and the substrate S is delivered to the substrate carrying-out section 7 (substrate unloading step P17).
Thereafter, the bare chips D are peeled off from the dicing tape 16 one by one in the same order (step P9). When the pickup of all the bare chips D except for the defective products is completed, the dicing tape 16, the wafer ring 14, and the like holding the bare chips D in the outer shape of the wafer 11 are unloaded to the wafer cassette (step P18).
Next, a method for measuring the warpage position (regular reflection region) of the bare chip will be described with reference to fig. 20. Fig. 20 (a) is an inspection image of a bare chip. Fig. 20 (b) is a reference image of a bare chip. Fig. 20 (c) is a difference image between the inspection image of fig. 20 (a) and the reference image of fig. 20 (b). Fig. 20 (d) is an image obtained by binarizing the difference image of fig. 20 (c). Fig. 20 (e) is a diagram for explaining a judgment of whether or not a bare chip is warped.
The control unit 8 calculates a difference image by calculating a difference between the inspection image of the bare chip in fig. 20 (a) and the reference image of the bare chip in fig. 20 (b). As shown in fig. 20 (c), the difference image is blackened out except for the regular reflection region, the regular reflection region is whitened out, and the boundary region is blurred. The control unit 8 binarizes the differential image based on a certain gradation threshold value, and obtains an image shown in fig. 20 (d). Four inspection areas shown in fig. 20 (e), for example, are provided near the edge of the image at this time. If the white area in each inspection area is above a certain area threshold, the existence of warpage is judged, and the warpage direction is judged according to the position of the white area. In this case, the lower side warpage of the bare chip is determined.
The surface inspection of the crack may be performed at least at one place of the die supply unit, the intermediate stage, and the mounting stage, which are places where the die position recognition is performed, but it is more preferable to perform the surface inspection at all places. If the surface inspection is performed on the bare chip supply portion, the crack can be detected earlier. If the crack is performed on the intermediate stage, a crack that cannot be detected by the die supply unit or a crack that occurs after the pick-up step (a crack that is not clearly apparent before the mounting step) can be detected before the mounting. In addition, if the process is performed on the mounting table, it is possible to detect a crack (a crack that is not apparent before the mounting process) that cannot be detected by the die supply unit and the intermediate table or a crack that occurs after the mounting process before stacking the next die or before discharging the substrate.
< modification >
In the following, several representative modifications are exemplified. In the following description of the modified example, the same reference numerals as those of the above-described embodiment are used for the portions having the same configuration and functions as those of the portions described in the above-described embodiment. Further, the description in the above embodiments may be appropriately given to the extent that the description of the related portions is not technically contradictory. In addition, some of the above embodiments and all or some of the modifications may be applied in a composite manner within a range that is not technically contradictory.
(first modification)
Fig. 22 is a schematic perspective view showing a substrate recognition camera and an illumination device in the first modification.
In the case of the embodiment, the oblique illumination device 46 is a two-directional oblique tube illumination, but may be a four-directional oblique tube illumination as shown in fig. 22. The oblique illumination device 46 is configured such that an oblique illumination device (not shown) located on the opposite side of the oblique illumination devices 46a to 46c and the substrate recognition camera 44 with respect to the oblique illumination devices 46c and the substrate recognition camera 44 is attached to the side surface of the substrate recognition camera 44. The substrate recognition camera 44 is fixed to a movable portion 45a, the movable portion 45a is movable in the X-axis direction by an X driving portion 45b, and the X driving portion 45b is movable in the Y-axis direction by a Y driving portion 45 c.
As shown in fig. 22 b, when the bare chips D are stacked while being shifted in the Y-axis direction, since direct reflection occurs in the area of upward warpage of the bare chips D on the positive side (right side in the drawing), the control unit 8 moves the substrate recognition camera 44 and the oblique illumination device 46 in the arrow direction (negative side (left side in the drawing)) to capture the bare chips D.
As shown in fig. 22 c, when the bare chips D are stacked while being offset in the X-axis direction, since direct reflection occurs in the area of upward warpage of the bare chips D on the negative side (right side in the drawing), the control section 8 moves the substrate recognition camera 44 and the oblique illumination device 46 in the direction of the arrow (positive side (left side in the drawing)) to take an image of the bare chips D.
(second modification)
Fig. 23 is a schematic perspective view showing a substrate recognition camera and an illumination device in a second modification.
In the case of the embodiment and the first modification, the oblique illumination device 46 is configured to move in the same positional relationship as the substrate recognition camera 44, but may also move independently of the substrate recognition camera 44 as shown in fig. 23. The oblique light tube lighting devices 46a to 46d of the oblique light lighting device 46 are fixed to a movable portion 47a, the movable portion 47a is movable in the X-axis direction by an X driving portion 47b, and the X driving portion 47b is movable in the Y-axis direction by a Y driving portion 47 c. The substrate recognition camera 44 is fixed to a movable portion 45a, the movable portion 45a is movable in the X-axis direction by an X driving portion 45b, and the X driving portion 45b is movable in the Y-axis direction by a Y driving portion 45 c.
(third modification)
Fig. 24 is a schematic perspective view showing a wafer recognition camera and an illumination device in a third modification.
In the case of the embodiment, the illumination device of the wafer recognition camera 24 is the same as the oblique illumination device 46 for illumination with oblique light, but may be the illumination with oblique light in four directions as shown in fig. 24. The oblique illumination device 26 is constituted by oblique tube illumination devices 26a to 26 d. The wafer holding table 12 is fixed to an X drive unit 19b, the X drive unit 19b is movable in the X axis direction, and the X drive unit 19b is movable in the Y axis direction by a Y drive unit 19 c.
The side of the multi-direction oblique light tube illumination, which is affected by the reflected light, can be extinguished.
The invention proposed by the present inventors has been specifically described above based on the embodiments and examples, but the invention is not limited to the examples and modifications described above, and various modifications are of course possible.
For example, in the embodiment, the example of using the two-directional oblique light tube illumination as the oblique light illumination device has been described, but the four-directional oblique light tube illumination may be used, or the unidirectional oblique light tube illumination may be used.
In the embodiment, the warpage position (regular reflection area) of the bare chip is measured by camera image recognition in advance, but the direction of warpage may be detected by a sensor such as a laser displacement system, and the illumination device or the camera may be operated based on the detection result. In addition, a lattice pattern may be projected onto the surface of the bare chip, and the warp direction may be determined based on the disorder of the lattice.
In addition, in the embodiment, the die-appearance inspection recognition is performed after the die-position recognition, but the die-position recognition may also be performed after the die-appearance inspection recognition.
In the embodiment, the DAF is attached to the back surface of the wafer, but the DAF may not be provided.
In the embodiment, the pick-up head and the mounting head each have one, but may have two. In the embodiment, the intermediate stage is provided, but the intermediate stage may not be provided. In this case, the pick-up head and the mounting head may be used in combination.
In the embodiment, the surface of the bare chip is directed upward for mounting, but the back of the bare chip may be directed upward for mounting by turning the front and back of the bare chip after the bare chip is picked up. In this case, the intermediate stage may not be provided. This device is called a flip chip mounter.
In addition, in the embodiment, the mounting head is provided, but the mounting head may not be provided. In this case, the picked-up bare chip is mounted on a container or the like. This device is called a pick-up device. In this case, the surface inspection of the crack may be performed in a container or the like in which the picked-up bare chip is placed.

Claims (16)

1. A semiconductor manufacturing apparatus, characterized in that,
the device is provided with:
an imaging device for imaging the bare chip;
an illumination device that irradiates light to the bare chip at a predetermined angle with respect to an optical axis of the imaging device; and
a control unit for controlling the imaging device and the illumination device,
The predetermined angle is an angle at which light irradiated from the illumination device is not entered into the imaging device even if the light is directly reflected by the bare chip when the bare chip is flat,
the position relation between the camera device and the lighting device is fixed,
the control unit is configured to move at least one of the imaging device and the bare chip such that, when the bare chip is uneven, light irradiated from the illumination device is directly reflected by the bare chip without entering the imaging device and such that the center of the field of view of the imaging device is offset from the center of the bare chip.
2. The semiconductor manufacturing apparatus according to claim 1, wherein,
the control unit is configured to confirm the surface illuminance of the bare chip, and to move at least one of the imaging device and the bare chip when it is determined that the light irradiated from the illumination device is directly reflected by the bare chip and is incident on the imaging device.
3. The semiconductor manufacturing apparatus according to claim 1 or 2, wherein,
means are provided for detecting warpage of the bare chip,
The control unit moves a field of view of the imaging device to either or both of the front and rear sides in the detected warp direction when the warp is detected.
4. The semiconductor manufacturing apparatus according to claim 1, wherein,
the bare chip is a bare chip stacked on top of the bare chip,
the control unit is configured to move a field of view of the imaging device based on the number of stacked layers.
5. The semiconductor manufacturing apparatus according to claim 4, wherein,
the direction in which the field of view of the imaging device is moved is a direction in which the imaging device is moved in either or both of the front and rear directions in the same direction as the direction in which the bare chips are offset to be stacked on the bare chips.
6. The semiconductor manufacturing apparatus according to claim 1, wherein,
the control unit is configured to perform imaging while shifting a center of a field of view of the imaging device from a center of the die so that a region of the imaging device, in which light irradiated from the illumination device is directly reflected by the die and does not enter the imaging device, becomes an entire region of the die, when the light irradiated from the illumination device is directly reflected by the die and enters the imaging device even if the field of view of the imaging device is moved.
7. The semiconductor manufacturing apparatus according to claim 1, wherein,
further comprises a die supply part having a wafer ring holding part for holding the dicing tape to which the die is attached,
the control unit photographs the bare chip attached to the dicing tape using the imaging device and the illumination device.
8. The semiconductor manufacturing apparatus according to claim 1, wherein,
further comprises a mounting head for mounting the bare chip on a substrate or a mounted bare chip,
the control unit photographs a bare chip mounted on the substrate or the bare chip by using the imaging device and the illumination device.
9. The semiconductor manufacturing apparatus according to claim 1, wherein,
the device further comprises:
a pick-up head picking up the bare chip; and
an intermediate stage on which the picked bare chip is mounted,
the control unit photographs a bare chip mounted on the intermediate stage by using the imaging device and the illumination device.
10. A method of manufacturing a semiconductor device, characterized in that,
the method comprises the following steps:
(a) A step of loading a substrate into a semiconductor manufacturing apparatus, the semiconductor manufacturing apparatus comprising: an imaging device for imaging the bare chip; an illumination device that irradiates light to the bare chip at a predetermined angle with respect to an optical axis of the imaging device; and a control unit that controls the imaging device and the illumination device, wherein the predetermined angle is an angle at which light irradiated from the illumination device is not incident on the imaging device even if the light is directly reflected by the bare chip when the bare chip is flat, and wherein the imaging device and the illumination device have a fixed positional relationship, and wherein the control unit is configured to move at least one of the imaging device and the bare chip so that light irradiated from the illumination device is directly reflected by the bare chip without entering the imaging device and so that the center of the field of view of the bare chip and the imaging device is offset when the bare chip is uneven;
(b) A step of carrying in a wafer ring holding part for holding a dicing tape to which a bare chip is attached;
(c) Picking up the bare chip; and
(d) The picked-up bare chip is mounted on the substrate or a bare chip already mounted on the substrate.
11. The method for manufacturing a semiconductor device according to claim 10, wherein,
in the step (c), the picked-up bare chip is mounted on an intermediate stage,
in the step (d), the bare chip mounted on the intermediate stage is picked up.
12. The method for manufacturing a semiconductor device according to claim 10, wherein,
the surface inspection method includes a step (f) of confirming the surface illuminance of the bare chip before the step (c), and performing the surface inspection of the bare chip by shifting the center of the bare chip from the center of the field of view of the imaging device so that the light irradiated from the illumination device is directly reflected by the bare chip and is not incident on the imaging device when it is determined that the light irradiated from the illumination device is directly reflected by the bare chip and is incident on the imaging device.
13. The method for manufacturing a semiconductor device according to claim 10, wherein,
And (g) confirming the surface illuminance of the bare chip after the step (d), wherein when it is determined that the light irradiated from the illumination device is directly reflected by the bare chip and enters the imaging device, the surface inspection of the bare chip is performed by shifting the center of the field of view of the imaging device from the center of the bare chip so that the light irradiated from the illumination device is directly reflected by the bare chip and does not enter the imaging device.
14. The method for manufacturing a semiconductor device according to claim 10, wherein,
and (g) performing surface inspection of the bare chip by shifting the center of the field of view of the imaging device and the center of the bare chip by an amount corresponding to the number of layers in which the bare chip is stacked after the step (d).
15. The method for manufacturing a semiconductor device according to claim 11, wherein,
and (h) after the step (c) and before the step (d), confirming the surface illuminance of the bare chip, and when it is determined that the light irradiated from the illumination device is directly reflected by the bare chip and is incident on the imaging device, performing surface inspection of the bare chip so that the light irradiated from the illumination device is directly reflected by the bare chip and is not incident on the imaging device, the center of the field of view of the imaging device is shifted from the center of the bare chip.
16. The method for manufacturing a semiconductor device according to any one of claims 12, 13, 15, wherein,
even if the bare chip is moved from the center of the imaging device by a field of view, when light irradiated from the illumination device is reflected directly by the bare chip and is still incident on the imaging device, imaging is performed while shifting the center of the field of view of the imaging device from the center of the bare chip so that the area where light irradiated from the illumination device is directly reflected by the bare chip and is not incident on the imaging device becomes the entire area of the bare chip.
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