CN111725071A - 一种硅基结型积累层和缓冲层横向双扩散场效应晶体管及其制作方法 - Google Patents
一种硅基结型积累层和缓冲层横向双扩散场效应晶体管及其制作方法 Download PDFInfo
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Abstract
本发明公开了一种硅基结型积累层和缓冲层横向双扩散场效应晶体管及其制作方法。该器件设置积累介质层，覆盖P型基区与N+漏区之间的区域；在积累介质层上形成外延层，在外延层的左侧端部、右侧端部分别通过离子注入形成两处P型区，并在所述外延层中邻接右端P型区通过离子注入形成N+区；在栅介质层表面形成栅极，栅极与左端P型区邻接；在N+漏区表面的右端区域形成漏极，漏极与右端P型区邻接。本发明通过结型积累层结构可产生电子，使得导通电阻不依赖于掺杂浓度，从而大幅度降低器件的导通电阻。通过缓冲层调制漂移区的电场，使电场分布更均匀，可大幅度提高器件的击穿电压。
Description
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种横向双扩散场效应晶体管。
背景技术
横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，LDMOS)具有易集成、热稳定性好、较好的频率、低功耗、开关速度高等优点，成为智能功率电路和高压器件的核心。随着便携式电源管理和汽车电子产品的市场需求日益增长，LDMOS受到越来越多的关注。
在横向器件设计过程中，需要满足弱化表面电场(Reduced Surface Field，简称RESURF)技术的条件，使得器件的击穿点从表面转移到体内。然而随着器件漂移区长度的增加，器件的击穿电压主要受限于体内纵向耐压能力，即由于横向功率器件的电压饱和效应，器件的击穿电压随着漂移区长度的增加逐渐趋于饱和。此外，随着耐压级别的提高，导通电阻大幅度增加，很大程度上限制了LDMOS器件在高压领域的应用。
发明内容
本发明提出了一种硅基结型积累层和缓冲层横向双扩散场效应晶体管，可获得更好的击穿电压与比导通电阻关系，大幅度提高器件的击穿电压并且降低导通电阻。
本发明的技术方案如下：
一种硅基结型积累层和缓冲层横向双扩散场效应晶体管，包括：
P型硅衬底，P型硅衬底的背面设置有衬底电极；
在P型硅衬底上部左端区域形成的P型基区，在P型基区中形成相应的沟道以及N+源区和P+源区；
在P型硅衬底上部右端区域形成的N型缓冲层，所述N型缓冲层与P型基区存在间隔；N型缓冲层的上部右端区域形成N+漏区；
源极，位于P+源区和N+源区表面；
栅介质层，覆盖N+源区右侧的沟道表面区域；
积累介质层，覆盖P型基区与N+漏区之间的区域；
外延层，覆盖所述积累介质层；
在所述外延层的左侧端部、右侧端部分别通过离子注入形成第一P型区和第二P型区，并在所述外延层中邻接所述第二P型区通过离子注入形成N+区；所述N+区的左端不超出N+漏区左端对应的边界；
在栅介质层表面形成栅极，栅极的右侧邻接第一P型区的左侧；
在N+漏区表面的右端区域形成漏极，漏极的左侧邻接第二P型区以及积累介质层的右侧。
上述外延层可以为N型，也可以为P型，可以轻掺杂或者不掺杂，其浓度低于N+区的掺杂浓度。外延层的材料可以是硅材料或多晶硅。
可选地，所述P型硅衬底的掺杂浓度为1×1014cm-3～1×1015cm-3，所述N型缓冲层的掺杂浓度为5×1014cm-3～5×1015cm-3。
可选地，所述N型缓冲层的长度为整个器件的1/2～1/3，深度为3-20微米。
可选地，所述所述积累介质层的材料为二氧化硅或高K材料。
可选地，所述积累介质层的厚度为0.05-0.2微米。
可选地，所述外延层的掺杂浓度1×1014cm-3～1×1015cm-3。
可选地，所述外延层的厚度为1～3微米。
可选地，所述第一P型区和第二P型区的掺杂浓度为1×1017cm-3～1×1019cm-3。
可选地，所述N+区的掺杂浓度为1×1017cm-3～1×1019cm-3。
上述的硅基结型积累层和缓冲层横向双扩散场效应晶体管的一种制作方法，其特征在于，包括以下步骤：
1)取P型硅衬底，并形成衬底电极；
2)通过离子注入和扩散形成N+源区、P+源区、P型基区、N型缓冲层和N+漏区；
3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成第一P型区、第二P型区以及N+区；
4)在沟道上方形成栅介质层，并淀积金属形成栅极，使得金属与外延层中的第一P型区相连接；
5)在N+漏区上方淀积金属形成漏极，使得金属与外延层中的第二P型区相连接；
6)在器件表面形成钝化层。
本发明技术方案的有益效果如下：
从矛盾源头出发，提出将耐压区域与导通区域分离的思想，通过消除导通电阻对掺杂浓度的依赖关系，可获得更好的击穿电压与比导通电阻关系，大幅度提高器件的击穿电压并且降低导通电阻。
通过缓冲层调制漂移区的电场，使电场分布更均匀，可大幅度提高器件的击穿电压；同时通过结型积累层结构产生电子，调制衬底的电导率，大幅度降低器件的比导通电阻，消除了导通对掺杂浓度的依赖关系；突破了横向器件中RESURF条件的限制，从而可通过降低栅极和漏极之间的掺杂浓度而大幅度高的击穿电压。
本发明中设置两处P型区，使金属与半导体形成良好的欧姆接触。
由于在器件开启时，会在氧化层下方形成电子，但同时会在氧化层上方形成等量的空穴，设置N+区可阻断氧化层上方外延层(10)中的空穴电流。
附图说明
图1为本发明的一个实施例的结构示意图。
图2是本发明的工作原理示意图。
图3是本发明实施例与普通LDMOS的击穿电压的对照示意图。
图4是本发明实施例与普通LDMOS的导通电阻的对照示意图。
附图标号说明：
1-P型硅衬底；2-基区；3-P+源区；4-源极；5-N+源区；6-栅介质层；7-栅极；8-第一P型区；9-积累介质层；10-外延层；11-N+区；12-第二P型区；13-漏极；14-漏区；15-N型缓冲层；16-衬底电极。
具体实施方式
以下结合附图，通过实施例进一步详述本发明。
如图1所示，一种硅基结型积累层和缓冲层横向双扩散场效应晶体管，包括：
P型硅衬底1，其背面形成有衬底电极16；P型硅衬底掺杂浓度的典型值为1×1014cm-3～1×1015cm-3；
在P型硅衬底上形成的P型基区2，基区的浓度由阈值电压决定，在基区中形成相应的沟道以及N+源区5和P+源区3；
在P型硅衬底上形成的N型缓冲层15以及N+漏区14，N型缓冲层的掺杂浓度和深度由器件的耐压决定；N型缓冲层的典型掺杂浓度5×1014cm-3～5×1015cm-3；N型缓冲层的长度为整个器件的1/2～1/3,深度的典型值为3-20微米；
在P+源区与N+源区的表面形成的源极4；
在沟道上方形成的栅介质层6；
在P型基区与N+漏区之间的器件表面形成的积累介质层9，介质层的厚度越小，导通电阻越低，厚度典型值为0.05-0.2微米；介质材料为二氧化硅或高K材料；
在积累介质层上方形成的外延层10，外延层的厚度在1～3微米；外延层的典型掺杂浓度1×1014cm-3～1×1015cm-3，外延层为N型(也可以为P型)；
在外延层上分别进行通过注入形成的第一P型区8、第二P型区12以及N+区11；第一P型区和第二P型区的典型掺杂浓度为1×1017cm-3～1×1019cm-3，N+区的典型掺杂浓度为1×1017cm-3～1×1019cm-3；
栅极7，覆盖栅氧化层且与外延层中的第一P型区8相接；
漏极13，漏极位于漏区上方且与外延层中的第二P型区12相接。
普通横向双扩散晶体管中击穿电压和比导通电阻二者呈现矛盾关系，这是由于高击穿电压需要低的掺杂浓度，而低的掺杂浓度会导致高的导通电阻。而本发明从矛盾源头出发，提出将击穿区域与导通区域分离的思想，如图2所示，通过结型积累层结构可产生电子，使得导通电阻不依赖于掺杂浓度，从而大幅度降低器件的导通电阻；同时通过缓冲层调制漂移区的电场，使电场分布更均匀，可大幅度提高器件的击穿电压。
该器件可按照以下步骤制备：
1)取P型硅衬底，并形成衬底电极；
2)通过离子注入和扩散形成N+源区、P+源区、P型基区、N型缓冲层和N+漏区；
3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成第一P型区、第二P型区以及N+区；
4)在沟道上方形成栅介质层，并淀积金属形成栅极，使得金属与外延层中的第一P型区相连接；
5)在N+漏区上方淀积金属形成漏极，使得金属与外延层中的第二P型区相连接；
6)在器件表面形成钝化层。
经仿真试验，对于N沟道LDMOS，当漂移区长度为20μm时：如图3所示，普通LDMOS的击穿电压仅为230V左右，而采用本发明的结构，可以将器件的击穿电压提高到460V左右，提高了100％；如图4所示，普通LDMOS的比导通电阻为30mΩ.cm2左右，而采用本发明的结构可以将器件的比导通电阻降低到6mΩ.cm2，下降了80％。
当然，本发明中的LDMOS也可以为P沟道，其结构与N沟道LDMOS等同，在此不再赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换的方案也落入本发明的保护范围。
Claims (10)
1.一种硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于，包括：
P型硅衬底(1)，P型硅衬底的背面设置有衬底电极(16)；
在P型硅衬底上部左端区域形成的P型基区(2)，在P型基区中形成相应的沟道以及N+源区(5)和P+源区(3)；
在P型硅衬底上部右端区域形成的N型缓冲层(15)，所述N型缓冲层(15)与P型基区(2)存在间隔；N型缓冲层(15)的上部右端区域形成N+漏区(14)；
源极(5)，位于P+源区(3)和N+源区(5)表面；
栅介质层(6)，覆盖N+源区(5)右侧的沟道表面区域；
积累介质层(9)，覆盖P型基区(2)与N+漏区(14)之间的区域；
外延层(10)，覆盖所述积累介质层(9)；
在所述外延层(10)的左侧端部、右侧端部分别通过离子注入形成第一P型区(8)和第二P型区(12)，并在所述外延层中邻接所述第二P型区(12)通过离子注入形成N+区(11)；所述N+区(11)的左端不超出N+漏区(14)左端对应的边界；
在栅介质层(6)表面形成栅极(7)，栅极(7)的右侧邻接第一P型区(8)的左侧；
在N+漏区(14)表面的右端区域形成漏极(13)，漏极(13)的左侧邻接第二P型区(12)以及积累介质层(9)的右侧。
2.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述P型硅衬底(1)的掺杂浓度为1×1014cm-3～1×1015cm-3，所述N型缓冲层(15)的掺杂浓度为5×1014cm-3～5×1015cm-3。
3.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N型缓冲层(15)的长度为整个器件的1/2～1/3，深度为3-20微米。
4.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述所述积累介质层(9)的材料为二氧化硅或高K材料。
5.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述积累介质层(9)的厚度为0.05-0.2微米。
6.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述外延层(10)的掺杂浓度1×1014cm-3～1×1015cm-3。
7.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述外延层(10)的厚度为1～3微米。
8.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述第一P型区(8)和第二P型区(12)的掺杂浓度为1×1017cm-3～1×1019cm-3。
9.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N+区(11)的掺杂浓度为1×1017cm-3～1×1019cm-3。
10.权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管的制作方法，其特征在于，包括以下步骤：
1)取P型硅衬底，并形成衬底电极；
2)通过离子注入和扩散形成N+源区、P+源区、P型基区、N型缓冲层和N+漏区；
3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成第一P型区、第二P型区以及N+区；
4)在沟道上方形成栅介质层，并淀积金属形成栅极，使得金属与外延层中的第一P型区相连接；
5)在N+漏区上方淀积金属形成漏极，使得金属与外延层中的第二P型区相连接；
6)在器件表面形成钝化层。
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