CN111722137A - Micro-resistance test system based on four-wire method and digital anti-interference circuit - Google Patents

Micro-resistance test system based on four-wire method and digital anti-interference circuit Download PDF

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CN111722137A
CN111722137A CN202010617118.4A CN202010617118A CN111722137A CN 111722137 A CN111722137 A CN 111722137A CN 202010617118 A CN202010617118 A CN 202010617118A CN 111722137 A CN111722137 A CN 111722137A
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CN111722137B (en
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苏良勇
范麟
戚园
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Chongqing Southwest Integrated Circuit Design Co ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/389Measuring internal impedance, internal conductance or related variables
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08Measuring resistance by measuring both voltage and current

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Abstract

The invention discloses a micro-resistance testing system and a digital anti-interference circuit based on a four-wire method; a digital anti-interference circuit for micro-resistance test based on a four-wire method comprises an addition counter, a phase shifter, a multiplier and an integrating circuit; the method is characterized in that: the addition counter generates a periodic ramp signal which is stepped into one according to the sampling clock frequency and outputs the periodic ramp signal to the phase shifter; the phase shifter is used for outputting a reference signal to the multiplier; the phase shifter selects two signal values with the phase difference of 180 degrees as preset digital values according to the periodic ramp signal output by the addition counter, and the preset digital values are between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter reaches a preset digital value, the output of the phase shifter is overturned; adjusting a preset digital value to adjust the phase of the reference signal; the multiplier performs product operation on the reference signal and the voltage signal acquired on line and outputs the product to the integrating circuit; the invention is suitable for the on-line test of the internal resistance of various batteries.

Description

Micro-resistance test system based on four-wire method and digital anti-interference circuit
Technical Field
The invention relates to battery testing, in particular to a micro-resistance testing system based on a four-wire method and a digital anti-interference circuit.
Background
Under normal conditions, the more sufficient the electric quantity stored by the storage battery is, the smaller the internal resistance is, and vice versa. In addition, the storage battery may be deteriorated after long-term use, and the deteriorated internal resistance value of the battery is larger than the normal internal resistance value of the battery under the condition that the batteries are charged to the same voltage, and the battery capacity is reduced accordingly. The SoH description is generally used to measure the degree of battery degradation, which is the ratio of the measured capacity to the nominal capacity, and characterizes the aging degree of the battery. By comparing the internal resistance values of the entire group of secondary batteries, the cells in the battery pack in which deterioration has occurred can be found out. When the internal resistance value is increased by more than 20% from the reference value, the performance of the battery is degraded by one step, so that corrective or replacement measures should be taken for the unit cell.
The battery internal resistance test method mainly comprises a direct current internal resistance measurement method and an alternating current internal resistance measurement method. The direct current internal resistance measurement method is not suitable for on-line testing because a large constant current direct current needs to be forced to pass through the battery in a short time, and the polarization phenomenon can occur inside the battery. The alternating current internal resistance measuring method adopts alternating current with the frequency of 1KHz to be injected into the storage battery, obtains the internal resistance value of the battery by monitoring and measuring the voltage at two ends of the battery, and is suitable for online testing.
Most of internal resistance testers in the current market are built by discrete components, most of sampling simulation schemes of high-precision internal resistance testers have high debugging difficulty, high cost and large volume and power consumption. The internal resistance tester adopting a digital scheme in the market requires higher AD sampling frequency in order to ensure the measurement precision, the AD sampling frequency is improved, and the power is correspondingly increased. The actual application condition of the battery mainly adopts a multi-group battery series-parallel connection structure, if each battery module is subjected to online detection, the volume and the power consumption of the internal resistance tester cannot meet the requirements, and no mature scheme exists in the market at the present stage.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a micro-resistance testing system based on a four-wire method and a digital anti-interference circuit.
The technical scheme of the invention is as follows: a digital anti-interference circuit for micro-resistance test based on a four-wire method comprises an addition counter, a phase shifter, a multiplier and an integrating circuit; the method is characterized in that:
the addition counter is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency and outputting the periodic ramp signal to the phase shifter;
the phase shifter is used for outputting a reference signal to the multiplier; the phase shifter selects two signal values with the phase difference of 180 degrees as preset digital values according to the periodic ramp signal output by the addition counter, and the preset digital values are between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter reaches a preset digital value, the output of the phase shifter is inverted, and the reference signal is a square wave signal; adjusting a preset digital value to adjust the phase of the reference signal;
the multiplier is used for performing product operation on the reference signal and the voltage signal acquired on line and outputting the product to the integrating circuit;
the integration circuit is used for accumulating the product term output by the multiplier, when the accumulation times reach 2mAfter one period, outputting data; and truncating the lower m bits of data in the output data to realize 2 of the product term accumulated value output by the multipliermSub-averaging; the value range of m is determined according to the maximum time allowed by the system to calculate.
The invention adopts orthogonal interference elimination method, and adopts vector multiplier and integrator as phase sensitive correlator, which can automatically eliminate electromagnetic interference signal.
According to the preferable scheme of the digital anti-interference circuit for the micro-resistance test based on the four-wire method, the data output by the integrating circuit in a half period is as follows:
Figure BDA0002564162400000021
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2ncounting the total collection points of the A/D converter in a signal period;
tau is the angle of two adjacent acquisition points of the A/D converter in one signal period;
phi is pressCalculating the total step number of voltage signals acquired on line after the reference signals lag according to the step angle tau; the angle of the reference signal to be adjusted relative to the input signal
Figure BDA0002564162400000031
SπThe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
According to the preferable scheme of the digital anti-interference circuit for the micro-resistance test based on the four-wire method, when the phase shifter is adjusted to enable the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance to be 90 degrees, the data S output in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between a current driving wire and a voltage monitoring wire in the four-wire method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is the output value of the integrating circuit (6) in a half period;
eta is a constant obtained by calculation after system calibration.
The second technical scheme of the invention is that the micro-resistance test system based on the four-wire method comprises an operational amplifier, an analog filter, an A/D conversion circuit, a V/I converter, a D/A conversion circuit, a cosine table and a digital anti-interference circuit; the method is characterized in that: the digital anti-interference circuit comprises an addition counter, a phase shifter, a multiplier and an integrating circuit;
the adder counter is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency, serving as an address signal of the cosine table and outputting the address signal to the cosine table; simultaneously outputting the periodic ramp signal to the phase shifter;
the cosine table is used for generating a digital sine wave signal in a table look-up mode and outputting the digital sine wave signal to the D/A conversion circuit;
D/A conversion circuit carries out digital-to-analog conversion on the received signal and outputs the signal to a V/I converter;
the V/I converter is connected with the positive electrode and the negative electrode of the battery cell through a capacitor and is used for converting sine wave voltage signals output by the D/A conversion circuit into constant alternating current signals and injecting the constant alternating current signals into the battery cell;
the operational amplifier is connected with the positive electrode and the negative electrode of the battery cell through a third capacitor and a fourth capacitor respectively; the operational amplifier collects alternating voltage signals of the third capacitor and the fourth capacitor, amplifies the alternating voltage signals and outputs the amplified alternating voltage signals to the analog filter;
the analog filter filters the received signal and outputs the signal to the A/D conversion circuit;
the A/D conversion circuit carries out analog-to-digital conversion on the received signal and outputs the signal to the multiplier;
the phase shifter is used for outputting a reference signal to the multiplier; the phase shifter selects two signal values with the phase difference of 180 degrees as preset digital values according to the periodic ramp signal output by the addition counter, and the preset digital values are between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter reaches a preset digital value, the output of the phase shifter is inverted, and the reference signal is a square wave signal; adjusting a preset digital value to adjust the phase of the reference signal;
the multiplier is used for carrying out product operation on the reference signal and the signal output by the A/D conversion circuit and outputting the product to the integrating circuit;
the integration circuit is used for accumulating the product term output by the multiplier, when the accumulation times reach 2mAfter one period, outputting data; and truncating the lower m bits of data in the output data to realize 2 of the product term accumulated value output by the multipliermSub-averaging; the value range of m is determined according to the maximum time allowed by the system to calculate.
The invention adopts an alternating current internal resistance measurement method, the frequency of a current signal is alternating current, and the internal resistance value of the battery is obtained by monitoring and measuring the voltages at two ends of the battery, so that the method is suitable for online testing. However, the special electromagnetic interference phenomenon when alternating current excitation is adopted can cause that the measured value is larger when the internal resistance is low, and meanwhile, the phase deviation occurs between the reference signal and the signal to be measured; in addition, if the sampling rate of the AD adopts an integral multiple frequency of the excitation signal, in order to reduce the calculation error, the sampling frequency of the AD, that is, the number of sampling points in the signal period, needs to be increased as much as possible, but the sampling rate requirement of the AD is increased, and the power consumption of the whole system is also greatly increased. According to the invention, through a digital anti-interference design scheme, the coupling influence between a current driving line and a voltage measuring line in a four-wire method is reduced by utilizing an orthogonal elimination method and an AD non-integral multiple sampling frequency, under the condition of the interference of electromagnetic coupling in the four-wire method, the test value within 0.5 milliohm cannot be obviously increased, the sampling frequency and the overall power consumption of the AD are reduced, the practicability and the usability of the circuit are enhanced, and the digital chip integration is facilitated. The accuracy of the measurement is still maintained in case of disturbances. The method is mainly used for on-line internal resistance test of the battery, can evaluate the aging condition of the battery, and can replace the deteriorated battery in time. Because the digital anti-interference design method of the micro resistor is adopted, electromagnetic interference signals are eliminated, the testing precision is improved, the volume and the power consumption are reduced, and conditions are created for chip integration.
According to the preferable scheme of the micro-resistance testing system based on the four-wire method, the digital filter is arranged between the A/D conversion circuit and the multiplier, and the digital filter carries out filtering processing on the signal output by the A/D conversion circuit and outputs the signal to the multiplier.
According to the preferable scheme of the micro-resistance testing system based on the four-wire method, the data output by the integrating circuit in a half period is as follows:
Figure BDA0002564162400000051
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2nfor A/D conversionThe total collection points of the circuit in one signal period;
tau is the angle of two adjacent acquisition points of the A/D conversion circuit in one signal period;
phi is the total step number of voltage signals acquired on line after the reference signals are lagged according to the step angle tau; the angle of the reference signal to be adjusted relative to the input signal
Figure BDA0002564162400000052
SπThe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
According to the preferable scheme of the micro-resistance testing system based on the four-wire method, when the phase shifter is adjusted to enable the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance to be 90 degrees, the data S output in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between a current driving wire and a voltage monitoring wire in the four-wire method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is an output value of the integrating circuit in a half period;
eta is a constant obtained by calculation after system calibration.
According to the preferable scheme of the micro-resistance testing system based on the four-wire method, the sampling clock frequency of the A/D conversion circuit is as follows:
Figure BDA0002564162400000061
wherein:
2nthe total collection points of the A/D conversion circuit in a signal period are counted;
finthe frequency of the voltage signal collected on line is usually 1 KHz;
k is a down-conversion factor determined according to the highest allowable sampling frequency of the A/D conversion circuit.
The micro-resistance testing system and the digital anti-interference circuit based on the four-wire method have the beneficial effects that: the invention reduces the volume, reduces the power consumption, improves the measurement precision, provides a practical product scheme for monolithic integration, realizes the real-time detection of the internal resistance of each battery of the battery pack, can monitor the internal resistance and the change condition of the battery in real time, evaluates the aging condition of the battery, replaces the degraded battery in time, meets the self-power supply requirement of the battery, provides a foundation for chip integration, has greater advantages than the traditional online internal resistance tester, and can be widely used for testing various batteries, in particular for testing batteries of electric automobiles and electric motorcycles.
Drawings
Fig. 1 is a schematic circuit block diagram of a four-wire method-based micro-resistance testing system according to the present invention.
Fig. 2 is a schematic diagram of the principle of the improved quadrature interference cancellation method.
Fig. 3 is a schematic diagram of the calculation of the orthogonal interference cancellation method.
Detailed Description
Referring to fig. 1 to fig. 3, a digital anti-interference circuit for micro-resistance test based on a four-wire method includes an addition counter 9, a phase shifter 8, a multiplier 7 and an integrating circuit 6; the addition counter 9 is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency and outputting the periodic ramp signal to the phase shifter 8;
the phase shifter 8 is used for outputting a reference signal to the multiplier 7; the phase shifter 8 selects two signal values with a phase difference of 180 degrees as a preset digital value according to the periodic ramp signal output by the addition counter 9, and the preset digital value is between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter 9 reaches a preset digital value, the output of the phase shifter 8 is inverted, and the reference signal is a square wave signal with the amplitude equal to +/-1; adjusting a preset digital value to adjust the phase of the reference signal;
if the clock cycle of the D/a conversion circuit 11 is 512KHz and the signal cycle is 1KHz, the D/a conversion circuit 11 will output 512 different values in one cycle, so the number of bits at the output end of the addition counter 9 and the input end of the cosine table 11 is 9 bits, the minimum and maximum values of the periodic ramp signal generated by the addition counter 9 are 0 and 511, respectively, two signal values 0+ Δ and 255+ Δ with a phase difference of 180 ° are selected as preset digital values, Δ is a phase shifter adjustment value, the corresponding angle is 0-90 °, and the range is 0-127. Assuming that Δ is 25, when the periodic ramp signal output from the addition counter 9 reaches 25, the reference signal goes from-1 to +1, and when 255+ Δ is 275, the output of the phase shifter 8 is inverted, and the reference signal goes from +1 to-1.
The multiplier 7 is used for performing product operation on the reference signal and the voltage signal acquired on line and outputting the product to the integrating circuit 6;
the integration circuit 6 is used for accumulating the product term output by the multiplier, when the accumulation times reach 2mAfter one period, outputting data; and truncating the lower m bits of data in the output data to realize 2 of the product term accumulated value output by the multipliermSub-averaging; the value range of m is determined according to the maximum time allowed by the system to calculate.
Maximum time TGeneral assembly=2mT, T is the period of the online collected voltage signal; e.g. T1 ms, TGeneral assembly0.128s, then m is log (T)General assembly/T)/log2=2/log2=7。
If taking TGeneral assembly64ms, m is 6, and there is a total of 26The 64 cycles participate in the accumulation calculation.
When the number of times of integration reaches 64 cycles, the lower 6 bits of data are cut off from the data output by the integrating circuit, and the 64 times of average of the accumulated value of the product term output by the multiplier is realized.
The data output by the integrating circuit 6 in a half cycle is:
Figure BDA0002564162400000081
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2nthe total collection points of the A/D conversion circuit in a signal period are counted;
tau is the angle of two adjacent acquisition points of the A/D conversion circuit in one signal period;
phi is the total step number of voltage signals acquired on line after the reference signals are lagged according to the step angle tau; the angle of the reference signal to be adjusted relative to the input signal
Figure BDA0002564162400000082
SπThe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
When the phase shifter 8 is adjusted to ensure that the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance is 90 degrees, the data S output in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between the current driving line and the voltage monitoring line in a four-line method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is the output value of the integrating circuit 6 in a half cycle;
eta is a constant obtained by calculation after system calibration.
Embodiment 2, a micro-resistance test system based on four-wire method, including an operational amplifier 1, an analog filter 2, an a/D conversion circuit 3, a V/I converter 12, a D/a conversion circuit 11, a cosine table 10 and a digitized anti-interference circuit; the digital anti-interference circuit comprises an addition counter 9, a phase shifter 8, a multiplier 7 and an integrating circuit 6;
the addition counter 9 is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency of the A/D conversion circuit 3, serving as an address signal of the cosine table 10 and outputting the address signal to the cosine table 10; while outputting the periodic ramp signal to the phase shifter 6;
the cosine table 10 is used for generating a digital sine wave signal in a table look-up manner and outputting the digital sine wave signal to the D/A conversion circuit 11;
the D/a conversion circuit 11 performs digital-to-analog conversion on the received signal, and outputs the signal to the V/I converter 12;
the V/I converter 12 is connected to the positive electrode and the negative electrode of the battery cell through a capacitor, and is configured to convert the sine wave voltage signal output by the D/a conversion circuit 11 into a constant alternating current signal, and inject the constant alternating current signal into the battery cell;
the operational amplifier 1 is respectively connected with the positive electrode and the negative electrode of the battery cell through a third capacitor and a fourth capacitor; the operational amplifier 1 collects alternating voltage signals of a third capacitor and a fourth capacitor, amplifies the alternating voltage signals and outputs the amplified alternating voltage signals to the analog filter 2;
the analog filter 2 filters the received signal and outputs the signal to the A/D conversion circuit 3;
the A/D conversion circuit 3 performs analog-to-digital conversion on the received signal and outputs the signal to the multiplier 7;
the phase shifter 8 is used for outputting a reference signal to the multiplier 7; the phase shifter 8 selects two signal values with a phase difference of 180 degrees as a preset digital value according to the periodic ramp signal output by the addition counter 9, and the preset digital value is between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter 9 reaches a preset digital value, the output of the phase shifter 8 is inverted, and the reference signal is a square wave signal with the amplitude of +/-1; adjusting a preset digital value to adjust the phase of the reference signal;
the multiplier 7 is used for performing product operation on the reference signal and the signal output by the A/D conversion circuit 3 and outputting the product to the integrating circuit 6;
the integration circuit 6 is used for accumulating product terms output by the multiplier, 2mAfter one period, outputting data, and eliminating low m bits of data to realize 2 of product term accumulated value output by multipliermSub-averaging to eliminate electromagnetic interference signals; and determining the value range of m according to the maximum time allowed to be calculated by the system. T isGeneral assembly=2mT, T is the period of the voltage signal collected online.
The internal resistance tester adopts a Kelvin four-wire method to test the internal resistance of the battery. The 1KHz AC constant current source signal generated by the internal V/I converter generates weak voltage signals through two ends of the battery, and the weak voltage signals are amplified by the instrument operational amplifier and then sent to the A/D converter for sampling. The capacitance value of the capacitor C1 is related to the current Imax of the current source, the highest voltage Umax that the current source can provide, and the frequency f of the signal, and the capacitance value of the capacitor C1 is selected according to the following formula.
Figure BDA0002564162400000101
In a specific embodiment, the circuit of the V/I converter adopts a Howland constant current source circuit, a single power supply is adopted for supplying power, the input and the output are blocked by capacitors, therefore, a direct current working point is not required to be provided for the V/I converter, and the output can be connected with a battery with high voltage.
In the specific embodiment, a digital filter 4 is provided between the a/D conversion circuit 3 and the multiplier 7, and the digital filter 4 performs filtering processing on the signal output from the a/D conversion circuit 3 and outputs the signal to the multiplier 7.
In the specific embodiment, the filter is a fully differential four-order triangular band-pass filter formed by connecting two differential operational amplifiers in series, and the filter structure adopts an MFB type infinite gain topological structure (or Rauch topology), so that the filter has small influence on parameter change of element values, and has the characteristics of simple structure and large sideband suppression. The capacitance value of the capacitor is reduced by adjusting the size of the resistor, and the area of the chip is reduced.
The data output by the integrating circuit 6 in a half cycle is:
Figure BDA0002564162400000111
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2ncounting the total collection points of the A/D converter in a signal period;
tau is the angle of two adjacent acquisition points of the A/D converter in one signal period;
phi is the total step number of voltage signals acquired on line after the reference signals are lagged according to the step angle tau; the angle of the reference signal to be adjusted relative to the input signal
Figure BDA0002564162400000112
SπThe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
When the phase shifter 8 is adjusted to ensure that the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance is 90 degrees, the data S output in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between the current driving line and the voltage monitoring line in a four-line method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is the output value of the integrating circuit 6 in a half cycle;
eta is a constant obtained by calculation after system calibration.
In a specific embodiment, the sampling clock frequency of the a/D conversion circuit (3) is:
Figure BDA0002564162400000113
wherein:
2nthe total number of acquisition points of the A/D conversion circuit 3 in a signal period;
finthe frequency of the voltage signal collected on line is usually 1 KHz;
k is a down-conversion factor determined according to the highest allowable sampling frequency of the a/D conversion circuit 3.
If n is 8 and k is 5, then fsThe a/D conversion circuit 3 will have 2 in 360 ° range, 51.2KHznThe angular difference between acquisition points is 360 °/256 ═ 1.40625 °, requiring 5 cycles to traverse 2n different angle acquisition points. Although the sampling frequency is only 51.2KHz, the number of acquisition points is increased to 256, and the number of the acquisition points is increased by nearly 5 times compared with the integral multiple sampling frequency.
In order to improve the phase debugging precision of the reference signal, the sampling frequency of the AD adopts the non-integral multiple frequency of the signal frequency of the driving current, under the condition of not improving the sampling frequency of the AD, the number of points acquired by the AD within the range of 360 degrees can be increased, the phase debugging precision of the reference signal is improved, the error is reduced, and the error is as follows:
Figure BDA0002564162400000121
wherein tau is the angle difference of two adjacent sampling points,
Figure BDA0002564162400000122
by debugging, the error value can be controlled at
Figure BDA0002564162400000123
Within a range of values.
Figure BDA0002564162400000124
The angle at which the reference signal needs to be adjusted relative to the input signal,
Figure BDA0002564162400000125
from the above analysis, it is found that the larger n is, the smaller τ is.
For example, suppose Vo(i τ) ═ sin (i τ), take
Figure BDA0002564162400000126
n is 8, the number of AD collected is 2n256, then Φ is 60 ° × 256/360 ° ≈ 43 ± 2.2%.
For the application of the vehicle battery, the voltage of the positive end and the negative end of the battery pack is as high as 24V, when the electrode of the battery contacts with the tester, the tester can bear the instantaneous high voltage, and the battery can generate surge current in the running process, so the input end of the operational amplifier 1 is provided with the amplitude limiting protection diodes D1 and D2.
Because the internal resistance of the storage battery is much smaller than the resistance of the connected lead, in order to avoid the influence of the testing precision of the most internal resistance of the lead resistance, the internal resistance tester adopts a Kelvin four-wire method to test the internal resistance of the battery. An internal V/I converter generates a 1KHz alternating current constant current source signal which is connected to electrodes at two ends of a battery through a capacitor C1, the current flows through two ends of the battery to generate weak voltage signals, and the weak voltage signals are amplified by a high-gain operational amplifier 1 and filtered by an analog filter 2 and then are sent to an A/D converter 3 for sampling. The high-gain operational amplifier 1 adopts an instrument three-operational-amplifier structure, the first-stage double operational amplifier provides extremely high input impedance, and the second-stage operational amplifier provides extremely high common-mode rejection. The operational amplifier and the resistor used in the amplifier circuit adopt a completely symmetrical structure, so that the direct current offset under the static condition of the operational amplifier can be reduced, and the common mode noise of two ends of the battery under the condition of normal operation can be reduced.
The V/I converter 12 adopts a single power supply scheme, i.e., self-powered by a battery; the voltage of the battery which can be borne by the circuit depends on the withstand voltage of the DC blocking capacitor. By adopting the scheme, the signal DC offset voltage at the input end and the battery voltage at the output end can not influence the working state of the V/I converter, and the chip integration is easy.
The working principle of the invention is as follows:
according to the invention, an address signal is provided for a cosine table 10 through an addition counter 9, the cosine table 10 generates a digital sine wave signal in a lookup table mode and outputs the digital sine wave signal to a D/A conversion circuit 11; then a sine wave current signal is output through a V/I converter 12, the current signal generates a voltage signal through the internal resistance of a storage battery, the voltage signal is processed by a high-gain operational amplifier 1, an analog filter 2, an A/D converter 3 and a digital filter 4, meanwhile, an addition counter 9 and a phase shifter 8 are used for outputting a reference signal, after the product operation of the reference signal and the acquired voltage signal is carried out, the integration operation of a plurality of periods is carried out through an integrator, and the internal resistance of the battery is obtained through the calibration parameters of the voltage and the resistance.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims (8)

1. A micro-resistance test digital anti-interference circuit based on a four-wire method comprises an addition counter (9), a phase shifter (8), a multiplier (7) and an integrating circuit (6); the method is characterized in that:
the addition counter (9) is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency and outputting the periodic ramp signal to the phase shifter (8);
the phase shifter (8) is used for outputting a reference signal to the multiplier (7); the phase shifter (8) selects two signal values with the phase difference of 180 degrees as preset digital values according to the periodic ramp signal output by the addition counter (9), and the preset digital values are between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter (9) reaches a preset digital value, the output of the phase shifter (8) is inverted, and the reference signal is a square wave signal; adjusting a preset digital value to adjust the phase of the reference signal;
the multiplier (7) is used for performing product operation on the reference signal and the voltage signal acquired on line and outputting the product to the integrating circuit (6);
the integration circuit (6) is used for accumulating the product term output by the multiplier whenThe accumulated times reach 2mAfter one period, outputting data; and truncating the lower m bits of data in the output data to realize 2 of the product term accumulated value output by the multipliermSub-averaging; the value range of m is determined according to the maximum time allowed by the system to calculate.
2. The four-wire method-based digital anti-jamming circuit for micro-resistance test according to claim 1, is characterized in that: the data output by the integrating circuit (6) in a half period is as follows:
Figure FDA0002564162390000011
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2nthe total collection points of the A/D conversion circuit in a signal period are counted;
tau is the angle of two adjacent acquisition points of the A/D conversion circuit in one signal period;
phi is the total step number of voltage signals acquired on line after the reference signals are lagged according to the step angle tau;
Sπthe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
3. The four-wire method-based digital anti-jamming circuit for micro-resistance test according to claim 1, is characterized in that: when the phase shifter (8) is adjusted to ensure that the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance is 90 degrees, the data S output by the integrating circuit (6) in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between a current driving line and a voltage monitoring line in a four-line method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is data output by the integrating circuit (6) in a half period;
eta is a constant obtained by calculation after system calibration.
4. A micro-resistance test system based on a four-wire method comprises an operational amplifier (1), an analog filter (2), an A/D conversion circuit (3), a V/I converter (12), a D/A conversion circuit (11), a cosine table (10) and a digital anti-interference circuit; the method is characterized in that: the digital anti-interference circuit comprises an addition counter (9), a phase shifter (8), a multiplier (7) and an integrating circuit (6);
the addition counter (9) is used for generating a periodic ramp signal which is stepped into one according to the sampling clock frequency, serving as an address signal of the cosine table (10) and outputting the address signal to the cosine table (10); simultaneously outputting the periodic ramp signal to a phase shifter (6);
the cosine table (10) is used for generating a digital sine wave signal in a table look-up mode and outputting the digital sine wave signal to the D/A conversion circuit (11);
the D/A conversion circuit (11) performs digital-to-analog conversion on the received signal and outputs the signal to the V/I converter (12);
the V/I converter (12) is connected with the positive pole and the negative pole of the battery cell through a capacitor and is used for converting the sine wave voltage signal output by the D/A conversion circuit (11) into a constant alternating current signal and injecting the constant alternating current signal into the battery cell;
the operational amplifier (1) is respectively connected with the positive electrode and the negative electrode of the battery cell through a third capacitor and a fourth capacitor; the operational amplifier (1) collects alternating current voltage signals of the third capacitor and the fourth capacitor, amplifies the alternating current voltage signals and outputs the amplified alternating current voltage signals to the analog filter (2);
the analog filter (2) filters the received signal and outputs the signal to the A/D conversion circuit (3);
the A/D conversion circuit (3) performs analog-to-digital conversion on the received signal and outputs the signal to the multiplier (7);
the phase shifter (8) is used for outputting a reference signal to the multiplier (7); the phase shifter (8) selects two signal values with the phase difference of 180 degrees as preset digital values according to the periodic ramp signal output by the addition counter (9), and the preset digital values are between the maximum value and the minimum value of the periodic ramp signal; when the periodic ramp signal output by the addition counter (9) reaches a preset digital value, the output of the phase shifter (8) is inverted, and the reference signal is a square wave signal; adjusting a preset digital value to adjust the phase of the reference signal;
the multiplier (7) is used for multiplying the reference signal by the signal output by the A/D conversion circuit (3) and outputting the signal to the integrating circuit (6);
the integration circuit (6) is used for accumulating the product term output by the multiplier when the accumulation times reach 2mAfter one period, outputting data; and truncating the lower m bits of data in the output data to realize 2 of the product term accumulated value output by the multipliermSub-averaging; the value range of m is determined according to the maximum time allowed by the system to calculate.
5. The four-wire method-based micro-resistance testing system according to claim 4, wherein: a digital filter (4) is provided between the A/D conversion circuit (3) and the multiplier (7), and the digital filter (4) performs filtering processing on the signal output by the A/D conversion circuit (3) and outputs the signal to the multiplier (7).
6. The four-wire method-based micro-resistance testing system according to claim 4, wherein: the data output by the integrating circuit (6) in a half period is as follows:
Figure FDA0002564162390000041
s is an output value obtained by multiplying and integrating the online acquired voltage signal by a reference signal within the range of 0-180 degrees, and is in a direct proportion relation with the resistance value of the internal resistance;
2nthe total collection points of the A/D conversion circuit in a signal period are counted;
tau is the angle of two adjacent acquisition points of the A/D conversion circuit in one signal period;
phi is the total step number of voltage signals acquired on line after the reference signals are lagged according to the step angle tau;
Sπthe integral value of the voltage signal collected on line from 0 to 180 degrees;
SAan integral value of a rising edge of a voltage signal collected on line from a reference signal to 180 degrees;
SBthe integral value of the voltage signal collected on line from 0 DEG to the rising edge of the reference signal is obtained;
Vo(i τ) is the discrete signal received at the signal input of the multiplier.
7. The four-wire method-based micro-resistance testing system according to claim 4, wherein: when the phase shifter (8) is adjusted to ensure that the phase difference between the reference signal and the voltage digital signal of the on-line acquired battery internal resistance is 90 degrees, the data S output by the integrating circuit (6) in a half period is in direct proportion to the resistance value of the resistor and is irrelevant to an interference signal generated by electromagnetic coupling between a current driving line and a voltage monitoring line in a four-line method;
R=S*η
wherein:
r is the internal resistance value of the battery;
s is the output value of the integrating circuit (6) in a half period;
eta is a constant obtained by calculation after system calibration.
8. The four-wire method-based micro-resistance testing system according to claim 4, wherein: the sampling clock frequency of the A/D conversion circuit (3) is as follows:
Figure FDA0002564162390000051
wherein:
2nthe total collection point number of the A/D conversion circuit (3) in a signal period;
finis the voltage signal frequency collected on line;
k is a down-conversion factor determined according to the highest allowable sampling frequency of the A/D conversion circuit (3).
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