CN111710293A - Shift register and driving method thereof, driving circuit and display device - Google Patents

Shift register and driving method thereof, driving circuit and display device Download PDF

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Publication number
CN111710293A
CN111710293A CN202010683132.4A CN202010683132A CN111710293A CN 111710293 A CN111710293 A CN 111710293A CN 202010683132 A CN202010683132 A CN 202010683132A CN 111710293 A CN111710293 A CN 111710293A
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terminal
control signal
node
light
clock signal
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CN202010683132.4A
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CN111710293B (en
Inventor
刘伟星
王铁石
秦纬
徐智强
张春芳
滕万鹏
李小龙
郭凯
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The embodiment of the invention provides a shift register, a driving method thereof, a driving circuit and a display device, relates to the technical field of display, solves the problem that two shift registers are required to output scanning signals and light-emitting control signals respectively, and solves the problem that the frequency of the light-emitting control signals provided by the shift registers is low. The first shift register is configured to shift a first scan signal input from the scan signal input terminal by one pulse of a clock signal provided from the first clock signal terminal to output a second scan signal at the scan signal output terminal; the second shift register is configured to shift the first light emission control signal input by the light emission control signal input terminal by one pulse of the clock signal provided by the first clock signal terminal to output a second light emission control signal at the light emission control signal output terminal; the second light emission control signal includes a clock signal; the active level signal in the second scan signal is earlier than the clock signal in the second light emission control signal by two pulses.

Description

Shift register and driving method thereof, driving circuit and display device
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a driving method thereof, a driving circuit and a display device.
Background
Electroluminescent display devices have the advantages of self-luminescence, low power consumption, wide viewing angle, fast response speed, and high contrast, and thus become the mainstream trend of current display devices.
Disclosure of Invention
Embodiments of the present invention provide a shift register, a driving method thereof, a driving circuit, and a display device, which solve the problem that two shift registers are required to output a scan signal and a light emission control signal respectively, and solve the problem that the frequency of the light emission control signal provided by the shift register is low.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect of embodiments of the present invention, a shift register is provided, including: a first shift register; the first shift register is connected with a first clock signal terminal, a scanning signal input terminal and a scanning signal output terminal, and is configured to shift a first scanning signal input by the scanning signal input terminal by one pulse of a clock signal provided by the first clock signal terminal to output a second scanning signal at the scanning signal output terminal; a second shift register connected to the first clock signal terminal, the light emission control signal input terminal, and the light emission control signal output terminal, and configured to shift the first light emission control signal input by the light emission control signal input terminal by one pulse of the clock signal provided by the first clock signal terminal to output a second light emission control signal at the light emission control signal output terminal; the second light emission control signal includes the clock signal; wherein an active level signal in the second scan signal is two pulses earlier than the clock signal in the second light emission control signal.
Optionally, the first shift register includes a light-emitting control signal input circuit, a first light-emitting control signal output circuit, a light-emitting control signal control circuit, and a second light-emitting control signal output circuit; the light-emitting control signal input circuit is connected with a light-emitting control signal input end, a second clock signal end and a first node, and is configured to transmit a first light-emitting control signal input by the light-emitting control signal input end to the first node under the control of the second clock signal end; the first light emitting control signal output circuit is connected with the first node, the first clock signal terminal and a light emitting control signal output terminal, and is configured to transmit a clock signal provided by the first clock signal terminal to the light emitting control signal output terminal under the control of the first node to output a second light emitting control signal at the light emitting control signal output terminal; the light emitting control signal control circuit is connected with a first node, a first clock signal terminal, a second voltage terminal and a second node, is configured to transmit a clock signal provided by the second clock signal terminal to the second node under the control of the first node, and is further configured to transmit a voltage of the second voltage terminal to the second node under the control of the clock signal provided by the first clock signal terminal; the second light emission control signal output circuit is connected to the second node, the first voltage terminal, and the light emission control signal output terminal, and configured to transmit the voltage of the first voltage terminal to the light emission control signal output terminal under the control of the second node.
Optionally, the second shift register includes a scan signal input circuit, a scan signal output circuit, and a reset circuit; the scanning signal input circuit is connected with a scanning signal input end and a third node and is configured to transmit a first scanning signal input by the scanning signal input end to the third node under the control of the scanning signal input end; the scan signal output circuit is connected to the third node, the first clock signal terminal and the scan signal output terminal, and configured to transmit a clock signal provided by the first clock signal terminal to the scan signal output terminal under the control of the third node to output a second scan signal at the scan signal output terminal; the reset circuit is connected with a first voltage terminal, the third node and a reset signal terminal, and is configured to transmit the voltage provided by the first voltage terminal to the third node under the control of the reset signal terminal.
Optionally, the light emission control signal input circuit includes a first transistor; the grid electrode of the first transistor is connected with the second clock signal end, the first pole of the first transistor is connected with the light-emitting control signal input end, and the second pole of the first transistor is connected with the first node; and/or, the first light-emitting control signal output circuit comprises a second transistor and a first storage capacitor; a grid electrode of the second transistor is connected with the first node, a first pole of the second transistor is connected with the first clock signal end, and a second pole of the second transistor is connected with the light-emitting control signal output end; one end of the first storage capacitor is connected with the first node, and the other end of the first storage capacitor is connected with the light-emitting control signal output end; and/or, the light emission control signal control circuit includes a third transistor and a fourth transistor; a grid electrode of the third transistor is connected with the first node, a first pole of the third transistor is connected with the second clock signal end, and a second pole of the third transistor is connected with the second node; a gate of the fourth transistor is connected to the first clock signal terminal, a first pole of the fourth transistor is connected to the second voltage terminal, and a second pole of the fourth transistor is connected to the second node; and/or, the second light emission control signal output circuit includes a fifth transistor; and the grid electrode of the fifth transistor is connected with the second node, the first pole of the fifth transistor is connected with the first voltage end, and the second pole of the fifth transistor is connected with the light-emitting control signal output end.
Optionally, the scan signal input circuit includes a sixth transistor; the grid electrode and the first electrode of the sixth transistor are both connected with the scanning signal input end, and the second electrode of the sixth transistor is connected with the third node; and/or, the scan signal output circuit includes: a seventh transistor and a second storage capacitor; a grid electrode of the seventh transistor is connected with the third node, a first pole of the seventh transistor is connected with the first clock signal end, and a second pole of the seventh transistor is connected with the scanning signal output end; one end of the second storage capacitor is connected with the third node, and the other end of the second storage capacitor is connected with the scanning signal output end; and/or, the reset circuit comprises an eighth transistor; and the grid electrode of the eighth transistor is connected with the reset signal end, the first pole of the eighth transistor is connected with the first voltage end, and the second pole of the eighth transistor is connected with the third node.
In a second aspect of the embodiments of the present invention, a driving circuit is provided, where the driving circuit includes a plurality of cascaded shift registers; under the condition that the shift register comprises a reset signal end, a scanning signal input end of the first-stage shift register is connected with an initial scanning signal end, and a light-emitting control signal input end of the first-stage shift register is connected with an initial light-emitting control signal end; except the first stage of shift register, the scanning signal input end of each stage of shift register is connected with the scanning signal output end of the previous stage of shift register; the light-emitting control signal input end of each stage of shift register is connected with the light-emitting control signal output end of the previous stage of shift register; except the last stage of shift register, the reset signal end of each stage of shift register is connected with the scanning signal output end of the next stage of shift register.
In a third aspect of the embodiments of the present invention, there is provided a display device including the above-described driving circuit.
In a fourth aspect of the embodiments of the present invention, there is provided a driving method for driving the shift register, where the driving method for driving the shift register in a frame of image includes: inputting a first scanning signal to a scanning signal input terminal, and shifting the first scanning signal by a pulse of a clock signal provided by a first clock signal terminal by a first shift register to output a second scanning signal at a scanning signal output terminal; a first light emitting control signal is input to a light emitting control signal input terminal, and a second shift register shifts the first light emitting control signal by one pulse of a clock signal provided by the first clock signal terminal to output a second light emitting control signal at a light emitting control signal output terminal; the second light emission control signal includes the clock signal; wherein an active level signal in the second scan signal is two pulses earlier than the clock signal in the second light emission control signal.
Optionally, the first shift register includes a light-emitting control signal input circuit, a first light-emitting control signal output circuit, a light-emitting control signal control circuit, and a second light-emitting control signal output circuit; in the case where the second shift register includes a scan signal input circuit, a scan signal output circuit, and a reset circuit, the driving method of the shift register specifically includes: in the first stage, under the control of the scanning signal input end, the scanning signal input circuit transmits a first scanning signal input by the scanning signal input end to a third node; under the control of a second clock signal end, the light-emitting control signal input circuit transmits a first light-emitting control signal input by a light-emitting control signal input end to the first node; in the second stage, under the control of the third node, the scanning signal output circuit transmits the clock signal provided by the first clock signal end to the scanning signal output end; under the control of the first clock signal end, the voltage of a second voltage end is transmitted to a second node, and under the control of the second node, the second light-emitting control output circuit transmits the voltage of the first voltage end to a light-emitting control signal output end; in the third stage, under the control of a reset signal end, the reset circuit transmits the voltage of the first voltage end to the third node; the light-emitting control signal input circuit transmits a first light-emitting control signal input from the light-emitting control signal input terminal to the first node under the control of a signal output from the second clock signal terminal, the light-emitting control signal control circuit transmits a clock signal provided from the second clock signal terminal to a second node under the control of the first node, and the second light-emitting control signal output circuit transmits a voltage of a first voltage terminal to the light-emitting control signal output terminal under the control of the second node; under the control of the first node, the first light-emitting control signal output circuit transmits a clock signal provided by the first clock signal terminal to the light-emitting control signal output terminal; and in the fourth stage, under the control of the first node, the first light-emitting control signal output circuit transmits the clock signal provided by the first clock signal end to the light-emitting control signal output end.
Optionally, the driving method of the shift register further includes: in a fifth stage, under the control of the clock signal provided by the first clock signal terminal, the light-emitting control signal control circuit transmits the voltage of the second voltage terminal to the second node, and under the control of the second node, the second light-emitting control signal output circuit transmits the voltage of the first voltage terminal to the light-emitting control signal output terminal.
The embodiment of the invention provides a shift register and a driving method thereof, a driving circuit and a display device, wherein the shift register comprises a first shift register and a second shift register, a scanning signal output end of the first shift register can output a second scanning signal, and a light-emitting control signal output end of the second shift register can output a second light-emitting control signal, so that the shift register can provide scanning signals and light-emitting control signals for a row of sub-pixels. In addition, compared to the related art in which the gate shift register is connected to one clock signal terminal and the light emission controlling shift register is connected to the other clock signal terminal, the first shift register and the second shift register of the present invention are connected to the same clock signal terminal, i.e., the first clock signal terminal, and thus the number of clock signal lines connected to the clock signal terminals can be reduced, thereby reducing power consumption.
On this basis, the second light-emitting control signal output by the light-emitting control signal output end comprises a clock signal, so that the frequency of the second light-emitting control signal is higher, and the health display can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a first schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of the signal terminals of the pixel circuit shown in FIG. 2;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 5 is a first schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 6 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a driving method of a shift register according to an embodiment of the present invention;
FIG. 9 is a timing diagram of signal terminals in a shift register according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a shift register according to a fourth embodiment of the present invention;
fig. 11 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 12 is a sixth schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 13a is a schematic structural diagram seven of a shift register according to an embodiment of the present invention;
fig. 13b is a schematic structural diagram eight of a shift register according to an embodiment of the present invention;
fig. 14a is a schematic structural diagram nine of a shift register according to an embodiment of the present invention;
fig. 14b is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 15a is a schematic diagram of a second scan signal obtained by simulation using simulation software according to an embodiment of the present invention;
fig. 15b is a schematic diagram of obtaining a second light-emitting control signal by simulation using simulation software according to an embodiment of the present invention.
Reference numerals:
01-a drive circuit; 1-a first shift register; 2-a second shift register; 10-a display panel; 11-a light emission control signal input circuit; 12-a first lighting control signal output circuit; 13-a light emission control signal control circuit; 14-a second light emission control signal output circuit; 15-a scan signal input circuit; 16-a scan signal output circuit; 17-a reset circuit; 20-sub-pixel; 100-an active display area; 101-a peripheral zone; 201-pixel circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
Some embodiments of the present invention provide a display device. The display device includes a mobile phone, a tablet computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer, and the like. In some embodiments, the display device is a display panel. The embodiment of the present invention does not particularly limit the specific form of the display device.
The display device includes a display panel 10 as shown in fig. 1. In some embodiments of the present invention, the display panel 10 may be a self-Emitting display panel such as an Organic Light Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, a Micro LED display panel, and a Mini LED display panel.
The display panel 10 includes an Active Area (AA) 100 and a peripheral area 101 located around the active area 100.
The effective display area 100 includes a plurality of sub-pixels 20. For convenience of explanation, the plurality of sub-pixels 20 are described as an example of a matrix arrangement in the present invention. At this time, the sub-pixels 20 arranged in a line in the horizontal direction X are referred to as sub-pixels in the same row, and the sub-pixels 20 arranged in a line in the vertical direction Y are referred to as sub-pixels in the same column. Each of the sub-pixels 20 has a light emitting device and a pixel circuit 201 for driving the light emitting device to emit light disposed therein. Here, the light emitting device may be, for example, an organic light emitting diode, a micro light emitting diode, a mini light emitting diode, a quantum dot light emitting diode, or the like.
The pixel circuit 201 may be other types of pixel circuits such as 6T1C, 6T2C, or 7T1C, which is not limited in the present invention. Here, nTmC means that one pixel circuit 201 includes n transistors (denoted by the letter "T") and m capacitors (denoted by the letter "C").
The pixel circuit 201 in the sub-pixel is exemplified below.
As shown in fig. 2, the pixel circuit 201 includes one capacitor C and 7 transistors, the 7 transistors being a switching transistor M1, M2, M3, M5, M6, M7, and a driving transistor M4, respectively.
The gates of a portion of the switching transistors (e.g., M1, M7 in fig. 2) in the pixel circuit 201 are used for receiving the scan signal N-1. The gates of the other part of the switch transistors (e.g., M2, M3 in fig. 2) are used for receiving the scan signal N. The gates of the further partial switching transistors (e.g. M5, M6 in fig. 2) are arranged to receive the emission control signal EM.
The operation process of the pixel circuit shown in fig. 2 includes three stages shown in fig. 3, namely, a first stage, a second stage, and a third stage.
In the first stage, the switching transistor M1 and the switching transistor M7 are turned on under the control of the scan signal N-1. The initial voltage Vinit is transmitted to a gate (gate, g) of the driving transistor M4 through the switching transistor M1, and resets the gate g of the driving transistor M4. The initial voltage Vinit is also transmitted to the anode a of the light emitting device L through the switching transistor M7, resetting the anode a of the light emitting device L.
In the second stage, under the control of the scan signal N, the switching transistor M2 and the switching transistor M3 are turned on, and the switching transistor M3 is turned on, so that the gate g and the drain (d) of the driving transistor M4 are electrically connected, and the driving transistor M4 is in a diode-on state. At this time, the data signal Vdata is written to the source(s) of the driving transistor M4 through the switching transistor M2, and the threshold voltage Vth of the driving transistor M4 is compensated.
In the third stage, under the control of the emission control signal EM, the switching transistor M5 and the switching transistor M6 are turned on, and the current path between the voltage ELVDD (Vdd for short) and the voltage ELVSS (Vss for short) is turned on. The driving current Isd generated by the driving transistor M4 is transmitted to the light emitting device L through the above current path to drive the light emitting device L to emit light.
The peripheral region 101 of the display panel 10 is provided with a driving circuit. The driving circuit may use a Gate Driver on Array (GOA) technology, that is, the driving circuit is fabricated on a substrate of the Array substrate in the display panel 10. The driving circuit is configured to provide signals to the gates of at least some of the transistors in the pixel circuit 201 of the sub-pixel 20, so as to drive the sub-pixel 20 to perform display. As can be seen from the above-described structure of the pixel circuit 201, the driving circuit is configured to provide scan signals (e.g., M1, M7, M2, M3 in fig. 2) to the gates of the partial transistors in the pixel circuit 201, and provide light emission control signals to the gates of the partial transistors (e.g., M5, M6 in fig. 2).
Based on the above, some embodiments of the present invention provide a driving circuit, as shown in fig. 4, the driving circuit 01 includes a plurality of cascaded Shift Registers (SR). Each shift register SR includes a scan signal output terminal OputNAnd a light emission control signal output terminal OputEMA scanning signal output terminal OputNA scan signal N can be supplied to the gate of at least one transistor in the pixel circuit 201 of one row of the sub-pixels 20, and a light emission control signal output terminal OputEMThe emission control signal EM can be supplied to the gate of at least one transistor in the pixel circuit 201 of one row of the sub-pixels 20.
In this case, when a plurality of shift registers SR are sequentially cascade-connected, as shown in FIG. 4, the scan signal input terminal Ipout of the shift register SR1 of the first stageNConnecting the initial scanning signal terminal STVNA light emission control signal input terminal Ipout of the first stage shift register SR1EMConnecting the initial light-emitting control signal terminal STVEM(ii) a The scan signal input terminal Ipout of each stage of the shift register SR is provided in addition to the first stage of the shift register SR1NAnd a scan signal output terminal Oput of the previous stage shift register SRNConnecting; light-emitting control signal input terminal Ipout of each stage of shift register SREMAnd a light emitting control signal output terminal Oput of the previous stage shift register SREMConnecting; reset signal terminals (Reset, Rst) of the shift registers SR at each stage and scan signal output terminals Oput of the shift registers SR at the next stage except for the last stageNAnd (4) connecting.
In some embodiments, the reset signal terminal Rst of the last stage shift register SR is connected to the start scan signal terminal STVN。
As shown in fig. 5, the shift register SR includes a first shift register 1 and a second shift register 2.
The first shift register 1 is connected to the first clock signal terminal CLK1 and the scan signalInput terminal IpoutNAnd a scan signal output terminal OputNConfigured to be driven by a scan signal input terminal IputNThe inputted first scan signal shifts one pulse of the clock signal supplied from the first clock signal terminal CLK1 to have the scan signal output terminal OputNAnd outputting a second scanning signal.
It should be understood that the first shift register 1 is connected to the first clock signal terminal CLK1, the scan signal input terminal Iput, and the likeNAnd a scan signal output terminal OputNIn addition to the connection, the first shift register 1 may be connected to other signal terminals, for example, the reset signal terminal Rst, the first voltage terminal Vdd, and the like.
Here, the waveforms of the first scan signal and the second scan signal are the same, and the active level signal in the second scan signal is one pulse of the clock signal supplied from the first clock signal terminal CLK1 later than the active level signal in the first scan signal. Further, an active level signal refers to a signal that can turn on a circuit.
The second shift register 2 is connected to the first clock signal terminal CLK1 and the light emission control signal input terminal IpoutEMAnd a light emission control signal output terminal OputEMConfigured to be driven by a light emission control signal input terminal IputEMThe inputted first light emission control signal shifts one pulse of the clock signal supplied from the first clock signal terminal CLK1 to output the light emission control signal at the light emission control signal output terminal OputEMOutputting a second light emitting control signal; the second light-emitting control signal comprises a clock signal provided by a first clock signal terminal CLK 1; wherein the active level signal in the second scan signal is earlier than the clock signal in the second emission control signal by two pulses of the clock signal provided from the first clock signal terminal CLK 1.
Here, the second shift register 2 is connected to the first clock signal terminal CLK1, the light emission control signal input terminal IpoutEMAnd a light emission control signal output terminal OputEMIn addition to the connection, other signal terminals, such as the second clock signal terminal CLK2, the first voltage terminal Vdd, and the second voltage terminal Vss, may be connected.
The waveform of the first light emission control signal and the second light emission control signalThe waveforms of the light emission control signals may be the same or different. For example, with respect to the shift register SR of the first stage, the light emission control signal input terminal Iput connected to the second shift register 2EMA waveform of the first light emission control signal, i.e., the initial light emission control signal, and a light emission control signal output terminal Oput connected to the second shift register 2 are inputtedEMThe waveforms of the output second light emission control signals may be different. Since the second emission control signal includes the clock signal provided from the first clock signal terminal CLK1, in some embodiments, the waveforms of the first emission control signal and the second emission control signal are different for the first stage shift register SR, considering that if the waveform of the start emission control signal is the same as the waveform of the second emission control signal, the start emission control signal also includes the clock signal, which increases the difficulty of providing the start emission control signal. For another example, the waveforms of the first and second light emission control signals are the same for the shift registers of the other stages except for the first stage shift register SR.
In the related art, the driving circuit disposed in the peripheral region 101 includes a gate driving circuit and a light emission control driving circuit. The Gate driving circuit includes a plurality of cascaded Gate shift registers (Gate GOAs), each for supplying a scan signal to a Gate of at least one transistor in the pixel circuit 201 of a row of the sub-pixels 20 connected thereto. The emission control driving circuit includes a plurality of cascaded emission control shift registers (EM GOAs), each for supplying an emission control signal to a gate of at least one transistor in the pixel circuit 201 of a row of the sub-pixels 20 connected thereto.
Based on the above, in the related art, since the peripheral region 101 of the display device needs to be provided with both the gate driving circuit and the light-emitting control driving circuit, the frame of the display device is large, which is not favorable for implementing the narrow frame design, and the power consumption is large. In addition, it has been proved by the standard that when the modulation depth of the display device is larger, the higher the frequency of the light source (i.e., the higher the frequency of the light control signal), the less the damage to the human eyes. In the related art, the frequency of the light-emitting control signal provided by the light-emitting control shift register is low, so that the display device is easy to screen flash, has great harm to human eyes and is not beneficial to healthy display.
Some embodiments of the present invention provide a shift register SR, since the shift register SR includes a first shift register 1 and a second shift register 2, a scan signal output terminal Oput of the first shift register 1NA second scan signal can be outputted, and a light emission control signal output terminal Oput of the second shift register 2EMThe second light emitting control signal can be output, that is, the shift register SR can provide a scanning signal to a row of sub-pixels 20 and can also provide a light emitting control signal to a row of sub-pixels 20, and compared with the related art, the shift register SR is required to be provided with both a gate shift register and a light emitting control shift register. Further, in contrast to the related art in which the gate shift register is connected to one clock signal terminal and the light emission controlling shift register is connected to the other clock signal terminal, the first shift register 1 and the second shift register 2 of the present invention are connected to the same clock signal terminal, i.e., the first clock signal terminal CLK1, and thus the number of clock signal lines connected to the clock signal terminals can be reduced, thereby reducing power consumption.
On this basis, since the light emission control signal output terminal OputEMThe output second light emission control signal includes a clock signal, and thus the frequency of the second light emission control signal is high, so that a healthy display can be realized.
As shown in fig. 6, the first shift register 1 includes a light emission control signal input circuit 11, a first light emission control signal output circuit 12, a light emission control signal control circuit 13, and a second light emission control signal output circuit 14.
Light emission control signal input circuit 11 and light emission control signal input terminal IputEMA second clock signal terminal CLK2 connected to the first node P1 and configured to emit light under the control of the second clock signal terminal CLK2Control signal input terminal IpoutEMThe input first lighting control signal is transmitted to the first node P1.
The first light emission control signal output circuit 12 is connected to the first node P1, the first clock signal terminal CLK1 and the light emission control signal output terminal OputEMA connection configured to transmit the clock signal provided from the first clock signal terminal CLK1 to the light emission control signal output terminal Oput under the control of the first node P1EMTo the light emission control signal output terminal OputEMAnd outputting a second light-emitting control signal.
The light emission control signal control circuit 13 is connected to the first node P1, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the second voltage terminal Vss, and the second node P2, and is configured to transmit the clock signal provided from the second clock signal terminal CLK2 to the second node P2 under the control of the first node P1, and is further configured to transmit the voltage of the second voltage terminal Vss to the second node P2 under the control of the clock signal provided from the first clock signal terminal CLK 1.
The second light-emission control signal output circuit 14 is connected to the second node P2, the first voltage terminal Vdd, and the light-emission control signal output terminal OputEMA connection configured to transmit the voltage of the first voltage terminal Vdd to the light emission control signal output terminal Oput under the control of the second node P2EM。
It should be understood that the first shift register 1 includes, but is not limited to, a light emission control signal input circuit 11, a first light emission control signal output circuit 12, a light emission control signal control circuit 13, and a second light emission control signal output circuit 14.
In some embodiments, as shown in fig. 7, the light emission control signal input circuit 11 includes a first transistor T1; the gate of the first transistor T1 is connected to the second clock signal terminal CLK2, and the first electrode is connected to the light-emission control signal input terminal IpoutEMAnd the second pole is connected to the first node P1. It should be noted that the embodiment of the present invention is not limited to this, and the light emission control signal input circuit 11 may be a circuit composed of other components.
In some embodiments, as shown in fig. 7, the first lighting control signal output circuit12 includes a first storage capacitor C1; one end of the first storage capacitor C1 is connected to the first node P1, and the other end is connected to the emission control signal output terminal OputEMAnd (4) connecting.
In the case where the first light emission control signal output circuit 12 includes the first storage capacitor C1, the light emission control signal input terminal Iput is turned on when the light emission control signal input circuit 11 is turned on under the control of the second clock signal terminal CLK2EMThe supplied voltage is stored in the first storage capacitor C1 through the light emission control signal input circuit 11. In the next stage, the voltage stored by the first storage capacitor C1 can maintain the voltage of the previous stage at the first node P1.
On this basis, in some embodiments, as shown in fig. 7, the first lighting control signal output circuit 12 further includes a second transistor T2; a gate of the second transistor T2 is connected to the first node P1, a first pole thereof is connected to the first clock signal terminal CLK1, and a second pole thereof is connected to the emission control signal output terminal OputEMAnd (4) connecting. It should be noted that the embodiment of the present invention is not limited to this, and the first light emission control signal output circuit 12 may be a circuit composed of other components.
In some embodiments, as shown in fig. 7, the light emission control signal control circuit 13 includes a third transistor T3 and a fourth transistor T4; a gate of the third transistor T3 is connected to the first node P1, a first pole is connected to the second clock signal terminal CLK2, and a second pole is connected to the second node P2; the fourth transistor T4 has a gate connected to the first clock signal terminal CLK1, a first pole connected to the second voltage terminal Vss, and a second pole connected to the second node P2. It should be noted that the embodiment of the present invention is not limited to this, and the light emission control signal control circuit 13 may be a circuit composed of other components.
In some embodiments, as shown in fig. 7, the second light emission control signal output circuit 14 includes a fifth transistor T5; a gate of the fifth transistor T5 is connected to the second node P2, a first pole is connected to the first voltage terminal Vdd, and a second pole is connected to the light emission control signal output terminal OputEMAnd (4) connecting. It should be noted that the embodiment of the present invention is not limited thereto, and the second emission control signal output circuit 14 may be the same circuitA circuit consisting of other components.
As shown in fig. 6, the second shift register 2 includes a scan signal input circuit 15, a scan signal output circuit 16, and a reset circuit 17.
Scan signal input circuit 15 and scan signal input terminal IputNConnected to a third node P3, configured to receive a scan signal input terminal IpoutNUnder the control of (2), a scanning signal input end IpoutNThe inputted first scan signal is transmitted to the third node P3.
The scan signal output circuit 16, the third node P3, the first clock signal terminal CLK1, and the scan signal output terminal OputNA connection configured to transmit the clock signal provided from the first clock signal terminal CLK1 to the scan signal output terminal Oput under the control of the third node P3NTo scan the signal output terminal OputNAnd outputting a second scanning signal.
The reset circuit 17 is connected to the first voltage terminal Vdd, the third node P3, and the reset signal terminal Rst, and configured to transmit the voltage provided from the first voltage terminal Vdd to the third node P3 under the control of the reset signal terminal Rst.
Here, the reset circuit 17 transmits the voltage provided by the first voltage terminal Vdd to the third node P3 under the control of the reset signal terminal Rst to reset the third node P3, thereby avoiding influence on other stages.
It should be understood that the second shift register 2 includes, but is not limited to, a scan signal input circuit 15, a scan signal output circuit 16, and a reset circuit 17.
In some embodiments, as shown in fig. 7, the scan signal input circuit 15 includes a sixth transistor T6; the gate and the first pole of the sixth transistor T6 are connected to the scan signal input terminal IputNAnd the second pole is connected with the third node P3. It should be noted that the embodiment of the present invention is not limited to this, and the scan signal input circuit 15 may be a circuit composed of other components.
In some embodiments, as shown in FIG. 7, the scan signal output circuit 16 includes a second storage capacitor C2, one terminal of the second storage capacitor C2 and a third node P3Connected with the other end thereof to a scan signal output terminal OputNAnd (4) connecting.
In the case where the scan signal output circuit 16 includes the second storage capacitor C2, at the scan signal input terminal IputNUnder the control of (1), when the scan signal input circuit 15 is turned on, the scan signal input terminal IpoutNThe supplied voltage is stored in the second storage capacitor C2 through the scan signal input circuit 15. In the next stage, the voltage stored by the second storage capacitor C2 may maintain the voltage of the previous stage at the third node P3.
On this basis, in some embodiments, as shown in fig. 7, the scan signal output circuit 16 further includes a seventh transistor T7; a gate of the seventh transistor T7 is connected to the third node P3, a first pole is connected to the first clock signal terminal CLK1, and a second pole is connected to the scan signal output terminal OputNAnd (4) connecting. It should be noted that the embodiment of the present invention is not limited to this, and the scan signal output circuit 16 may be a circuit composed of other components.
In some embodiments, as shown in fig. 7, the reset circuit 17 includes an eighth transistor T8; the eighth transistor T8 has a gate connected to the reset signal terminal Rst, a first pole connected to the first voltage terminal Vdd, and a second pole connected to the third node P3. It should be noted that the embodiment of the present invention is not limited to this, and the reset circuit 17 may be a circuit composed of other components.
The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may all be P-type transistors or all be N-type transistors; alternatively, a part of the transistors may be N-type transistors, and another part of the transistors may be P-type transistors. If the transistor is a P-type transistor, the transistor is turned on in response to a low level signal. If the transistor is an N-type transistor, the transistor is turned on in response to a high level signal.
In addition, the first electrode may be a source electrode, and the second electrode may be a drain electrode; the first pole may be a drain and the second pole may be a source.
It should be understood that the first node P1, the second node P2, and the third node P3 described above do not represent actual components, but rather represent a junction of related circuit connections in a circuit diagram.
An embodiment of the present invention further provides a driving method for driving the shift register SR, where in a frame of image, the driving method for the shift register SR includes:
to the scan signal input terminal IputNThe first shift register 1, to which the first scan signal is input, shifts the first scan signal by one pulse of the clock signal supplied from the first clock signal terminal CLK1 to output the scan signal at the scan signal output terminal OputNAnd outputting a second scanning signal.
To the lighting control signal input terminal IputEMThe first light emission control signal is inputted, and the second shift register 2 shifts the first light emission control signal by one pulse of the clock signal supplied from the first clock signal terminal CLK1 to output the light emission control signal at the light emission control signal output terminal OputEMOutputting a second light emitting control signal; the second light emission control signal includes a clock signal; wherein the active level signal in the second scan signal is two pulses earlier than the clock signal in the second light emission control signal.
The first shift register 1 includes a light emission control signal input circuit 11, a first light emission control signal output circuit 12, a light emission control signal control circuit 13, and a second light emission control signal output circuit 14; in the case where the second shift register 2 includes the scan signal input circuit 15, the scan signal output circuit 16, and the reset circuit 17, a driving method of the shift register in one frame image is as shown in fig. 8. The operation principle of the shift register SR shown in fig. 6 and 7 will be described in one frame of image with reference to the signal timing chart shown in fig. 9. Wherein, taking the shift register SR as an example to provide the scan signal N and the emission control signal EM for the pixel circuit of the first sub-pixel, the scan signal input terminal IpoutNInputting start scanning signal STVNA scanning signal output terminal OputNThe second scan signal G1 is output. Light emission control signal input terminal IputEMInputting an initial light-emitting control signal STVEMAn emission control signal output terminal OputEMThe second light emission control signal E1 is output.
As shown in fig. 9, each frame image of the shift register SR includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4, and fig. 9 illustrates timing waveforms of respective signals in each stage.
It should be noted that fig. 10 is a schematic diagram of the shift register SR shown in fig. 7 in the first stage t1, fig. 11 is a schematic diagram of the shift register SR shown in fig. 7 in the second stage t2, fig. 12 is a schematic diagram of the shift register SR shown in fig. 7 in the third stage t3, and fig. 13a and 13b are schematic diagrams of the shift register SR shown in fig. 7 in the fourth stage t 4. The transistors identified by the dotted lines in fig. 10, 11, 12, 13a, and 13b each indicate an off state in the corresponding stage, and the dotted lines with arrows in fig. 10, 11, 12, 13a, and 13b indicate the current flow paths of the shift register SR in the corresponding stage. The transistors shown in fig. 10, 11, 12, 13a, and 13b are all described using P-type transistors as an example, i.e., the gate of each P-type transistor is turned on when a low-level signal is input and turned off when a high-level signal is input.
S10, the first stage t1, at the input end of scan signal IpoutNUnder the control of (2), the scan signal input circuit 15 inputs the scan signal input terminal IputNThe inputted first scan signal is transmitted to the third node P3. Meanwhile, the light emission control signal input circuit 11 inputs the light emission control signal input terminal Iput under the control of the second clock signal terminal CLK2EMThe input first lighting control signal is transmitted to the first node P1.
As shown in fig. 9 and 10, the sixth transistor T6 is scanned by the scan signal input terminal Iput during the first period T1NThe low level of the inputted first scan signal is turned on, the low level of the first scan signal is transferred to the third node P3 through the sixth transistor T6, the seventh transistor T7 is turned on under the control of the low level supplied from the third node P3, and the high level signal of the clock signal supplied from the first clock signal terminal CLK1 is supplied to the scan signal output terminal Oput through the seventh transistor T7N. Meanwhile, the second storage capacitor C2 stores a low level signal.
The high level signal of the clock signal provided from the first clock signal terminal CLK1 is transmitted to the gate of the fourth transistor T4, and the fourth transistor T4 is turned off. The first transistor T1 is turned on by the low level of the clock signal supplied from the second clock signal terminal CLK2, and the light emission control signal input terminal IputEMThe high level of the input is transmitted to the first node P1 through the first transistor T1, and the second transistor T2 and the third transistor T3 are turned off under the control of the high level provided at the first node P1. The high level signal provided from the reset signal terminal Rst turns off the eighth transistor T8. The gate of the fifth transistor T5 is not supplied with the low level signal, and the fifth transistor T5 is turned off. Light emission control signal output terminal OputEMAnd outputting a high level.
S11, the second stage t2, the scan signal output circuit 16 transmits the clock signal provided by the first clock signal terminal CLK1 to the scan signal output terminal Oput under the control of the third node P3N. The second light emission control output circuit 14 transmits the voltage of the first voltage terminal Vdd to the light emission control signal output terminal Oput under the control of the second node P2, and the second voltage terminal Vss is transmitted to the second node P2 under the control of the first clock signal terminal CLK1EM。
As shown in fig. 9 and 11, in the second stage T2, the low level signal stored in the second storage capacitor C2 maintains the third node P3 at a low level, the seventh transistor T7 is turned on under the control of the low level signal provided from the third node P3, and the low level signal of the clock signal provided from the first clock signal terminal CLK1 is supplied to the scan signal output terminal Oput through the seventh transistor T7NAnd (6) outputting. At this time, due to the bootstrap effect of the capacitor, the voltage at the right end of the second storage capacitor C2 further decreases, that is, the voltage at the third node P3 decreases, so that the seventh transistor T7 is always in a conducting state.
The high level signal of the clock signal provided from the second clock signal terminal CLK2 turns off the first transistor T1. The high signal stored in the first storage capacitor C1 maintains the high level of the first node P1, and the second transistor T2 and the third transistor T3 are turned off under the control of the high level provided from the first node P1. The fourth transistor T4 is driven by the low of the clock signal provided by the first clock signal terminal CLK1The level signal is turned on, the low level signal provided from the second voltage terminal Vss is transmitted to the second node P2 through the fourth transistor T4, the fifth transistor T5 is turned on under the control of the low level signal provided from the second node P2, and the high level signal provided from the first voltage terminal Vdd is transmitted to the light emission control signal output terminal Oput through the fifth transistor T5EMAnd (6) outputting. The high level signal provided from the reset signal terminal Rst turns off the eighth transistor T8.
S12, the third stage t3, the reset circuit 17 transmits the voltage of the first voltage terminal Vdd to the third node P3 under the control of the reset signal terminal Rst.
The light emission control signal input circuit 11 inputs the light emission control signal input terminal Iput under the control of the signal output from the second clock signal terminal CLK2EMThe inputted first light emission control signal is transmitted to the first node P1, the light emission control signal control circuit 13 transmits the clock signal provided from the second clock signal terminal CLK2 to the second node P2 under the control of the first node P1, and the second light emission control signal output circuit 14 transmits the voltage of the first voltage terminal Vdd to the light emission control signal output terminal Oput under the control of the second node P2EM(ii) a The first emission control signal output circuit 12 transmits the clock signal provided from the first clock signal terminal CLK1 to the emission control signal output terminal Oput under the control of the first node P1EM。
As shown in FIGS. 9 and 12, in the third stage T3, the sixth transistor T6 is connected to the scan signal input terminal IpoutNThe high level provided is cut off. The eighth transistor T8 is turned on by the low level provided by the reset signal terminal Rst. The high level provided by the first voltage terminal Vdd is transmitted to the third node P3 through the eighth transistor T8, and the seventh transistor T7 is turned off under the control of the third node P3. The third node P3 provides a high level, i.e., the voltage at the right end of the second storage capacitor C2 is increased, and the voltage at the left end of the second storage capacitor C2 is increased due to the bootstrap effect of the capacitor, so that the scan signal output terminal Oput isNAnd outputting a high level.
In the third stage T3, the first transistor T1 is turned on by the low level of the clock signal provided from the second clock signal terminal CLK2, and the light emission control signal input terminal IputEMFirst of inputThe low level of the light emission control signal is transmitted to the first node P1 through the first transistor T1, the second and third transistors T2 and T3 are turned on under the control of the first node P1, the low level of the clock signal provided from the second clock signal terminal CLK2 is transmitted to the second node P2 through the third transistor T3, the fifth transistor T5 is turned on under the control of the second node P2, and the high level provided from the first voltage terminal Vdd is transmitted to the light emission control signal output terminal Oput through the fifth transistor T5EM. The high level of the clock signal provided from the first clock signal terminal CLK1 is transmitted to the light emission control signal output terminal Oput through the second transistor T2EM. The fourth transistor T4 is turned off by the high level of the clock signal supplied from the first clock signal terminal CLK 1.
S13, the fourth stage, the first light emission control signal output circuit 12 transmits the clock signal provided by the first clock signal terminal CLK1 to the light emission control signal output terminal Oput under the control of the first node P1EM。
As shown in FIGS. 9, 13a and 13b, in the fourth stage T4, the sixth transistor T6 is connected to the scan signal input terminal IpoutNThe high level provided is cut off. The eighth transistor T8 is turned off by the high level provided by the reset signal terminal Rst. The third node P3 maintains the high level of the third stage T3, the seventh transistor T7 is turned off, and the left end of the second storage capacitor C2 maintains a high voltage due to the bootstrap effect of the capacitor, so that the scan signal output terminal Oput is connected to the second storage capacitor C2NA high level is always output.
In the fourth stage T4, as shown in fig. 13a, in the case where the clock signal provided from the first clock signal terminal CLK1 is at a low level and the clock signal provided from the second clock signal terminal CLK2 is at a high level, the first transistor T1 is turned off by the high level of the clock signal provided from the second clock signal terminal CLK 2. The first node P1 maintains the low level of the third stage T3, and the second transistor T2 and the third transistor T3 are turned on under the control of the low level provided by the first node P1. The low level of the clock signal provided from the first clock signal terminal CLK1 is transmitted to the light emission control signal output terminal Oput through the second transistor T2EM. The high level of the clock signal provided from the second clock signal terminal CLK2 is transmitted to the second node through the third transistor T3Point P2. The fourth transistor T4 is turned on by the low level of the clock signal supplied from the first clock signal terminal CLK1, and the low level of the second voltage terminal Vss is transmitted to the second node P2 through the fourth transistor T4. Here, it should be understood that the second node P2 is at a high level when the high level of the clock signal provided from the second clock signal terminal CLK2 is transmitted to the second node P2 and the low level of the second voltage terminal Vss is transmitted to the second node P2. Thus, the fifth transistor T5 is turned off under the control of the high level provided by the second node P2.
As shown in fig. 13b, in the case where the clock signal supplied from the first clock signal terminal CLK1 is at a high level and the clock signal supplied from the second clock signal terminal CLK2 is at a low level, the first transistor T1 is turned on by the low level of the clock signal supplied from the second clock signal terminal CLK2, and the light emission control signal input terminal IputEMThe low level of the inputted first light emission control signal is transmitted to the first node P1 through the first transistor T1. The second transistor t2 and the third transistor t3 are turned on under the control of a low level provided from the first node P1. The high level of the clock signal provided from the first clock signal terminal CLK1 is transmitted to the light emission control signal output terminal Oput through the second transistor T2EM. The low level of the clock signal provided from the second clock signal terminal CLK2 is transmitted to the second node P2 through the third transistor T3, the fifth transistor T5 is turned on under the control of the low level provided from the second node P2, and the high level provided from the first voltage terminal Vdd is transmitted to the light emission control signal output terminal Oput through the fifth transistor T5EM. The fourth transistor T4 is turned off by the high level of the clock signal supplied from the first clock signal terminal CLK 1.
Based on the above, the light emission control signal output terminal OputEMThe high level and the low level are alternately output at the fourth stage t4, that is, the clock signal of the first clock signal terminal CLK1 is output.
On the basis, in conjunction with the signal timing diagram shown in fig. 8, the operation process of the shift register shown in fig. 6 may further include a fifth stage t 5.
Fig. 14a and 14b are schematic diagrams of the shift register SR shown in fig. 7 at a fifth stage t 5.
A fifth stage ofThe light-emission control signal control circuit 13 transmits the voltage of the second voltage terminal Vss to the second node P2 under the control of the clock signal supplied from the first clock signal terminal CLK1, and the second light-emission control signal output circuit 14 transmits the voltage of the first voltage terminal Vdd to the light-emission control signal output terminal Oput under the control of the second node P2EM。
As shown in FIGS. 9, 14a and 14b, in the fifth stage T5, the sixth transistor T6 is clocked by the scan signal input terminal IpoutNThe high level provided is cut off. The eighth transistor T8 is turned off by the high level provided by the reset signal terminal Rst. The third node P3 is maintained at a high level, the seventh transistor T7 is turned off, and the left terminal of the second storage capacitor C2 is maintained at a high voltage due to the bootstrap effect of the capacitor, so that the scan signal output terminal Oput is maintained at a high voltageNA high level is always output.
As shown in fig. 14a, in the case where the clock signal supplied from the first clock signal terminal CLK1 is at a high level and the clock signal supplied from the second clock signal terminal CLK2 is at a low level, the first transistor T1 is turned on by the low level of the clock signal supplied from the second clock signal terminal CLK2, and the light emission control signal input terminal IputEMThe high level of the inputted first light emission control signal is transmitted to the first node P1 through the first transistor T1. The second and third transistors T2 and T3 are turned off under the control of the first node P1. The fourth transistor T4 is turned off by the high level of the clock signal supplied from the first clock signal terminal CLK 1. Light emission control signal output terminal OputEMAnd outputting a high level.
As shown in fig. 14b, in the case where the clock signal supplied from the first clock signal terminal CLK1 is at a low level and the clock signal supplied from the second clock signal terminal CLK2 is at a high level, the first transistor T1 is turned off by the high level of the clock signal supplied from the second clock signal terminal CLK 2. The first node P1 maintains a high level, and the second transistor T2 and the third transistor T3 are turned off under the control of the first node P1. The fourth transistor T4 is turned on by a low level of the clock signal provided from the first clock signal terminal CLK 1. The low level of the second voltage terminal Vss is transmitted to the second node P2 through the fourth transistor T4, the fifth transistor T5 is turned on under the control of the low level provided from the second node P2, and the first voltage terminal Vss is turned onThe high level provided by the terminal Vdd is transmitted to the light emission control signal output terminal Oput through the fifth transistor T5EM。
Based on the above, in the fifth stage t5, the light emission control signal output terminal OputEMThe high level is continuously output.
The embodiment of the invention adds the fifth stage t5 by adjusting the light emission control signal output terminal OputEMThe duty ratio of the output second light-emitting control signal can adjust the display brightness of the whole display device.
The shift register shown in fig. 7 was simulated using HSPICE software according to the signal timing diagram shown in fig. 9. Wherein the voltage of the first voltage terminal Vdd is 15V, the voltage of the second voltage terminal Vss is-15V, and the positive and negative voltages of the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are +15V and-15V, respectively. The capacitance of the first reservoir capacitor C1 and the second reservoir capacitor C2 are 100pF and 80pF, respectively. Simulation results As shown in FIGS. 15a and 15b, the scan signal output terminal OputNOutputting the second scan signal with respect to the scan signal input terminal IpoutNThe inputted first scan signal is shifted by one pulse of the clock signal supplied from the first clock signal terminal CLK 1. Light emission control signal output terminal OputEMThe outputted second emission control signal includes a clock signal provided from the first clock signal terminal CLK 1.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A shift register, comprising:
a first shift register; the first shift register is connected with a first clock signal terminal, a scanning signal input terminal and a scanning signal output terminal, and is configured to shift a first scanning signal input by the scanning signal input terminal by one pulse of a clock signal provided by the first clock signal terminal to output a second scanning signal at the scanning signal output terminal;
a second shift register connected to the first clock signal terminal, the light emission control signal input terminal, and the light emission control signal output terminal, and configured to shift the first light emission control signal input by the light emission control signal input terminal by one pulse of the clock signal provided by the first clock signal terminal to output a second light emission control signal at the light emission control signal output terminal; the second light emission control signal includes the clock signal;
wherein an active level signal in the second scan signal is two pulses earlier than the clock signal in the second light emission control signal.
2. The shift register according to claim 1, wherein the first shift register includes a light emission control signal input circuit, a first light emission control signal output circuit, a light emission control signal control circuit, and a second light emission control signal output circuit;
the light-emitting control signal input circuit is connected with a light-emitting control signal input end, a second clock signal end and a first node, and is configured to transmit a first light-emitting control signal input by the light-emitting control signal input end to the first node under the control of the second clock signal end;
the first light emitting control signal output circuit is connected with the first node, the first clock signal terminal and a light emitting control signal output terminal, and is configured to transmit a clock signal provided by the first clock signal terminal to the light emitting control signal output terminal under the control of the first node to output a second light emitting control signal at the light emitting control signal output terminal;
the light emitting control signal control circuit is connected with a first node, a first clock signal terminal, a second voltage terminal and a second node, is configured to transmit a clock signal provided by the second clock signal terminal to the second node under the control of the first node, and is further configured to transmit a voltage of the second voltage terminal to the second node under the control of the clock signal provided by the first clock signal terminal;
the second light emission control signal output circuit is connected to the second node, the first voltage terminal, and the light emission control signal output terminal, and configured to transmit the voltage of the first voltage terminal to the light emission control signal output terminal under the control of the second node.
3. The shift register according to claim 1, wherein the second shift register includes a scan signal input circuit, a scan signal output circuit, and a reset circuit;
the scanning signal input circuit is connected with a scanning signal input end and a third node and is configured to transmit a first scanning signal input by the scanning signal input end to the third node under the control of the scanning signal input end;
the scan signal output circuit is connected to the third node, the first clock signal terminal and the scan signal output terminal, and configured to transmit a clock signal provided by the first clock signal terminal to the scan signal output terminal under the control of the third node to output a second scan signal at the scan signal output terminal;
the reset circuit is connected with a first voltage terminal, the third node and a reset signal terminal, and is configured to transmit the voltage provided by the first voltage terminal to the third node under the control of the reset signal terminal.
4. The shift register according to claim 2, wherein the light emission control signal input circuit includes a first transistor; the grid electrode of the first transistor is connected with the second clock signal end, the first pole of the first transistor is connected with the light-emitting control signal input end, and the second pole of the first transistor is connected with the first node;
and/or the presence of a gas in the gas,
the first light emission control signal output circuit includes a second transistor and a first storage capacitor; a grid electrode of the second transistor is connected with the first node, a first pole of the second transistor is connected with the first clock signal end, and a second pole of the second transistor is connected with the light-emitting control signal output end; one end of the first storage capacitor is connected with the first node, and the other end of the first storage capacitor is connected with the light-emitting control signal output end;
and/or the presence of a gas in the gas,
the light emission control signal control circuit includes a third transistor and a fourth transistor; a grid electrode of the third transistor is connected with the first node, a first pole of the third transistor is connected with the second clock signal end, and a second pole of the third transistor is connected with the second node; a gate of the fourth transistor is connected to the first clock signal terminal, a first pole of the fourth transistor is connected to the second voltage terminal, and a second pole of the fourth transistor is connected to the second node;
and/or the presence of a gas in the gas,
the second light emission control signal output circuit includes a fifth transistor; and the grid electrode of the fifth transistor is connected with the second node, the first pole of the fifth transistor is connected with the first voltage end, and the second pole of the fifth transistor is connected with the light-emitting control signal output end.
5. The shift register according to claim 3, wherein the scan signal input circuit includes a sixth transistor; the grid electrode and the first electrode of the sixth transistor are both connected with the scanning signal input end, and the second electrode of the sixth transistor is connected with the third node;
and/or the presence of a gas in the gas,
the scan signal output circuit includes: a seventh transistor and a second storage capacitor; a grid electrode of the seventh transistor is connected with the third node, a first pole of the seventh transistor is connected with the first clock signal end, and a second pole of the seventh transistor is connected with the scanning signal output end; one end of the second storage capacitor is connected with the third node, and the other end of the second storage capacitor is connected with the scanning signal output end;
and/or the presence of a gas in the gas,
the reset circuit includes an eighth transistor; and the grid electrode of the eighth transistor is connected with the reset signal end, the first pole of the eighth transistor is connected with the first voltage end, and the second pole of the eighth transistor is connected with the third node.
6. A driver circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 5; in case the shift register comprises a reset signal terminal,
the light-emitting control signal input end of the first-stage shift register is connected with the initial light-emitting control signal end;
except the first stage of shift register, the scanning signal input end of each stage of shift register is connected with the scanning signal output end of the previous stage of shift register; the light-emitting control signal input end of each stage of shift register is connected with the light-emitting control signal output end of the previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is connected with the scanning signal output end of the next stage of shift register.
7. A display device comprising the driver circuit according to claim 6.
8. A driving method for driving the shift register according to any one of claims 1 to 5, wherein the driving method for the shift register in one frame image comprises:
inputting a first scanning signal to a scanning signal input terminal, and shifting the first scanning signal by a pulse of a clock signal provided by a first clock signal terminal by a first shift register to output a second scanning signal at a scanning signal output terminal;
a first light emitting control signal is input to a light emitting control signal input terminal, and a second shift register shifts the first light emitting control signal by one pulse of a clock signal provided by the first clock signal terminal to output a second light emitting control signal at a light emitting control signal output terminal; the second light emission control signal includes the clock signal; wherein an active level signal in the second scan signal is two pulses earlier than the clock signal in the second light emission control signal.
9. The method for driving a shift register according to claim 8, wherein the first shift register comprises a light emission control signal input circuit, a first light emission control signal output circuit, a light emission control signal control circuit, and a second light emission control signal output circuit; in the case where the second shift register includes a scan signal input circuit, a scan signal output circuit, and a reset circuit, the driving method of the shift register specifically includes:
in the first stage, under the control of the scanning signal input end, the scanning signal input circuit transmits a first scanning signal input by the scanning signal input end to a third node; under the control of a second clock signal end, the light-emitting control signal input circuit transmits a first light-emitting control signal input by a light-emitting control signal input end to a first node;
in the second stage, under the control of the third node, the scanning signal output circuit transmits the clock signal provided by the first clock signal end to the scanning signal output end; under the control of the first clock signal end, the voltage of a second voltage end is transmitted to a second node, and under the control of the second node, the second light-emitting control output circuit transmits the voltage of the first voltage end to a light-emitting control signal output end;
in the third stage, under the control of a reset signal end, the reset circuit transmits the voltage of the first voltage end to the third node;
the light-emitting control signal input circuit transmits a first light-emitting control signal input from the light-emitting control signal input terminal to the first node under the control of a signal output from the second clock signal terminal, the light-emitting control signal control circuit transmits a clock signal provided from the second clock signal terminal to a second node under the control of the first node, and the second light-emitting control signal output circuit transmits a voltage of a first voltage terminal to the light-emitting control signal output terminal under the control of the second node; under the control of the first node, the first light-emitting control signal output circuit transmits a clock signal provided by the first clock signal terminal to the light-emitting control signal output terminal;
and in the fourth stage, under the control of the first node, the first light-emitting control signal output circuit transmits the clock signal provided by the first clock signal end to the light-emitting control signal output end.
10. The method for driving a shift register according to claim 9, further comprising:
in a fifth stage, under the control of the clock signal provided by the first clock signal terminal, the light-emitting control signal control circuit transmits the voltage of the second voltage terminal to the second node, and under the control of the second node, the second light-emitting control signal output circuit transmits the voltage of the first voltage terminal to the light-emitting control signal output terminal.
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