CN111708726A - Port sharing method, device, equipment, system and readable storage medium - Google Patents
Port sharing method, device, equipment, system and readable storage medium Download PDFInfo
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- CN111708726A CN111708726A CN202010559651.XA CN202010559651A CN111708726A CN 111708726 A CN111708726 A CN 111708726A CN 202010559651 A CN202010559651 A CN 202010559651A CN 111708726 A CN111708726 A CN 111708726A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention discloses a port sharing method, which comprises the following steps: when the switching signal is detected, acquiring a link state corresponding to a target link between target chips; wherein, the target chip is connected with a debugging line; when the link state is the establishment, closing the target link; when the link state is closed, establishing a target link; the method establishes or closes a target link according to the link state, can debug the shared equipment of a plurality of ports through a target chip when one debugging line and one port are used, does not need to plug and pull the debugging line or adopt a plurality of debugging lines, and improves the debugging efficiency while saving the material cost; in addition, the invention also provides a port sharing device, a port sharing system and a computer readable storage medium, which also have the beneficial effects.
Description
Technical Field
The present invention relates to the field of port sharing technologies, and in particular, to a port sharing method, a port sharing apparatus, a port sharing device, a port sharing system, and a computer-readable storage medium.
Background
Serial Interface (Serial Interface), also called Serial communication Interface or Serial communication Interface (usually referred to as COM Interface), is an extended Interface adopting a Serial communication mode, and Serial refers to data being transmitted sequentially bit by bit. The network port refers to a network connection port. When some network devices, such as a switch device, are debugged, in order to meet some debugging requirements or improve debugging efficiency, two network devices are usually debugged at the same time. Therefore, the debugging personnel need to use a plurality of debugging lines and a plurality of ports (the ports correspond to the debugging lines one to one) to respectively connect each network device with the debugging device, which results in higher material cost. In order to save material cost, the related art adopts one debugging line and uses one port for debugging, but when debugging is carried out by using one debugging line and one port, the debugging line needs to be continuously plugged and pulled to connect different network equipment, so that the debugging efficiency is lower.
Therefore, how to solve the problem of low debugging efficiency in the related art is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a port sharing method, a port sharing apparatus, a port sharing device, a port sharing system and a computer readable storage medium, which solve the problem of low debugging efficiency in the related art.
In order to solve the above technical problem, the present invention provides a port sharing method, including:
when the switching signal is detected, acquiring a link state corresponding to a target link between target chips; wherein, the target chip is connected with the port;
when the link state is established, closing the target link;
and when the link state is closed, establishing the target link.
Optionally, before the detecting the switching signal, the method further includes:
when power-on is detected, performing initialization configuration;
acquiring identity information, and judging whether the equipment is shared by a main port or not by using the identity information;
if the main port is the shared device, the target link between the main port and the target chip is established;
and if the target link is not the main port shared device, closing the target link.
Optionally, the establishing the target link includes:
when the target chip is an internet access chip, a reset link, a serial management interface link and a serial-parallel transceiving link with the target chip are established by using a logic component;
resetting the target chip through the reset link;
and configuring the target chip through the serial management interface link to complete the establishment of the target link.
Optionally, the closing the target link includes:
and when the target chip is the internet access chip, the logic component is utilized to shut off the serial-parallel transceiving link through the serial management interface link, so as to complete the closing of the target link.
Optionally, the establishing the target link includes:
when the target chip is a serial port chip, setting a first link and a second link between a processor and the logic component to be in a penetration state by using the logic component;
and establishing a third link between the logic component and the target chip to complete the establishment of the target link.
Optionally, the closing the target link includes:
and when the target chip is the serial port chip, setting the first link and the second link to be in a high-impedance state, and finishing the closing of the target link.
The present invention also provides a port sharing device, including:
the detection module is used for acquiring a link state corresponding to a target link between target chips when the switching signal is detected; wherein, the target chip is connected with the port;
a closing module, configured to close the target link when the link status is established;
and the establishing module is used for establishing the target link when the link state is closed.
The present invention also provides a port sharing device, comprising a memory and a processor, wherein:
the memory is used for storing a computer program;
the processor is configured to execute the computer program to implement the port sharing method.
The invention also provides a port sharing system, which comprises a first port sharing device, a second port sharing device and a target chip, wherein:
the target chip is connected with the port;
when a switching signal is detected, the first port shared device acquires a first link state corresponding to a first target link between the target chips, and the second port shared device acquires a second link state corresponding to a second target link between the target chips;
when the first link state is established, the first port shared device closes the first target link; when the second link state is established, the second port shared device closes the second target link;
when the first link state is closed, the first port shared device establishes the first target link; and when the second link state is closed, the second port shared device establishes the second target link.
The present invention also provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the port sharing method described above.
According to the port sharing method provided by the invention, when the switching signal is detected, the link state corresponding to the target link between the target chips is obtained; wherein, the target chip is connected with a debugging line; when the link state is the establishment, closing the target link; and when the link state is closed, establishing the target link.
Therefore, when the method detects the switching signal, it may be determined that the debugged port sharing device changes, and thus a link state of the target link is obtained, where the link state may represent a connection state between the port sharing device and the target chip. Because the target chip is connected with the debugging line, the link state of the target link can represent the communication state of the port shared equipment and the debugging line. When the link state is the establishment state, the state is that the link state is originally the debugged port sharing equipment but not the debugged port sharing equipment, so that the target link is closed so that the debugged port sharing equipment establishes the target link; when the link status is off, it indicates that the link is not the debugged port sharing device but now, and thus the target link is established. The target link is established or closed according to the link state, the common equipment of a plurality of ports can be debugged through the target chip when one debugging line and one port are used, the debugging line does not need to be plugged or pulled, or a plurality of debugging lines are adopted, and the debugging efficiency is improved while the material cost is saved.
In addition, the invention also provides a port sharing device, a port sharing system and a computer readable storage medium, which also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a port sharing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a port sharing system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another port sharing system according to an embodiment of the present invention;
fig. 4 is a schematic configuration diagram of a connection method according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another port sharing system according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a port sharing device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a port sharing device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment, please refer to fig. 2, and fig. 2 is a schematic structural diagram of a port sharing system according to an embodiment of the present invention. The port sharing system includes a first port sharing device 10, a second port sharing device 11, and a target chip 12, where the first port sharing device 10 is connected to the target chip 12 through a first target link, and the second port sharing device 11 is connected to the target chip 12 through a second target link. The first port sharing device 10 and the second port sharing device 11 may be specifically a switch management card, a master card, or the like. The target chip 12 is connected to a port, and the port is connected to the debugging device 13 through a debugging line, so that the debugging device 13 debugs the first port sharing device 10 or the second port sharing device 11 through the debugging line and the port. The first port sharing device 10 and the first port sharing device 11 may each perform all or part of the steps of the port sharing method provided herein. Referring to fig. 1, fig. 1 is a flowchart of a port sharing method according to an embodiment of the present invention, where the method includes:
s101: when the switching signal is detected, a link state corresponding to a target link between target chips is acquired.
The target chip is connected with the port, and the port is connected with the debugging line. In this embodiment, the first port sharing device 10 may be selected to perform some or all of the steps of the method. The switch signal may also be referred to as a switch special character, which is used to indicate that the port sharing device receiving the debug is switched. The specific content of the switching signal can be defined according to the requirement, and in order to avoid the normal signal being mistaken as the switching signal, characters or character combinations which are not frequently used in the normal signal can be used as the switching signal. And when the switching signal is detected, determining a target link between the target chip and the target chip, and acquiring a link state corresponding to the target link. The link state represents the connection condition of the target link, namely the connection state between the port sharing device and the target chip. In this embodiment, the target link is the first target link.
The embodiment is not limited to the specific method for obtaining the link state corresponding to the target link. For example, a log file can be read, and the link state is determined through record information in the log file; or the status flag bit may be checked to determine the corresponding link status.
S102: and when the link state is the establishment, closing the target link.
When the link status is established, it is described that the target link between the port sharing device and the target chip is in a conducting state at this time, in this embodiment, the first target link between the first port sharing device 10 and the target chip 12 is in a conducting state. And when the switching signal is received, the port sharing equipment which establishes connection with the target chip and is debugged needs to be replaced, and the connection with the target chip needs to be disconnected, so that the target link is closed.
It should be noted that the target link corresponds to the target chip, that is, different types of target chips, the specific form of the target link between the port sharing device and the target chip may be different, and the specific method for closing the target link may be different. When a plurality of target chips exist, a plurality of target links may exist, the target links and the target chips are in a one-to-one correspondence relationship, and the target links and the port sharing devices may be in a many-to-one relationship.
S103: and when the link state is closed, establishing the target link.
When the link status is off, it indicates that the target link between the port sharing device and the target chip is off at this time. The switching signal is received, which indicates that the port sharing device connected with the target chip and subjected to debugging needs to be replaced, and the port sharing system shares two port sharing devices, so that the port sharing system can determine that the port sharing device needs to be subjected to debugging, and a target link between the port sharing device and the target chip is established.
Based on the port sharing system shown in fig. 2, the first port sharing device 10 and the first port sharing device 11 may each perform the steps S101, S102, and S103 described above. For example, when the first target link corresponding to the first port sharing device 10 is in an established state, the second target link corresponding to the second port sharing device 11 is in a closed state. At this time, when both the first port shared device 10 and the first port shared device 11 receive the switching signal, the first port shared device 10 determines that the link state corresponding to the first target link is established, so that the first target link is closed; the second port shared device 11 determines that the link status corresponding to the second target link is closed, and thus establishes the second target link. The switching of the port sharing device that establishes a connection with the target chip 12 can be completed only by sending a switching signal.
By applying the port sharing method provided by the embodiment of the invention, when the switching signal is detected, the debugged port sharing device can be determined to change, so that the link state of the target link is obtained, and the link state can represent the communication state of the port sharing device and the target chip. Because the target chip is connected with the debugging line, the link state of the target link can represent the communication state of the port shared equipment and the debugging line. When the link state is the establishment state, the state is that the link state is originally the debugged port sharing equipment but not the debugged port sharing equipment, so that the target link is closed so that the debugged port sharing equipment establishes the target link; when the link status is off, it indicates that the link is not the debugged port sharing device but now, and thus the target link is established. The target link is established or closed according to the link state, the common equipment of a plurality of ports can be debugged through the target chip when one debugging line and one port are used, the debugging line does not need to be plugged or pulled, or a plurality of debugging lines are adopted, and the debugging efficiency is improved while the material cost is saved.
Based on the foregoing embodiment, in a possible implementation manner, before debugging, an initialization process is further performed, specifically:
step 11: and when the power-on is detected, performing initial configuration.
When the power-on of the self is detected, the self is initialized, namely, the initialization configuration is carried out. The specific process of configuration may be related to the specific type of port sharing device itself. It should be noted that, the configuration process needs to determine identity information, so as to determine the identity of the user according to the identity information in the following.
Step 12: and acquiring identity information, and judging whether the equipment is the main port shared equipment or not by using the identity information.
Whether the device is a master port sharing device (namely, a master device) can be judged by utilizing the identity information, and the master device is the port sharing device which establishes target connection with the target chip. Specifically, the identity information may be physical location information, for example, when two port sharing devices are arranged up and down, the port sharing device above may be determined as a master device; or when two port sharing devices are arranged left and right, the port sharing device on the left can be determined as the master device. The identity information may also be timestamp information, which may correspond to a timestamp of power-up or may correspond to a timestamp of completion of the initialization configuration. After the identity information is obtained, the obtained identity information is compared with the identity information of another port shared device, and the port shared device which is powered on first or the port shared device which completes initialization configuration first can be the master device.
Step 13: and if the device is shared by the main port, establishing a target link between the main port and the target chip.
After determining that the device is the main port shared device, a target link between the device and a target chip can be established to wait for receiving debugging.
Step 14: if the device is not the primary port shared device, the target link is closed.
And after determining that the target link is not the main port shared device, closing the target link and waiting for receiving a switching signal.
Based on the foregoing embodiment, in a possible implementation manner, the target chip may be an internet access chip, and the port sharing device may be a main control card. Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of another port sharing system according to an embodiment of the present invention. In this embodiment, each of the main control card 1 and the main control card 2 includes a CPU and a logic module (also referred to as a logic component), the target chip is a single-port PHY chip (i.e., a single-port physical layer chip), the model of the target chip may be 88E1512, the target chip is connected to a RJ45 port of the panel through a panel Interface card MDI (Medium Dependent Interface, media related Interface), the RJ45 port of the panel is a port, and the RJ45 is an integrated wiring standard, the RJ is Registered Jack. Because the target chip is a network port chip, the debugging line is a network cable. When the main control card 1 establishes a target link with a target chip for the first time, the following steps may be performed:
step 21: when the target chip is an internet access chip, a reset link, a serial management interface link and a serial-parallel transceiving link with the target chip are established by using the logic component.
In this embodiment, the logic component is a logic module in the main control card 1. When the target link is determined to be needed to be established, a RESET link RESET, a serial management interface link SMI and a serial-parallel transceiving link SGMII between the target chip and the target chip are established through the control logic component. The serial-to-parallel transceiving link may be established by a SERDES, which is an abbreviation of SERializer/DESerializer.
Step 22: and resetting the target chip through the reset link.
After the three links are established, the target chip is reset by utilizing the reset link so as to be configured subsequently.
Step 23: and configuring the target chip through the serial management interface link to complete the establishment of the target link.
And after the target chip is determined to be reset, configuring the target chip through the serial management interface link. Referring to fig. 4, fig. 4 is a schematic view of a connection configuration according to an embodiment of the present invention. The SERDES is a serial-parallel transceiving link SGMII, and the PHY Device is a target chip. And finishing the establishment of the target link after the configuration is finished.
Based on the above embodiment, when the target chip is an internet access chip, the process of closing the target link may include:
step 24: when the target chip is a network port chip, the logic component is utilized to shut off the serial and parallel transceiving link through the serial management interface link, and the target link is closed.
When the target link is closed, the logic component can be controlled to complete the shutdown of the serial-parallel receiving and transmitting link through the serial management interface link, and after the serial link is shut down, the main control card 1 cannot be debugged through the target chip, so that the target link can be determined to be closed.
It should be noted that, step 21 to step 23 are the first establishment procedure of the target link, and since only the serial-parallel transceiving link is turned off in step 24 when the target link is closed, in the subsequent target link reestablishment procedure, only the serial-parallel transceiving link is restored through the serial management interface link, that is, the serial-parallel transceiving link is reestablished, and it is not necessary to reestablish the reset link and the serial management interface link.
Based on the above embodiment, in a possible implementation manner, the target chip may be a serial port chip, and the port sharing device may be a main control card. Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of another port sharing system according to an embodiment of the present invention. In this embodiment, each of the main control card 1 and the main control card 2 includes a CPU and a logic module (also referred to as a logic component), the target chip is a serial port chip, the model of the target chip is SP32 3232E, the target chip is connected to a panel serial port through a panel interface card RS232 (asynchronous transmission standard interface), and the panel serial port is a port. Because the target chip is a serial port chip, the debugging line is a serial port line. When the main control card 1 establishes a target link with a target chip for the first time, the following steps may be performed:
step 31: when the target chip is a serial port chip, a first link and a second link between the processor and the logic component are set to be in a penetration state by the logic component.
Referring to fig. 5, the first link and the second link between the CPU and the logic component are a TX link and an RX link, where the TX link is a signal transmission link, TX is Transmit, the RX link is a signal reception link, RX is Receive, and X has no practical meaning. When the target link is established, the first link and the second link in the master control card 1 may be set to a penetration state, that is, data is allowed to be transmitted through the first link and the second link.
Step 32: and establishing a third link between the logic component and the target chip to complete the establishment of the target link.
In this embodiment, the third link includes two links, namely a txd (transmit data) link and an rxd (receive data) link, which are respectively used for data transmission and reception. It should be noted that the third link may only connect the main control card 1 and the target chip, and may also connect the main control card 1, the main control card 2 and the target chip, as shown in fig. 5.
Based on the above embodiment, when the target chip is a serial chip, the process of closing the target link may include:
step 33: and when the target chip is a serial port chip, setting the first link and the second link to be in a high-impedance state to complete the closing of the target link.
It should be noted that the target link may be closed by setting the first link and the second link to a high-impedance state, so as to prevent data communication, i.e., close the target link.
It should be noted that, step 31 to step 32 are the first establishment procedure of the target link, and when the target link is closed, only the states of the first link and the second link are set in step 23, and the third link is not processed, so in the subsequent target link reestablishment procedure, only the states of the first link and the second link need to be set, that is, the first link and the second link need to be set in the penetration state, and the third link does not need to be reestablished. Just because the shutdown of the target link is controlled through the state settings of the first link and the second link, when the first link and the second link are in a high-impedance state, information on the third link cannot be acquired by the main control card 1, and therefore, the main control card 1 and the main control card 2 can be connected with the target chip through one third link.
The port sharing device provided by the embodiment of the present invention is introduced below, and the port sharing device described below and the port sharing method described above may be referred to correspondingly.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a port sharing device according to an embodiment of the present invention, including:
a detection module 610, configured to, when a handover signal is detected, obtain a link state corresponding to a target link between target chips; wherein, the target chip is connected with the port;
a closing module 620, configured to close the target link when the link status is setup;
an establishing module 630, configured to establish the target link when the link status is off.
Optionally, the method further comprises:
the initialization configuration module is used for performing initialization configuration after power-on is detected;
the judging module is used for acquiring the identity information and judging whether the equipment is shared by the main port or not by utilizing the identity information;
the first establishing module is used for establishing a target link with a target chip if the main port shares equipment;
and the first closing module is used for closing the target link if the target link is not the main port shared device.
Optionally, the establishing module 630 includes:
the link establishing unit is used for establishing a reset link, a serial management interface link and a serial-parallel transceiving link with the target chip by using the logic component when the target chip is the internet access chip;
the reset unit is used for resetting the target chip through the reset link;
and the configuration unit is used for configuring the target chip through the serial management interface link to complete the establishment of the target link.
Optionally, the shutdown module 620 includes:
and the serial-parallel receiving and transmitting link closing unit is used for closing the serial-parallel receiving and transmitting link through the serial management interface link by using the logic component when the target chip is the network port chip so as to complete the closing of the target link.
Optionally, the establishing module 630 includes:
the first setting unit is used for setting a first link and a second link between the processor and the logic component into a penetration state by using the logic component when the target chip is a serial port chip;
and the link establishing unit is used for establishing a third link between the logic component and the target chip to complete the establishment of the target link.
Optionally, the shutdown module 620 includes:
and the second setting unit is used for setting the first link and the second link to be in a high-impedance state when the target chip is a serial port chip, and finishing the closing of the target link.
By applying the port sharing device provided by the embodiment of the invention, when the switching signal is detected, the debugged port sharing equipment can be determined to change, so that the link state of the target link is obtained, and the link state can represent the communication state of the port sharing equipment and the target chip. Because the target chip is connected with the debugging line, the link state of the target link can represent the communication state of the port shared equipment and the debugging line. When the link state is the establishment state, the state is that the link state is originally the debugged port sharing equipment but not the debugged port sharing equipment, so that the target link is closed so that the debugged port sharing equipment establishes the target link; when the link status is off, it indicates that the link is not the debugged port sharing device but now, and thus the target link is established. The target link is established or closed according to the link state, the common equipment of a plurality of ports can be debugged through the target chip when one debugging line and one port are used, the debugging line does not need to be plugged or pulled, or a plurality of debugging lines are adopted, and the debugging efficiency is improved while the material cost is saved.
The port sharing device provided by the embodiment of the present invention is introduced below, and the port sharing device described below and the port sharing method described above may be referred to correspondingly.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a port sharing device according to an embodiment of the present invention. Wherein the port sharing device 700 may include a processor 701 and a memory 702, and may further include one or more of a multimedia component 703, an information input/information output (I/O) interface 704, and a communication component 705.
The processor 701 is configured to control the overall operation of the port sharing apparatus 700, so as to complete all or part of the steps in the port sharing method; memory 702 is used to store various types of data to support the operation of porter 700, such data can include, for example, instructions for any application or method operating on the porter 700, as well as application-related data. The Memory 702 may be implemented by any type or combination of volatile and non-volatile Memory devices, such as one or more of Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic or optical disk.
The multimedia components 703 may include screen and audio components. Wherein the screen may be, for example, a touch screen and the audio component is used for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may further be stored in the memory 702 or transmitted through the communication component 705. The audio assembly also includes at least one speaker for outputting audio signals. The I/O interface 704 provides an interface between the processor 701 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is used for wired or wireless communication between the port sharing device 700 and other devices. Wireless Communication, such as Wi-Fi, bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them, so that the corresponding Communication component 707 may include: Wi-Fi part, Bluetooth part, NFC part.
The port sharing Device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, and is used to implement the port sharing method provided by the above embodiments.
The following describes a computer-readable storage medium provided by an embodiment of the present invention, and the computer-readable storage medium described below and the port sharing method described above may be referred to correspondingly.
The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the port sharing method described above.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relationships such as first and second, etc., are intended only to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms include, or any other variation is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The port sharing method, the port sharing apparatus, the port sharing device, the port sharing system and the computer readable storage medium provided by the present invention are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method of port sharing, comprising:
when the switching signal is detected, acquiring a link state corresponding to a target link between target chips; wherein, the target chip is connected with the port;
when the link state is established, closing the target link;
and when the link state is closed, establishing the target link.
2. The port sharing method according to claim 1, further comprising, before detecting the switching signal:
when power-on is detected, performing initialization configuration;
acquiring identity information, and judging whether the equipment is shared by a main port or not by using the identity information;
if the main port is the shared device, the target link between the main port and the target chip is established;
and if the target link is not the main port shared device, closing the target link.
3. The port sharing method according to claim 1, wherein said establishing the target link comprises:
when the target chip is an internet access chip, a reset link, a serial management interface link and a serial-parallel transceiving link with the target chip are established by using a logic component;
resetting the target chip through the reset link;
and configuring the target chip through the serial management interface link to complete the establishment of the target link.
4. The port sharing method of claim 3, wherein said shutting down the target link comprises:
and when the target chip is the internet access chip, the logic component is utilized to shut off the serial-parallel transceiving link through the serial management interface link, so as to complete the closing of the target link.
5. The port sharing method according to claim 1, wherein said establishing the target link comprises:
when the target chip is a serial port chip, setting a first link and a second link between a processor and the logic component to be in a penetration state by using the logic component;
and establishing a third link between the logic component and the target chip to complete the establishment of the target link.
6. The port sharing method of claim 5, wherein said shutting down the target link comprises:
and when the target chip is the serial port chip, setting the first link and the second link to be in a high-impedance state, and finishing the closing of the target link.
7. A port sharing device, comprising:
the detection module is used for acquiring a link state corresponding to a target link between target chips when the switching signal is detected; wherein, the target chip is connected with the port;
a closing module, configured to close the target link when the link status is established;
and the establishing module is used for establishing the target link when the link state is closed.
8. A port sharing device comprising a memory and a processor, wherein:
the memory is used for storing a computer program;
the processor for executing the computer program to implement the port sharing method of any one of claims 1 to 6.
9. A port sharing system, comprising a first port sharing device, a second port sharing device, and a target chip, wherein:
the target chip is connected with the port;
when a switching signal is detected, the first port shared device acquires a first link state corresponding to a first target link between the target chips, and the second port shared device acquires a second link state corresponding to a second target link between the target chips;
when the first link state is established, the first port shared device closes the first target link; when the second link state is established, the second port shared device closes the second target link;
when the first link state is closed, the first port shared device establishes the first target link; and when the second link state is closed, the second port shared device establishes the second target link.
10. A computer-readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the port sharing method of any one of claims 1 to 6.
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| CN202010559651.XA CN111708726A (en) | 2020-06-18 | 2020-06-18 | Port sharing method, device, equipment, system and readable storage medium |
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Application publication date: 20200925 |