CN111695316B - On-chip network test planning method based on improved hybrid algorithm - Google Patents

On-chip network test planning method based on improved hybrid algorithm Download PDF

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CN111695316B
CN111695316B CN202010536487.0A CN202010536487A CN111695316B CN 111695316 B CN111695316 B CN 111695316B CN 202010536487 A CN202010536487 A CN 202010536487A CN 111695316 B CN111695316 B CN 111695316B
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胡聪
信文雪
朱爱军
许川佩
梁志勋
黄喜军
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Abstract

The invention discloses a network-on-chip test planning method based on an improved hybrid algorithm, which comprises the steps of introducing a reverse learning strategy to increase the diversity of an initial population; then adding dynamic inertia weight w and cross probability factor CR to respectively improve particle swarm algorithm (PSO) and differential learning algorithm (DE) so as to increase randomness and ergodic property of population; and combining an improved particle swarm algorithm with an improved differential algorithm, and implementing test planning on the NoC to improve network-on-chip test efficiency and reduce test cost and power consumption generated in the test process.

Description

On-chip network test planning method based on improved hybrid algorithm
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a network-on-chip test planning method based on an improved hybrid algorithm.
Background
The design of integrated circuits is also being improved with the continued development of semiconductor manufacturing processes. At present, the development of chip integration technology has achieved a qualitative leap, and it is possible to integrate numerous processor cores onto the same chip, so that the cost for testing the performance of the chip is higher and higher, and the time spent is longer and longer. Testing is therefore becoming increasingly important in the development of integrated circuits. The Network on Chip (NoC) transfers the idea of computer Network to the design of integrated circuit Chip, thoroughly changes the bus communication mode in the SoC (System on Chip), instead, can realize the multiprocessor System on a single Chip, and the architecture fundamentally solves the technical bottleneck problem brought by the SoC bus. Compared with the traditional bus structure, the NoC has the advantages of strong parallelism, low power consumption and the like, and has larger advantages in the aspect of expansibility. Nocs have therefore become the primary communication structure for many-core systems on chip. Although the network-on-chip proposal has overcome the limitation of the system-on-chip on the communication bandwidth and the expandability, solves the defect of the shared bus architecture of the system-on-chip, reduces the design complexity of the system-on-chip, and makes the testing of the IP cores in the network-on-chip more difficult along with the large increase of the number of the cores to be tested. How to more efficiently complete network-on-chip testing under multiple constraints of power consumption, bandwidth, etc. has become a research hotspot.
Disclosure of Invention
The invention aims to solve the problems of low testing efficiency and long testing time in the network-on-chip testing process and provides a network-on-chip testing planning method based on an improved hybrid algorithm.
In order to solve the problems, the invention is realized by the following technical scheme:
an on-chip network test planning method based on an improved hybrid algorithm specifically comprises the following steps:
step 1, setting a population scale n and a maximum iteration number run max
Step 2, distributing the IP cores to be tested of the network on chip into a hypercube topological structure according to a preset distribution principle through a mapping algorithm;
step 3, scheduling and testing the IP cores to be tested distributed in the hypercube topological structure by utilizing an E-cube routing algorithm with partial self-adaptation capability to obtain a test planning path;
step 4, randomly selecting n test planning paths from the test planning paths obtained in the step 3 to form an initial population, and recoding the n selected test planning paths of the initial population by introducing a reverse learning strategy to obtain n new test planning paths to form a reverse population;
step 5, selecting n test planning paths with shorter test time from the initial population and the reverse population obtained in the step 4 to form an initial population;
step 6, equally dividing the initialized population obtained in the step 5 into two populations, namely an initial PSO population and an initial DE population; wherein each of the initial PSO population and the initial DE population comprises n/2 test planning paths, namely individuals;
step 7, based on the current inertia weight factor w, updating the speed and the position of all individuals in the current PSO population by using a PSO algorithm, and selecting an individual with the shortest test time from the updated speed and the updated position as a PSO optimal individual;
step 8, based on the current crossover probability factor CR, carrying out mutation, crossover and selection operation on all individuals in the current DE population by using a DE algorithm, and selecting an individual with the shortest test time from the current DE population as the optimal DE individual;
step 9, judging whether the current iteration number run reaches the maximum iteration number run max
If so, comparing the test time of the PSO optimal individual and the test time of the DE optimal individual, taking the optimal individual with shorter test time as the optimal individual of the whole population, taking the optimal individual as the final network-on-chip test planning path to output, and ending the algorithm;
if not, adjusting the inertia weight w of the PSO population and the cross probability factor CR of the DE population, and returning to the step 7 for continuous iteration.
In the step 1, the allocation principle is that the test time of the IP cores allocated in the subcube is equal to the test power consumption.
In the above step 9, the adjustment formula of the inertia weight w is:
Figure BDA0002537227840000021
wherein w is max And w min Representing given maximum and minimum inertial weight factors, run being the current iteration number, run max For a given maximum number of iterations.
In the above step 9, the adjustment formula of the crossover probability factor CR is:
Figure BDA0002537227840000022
wherein CR is max And CR (CR) min Representing given maximum and minimum crossover probability factors, run being the current iteration number, run max For a given maximum number of iterations.
Compared with the prior art, the invention has the following characteristics:
1. introducing a reverse learning strategy to increase the diversity of the initial population;
2. adding dynamic inertia weight w and cross probability factor CR to respectively improve particle swarm algorithm (PSO) and differential learning algorithm (DE) so as to increase randomness and ergodic property of population;
3. the improved particle swarm algorithm is combined with the improved differential algorithm, and the NoC is subjected to test planning, so that the network-on-chip test efficiency is improved, and the test cost and the power consumption generated in the test process are reduced.
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Fig. 1 is a schematic diagram of a hypercube topology.
Fig. 2 is a flow chart of an E-cube part adaptive routing algorithm.
Fig. 3 is a four-dimensional hypercube topology.
Fig. 4 is a 2×2×4 3d Mesh structure.
FIG. 5 is a flow chart of NoC test planning.
FIG. 6 is a graph comparing the test results of the present invention with the test results of the modified IBA and modified IFA algorithms, wherein (a) is the test result of d695 and (b) is the test result of g 1023.
Detailed Description
The invention will be further described in detail below with reference to specific examples and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the invention more apparent.
In order to optimize test time and improve test efficiency of network on chip (NoC) resource cores, and combine the NoC test characteristics, the invention provides a network on chip test planning method based on an improved hybrid algorithm, which comprises the following steps: the method specifically comprises the following steps:
(1) The plurality of IP cores are distributed into the hypercube topology structure (four-dimensional and above) according to a certain distribution principle through a mapping algorithm.
The topology determines the manner in which the IP cores, routers, and communication links in the NoC are connected, largely determining the performance and cost of the system. The hypercube topology structure not only has the characteristics of good symmetry, strong expandability and the like of the 3D Mesh structure, but also has short network diameter and high connectivity, so the hypercube structure is selected as the topology structure in NoC test planning research.
Determining the number of IP cores and related parameter information, the number of flags when the test is completed, the number of TAM strips, the maximum allowable total power consumption set by the system, the power consumption constraint of each subcube, selecting part of nodes in the hypercube structure as input/output ports and the like. The invention distributes IP cores in a circuit into a hypercube topology structure (taking four dimensions as an example) according to the principle that the test time and the test power consumption of the IP cores distributed in a subcube are approximately equal, as shown in figure 1.
(2) Aiming at the self structural characteristics of the hypercube, an E-cube routing algorithm with partial self-adaption capability is utilized to conduct scheduling test on the IP core, and N test planning paths are obtained, wherein N is a set value.
The E-cube routing algorithm is a deterministic routing algorithm, is simple to realize, is irrelevant to the current network state when data is transmitted by a selected path, cannot be dynamically adjusted according to the network state, and lacks self-adaptability. Currently, for networks with smaller network scale and low traffic, a deterministic routing algorithm is generally selected in the test process; for networks with larger network scale and higher traffic, an adaptive routing algorithm is generally selected. Because the traffic in the network on chip is not fixed in most cases, the invention considers the two, and applies the E-cube routing algorithm with partial self-adaption capability to the hypercube topology structure so as to increase the utilization rate of the routing nodes and the communication links in the test process.
The E-cube routing algorithm with partial self-adaption capability adopts a low-dimensional priority principle, and data output is controlled by setting the priority of an output port. In the data transmission process, firstly judging whether the initial node is the same as the target node, if so, transmitting test data to the IP core where the node is located, otherwise, judging whether the one-dimensional direction in the next-hop node is occupied, if not, transmitting the test data to the node, otherwise, judging the two-dimensional direction of the next-hop node. And so on, successively to the high dimension. This avoids the problem of deadlock of a dimension of the deterministic routing algorithm due to congestion. The specific process is shown in fig. 2.
A comparative analysis is now made by taking a four-dimensional hypercube structure with 16 routing nodes as an example with a 3D Mesh structure with the same network size 2 x 4. In fig. 3 and 4, the black sphere represents the input port and the core to be tested, respectively, and the portion indicated by the black arrow represents the path taken by the routing algorithm. As can be seen by comparison, the number of routers and links passing through in the test process of FIG. 3 is significantly lower than that of FIG. 4, and for the hypercube structure, the higher the dimension, the more obvious the optimization effect.
When all the IP cores in the system are tested, the end time of the last tested IP core is taken as the adaptability value of the whole system. Since multiple TAMs are tested in parallel, the time of one TAM with the longest test time is calculated as the population fitness function according to the following formula:
Figure BDA0002537227840000041
wherein B represents the number of TAM strips; k (k) j Representing the number of IP cores on the jth TAM; t (T) testi The test time of the representative IP core i comprises the time spent on testing the IP core itself and the routing time of the test data packet.
(3) A test planning study was performed on nocs using a modified hybrid algorithm, i.e., a combination of modified particle swarm algorithm (Particle Swarm Optimization, PSO) and modified differential algorithm (Differential Evolution, DE).
The research shows that the PSO algorithm and the DE algorithm are used as efficient intelligent group optimization algorithms, have the advantages of good robustness, simplicity and easiness in operation, capability of rapidly finding out a local optimal solution and the like, show excellent performance on a plurality of problems, and become a hotspot in the research field of modern optimization methods at present. However, a single algorithm has a certain contradiction between calculation accuracy and calculation speed, and in order to overcome the defects of the single algorithm, the idea of combining two or more algorithms is paid attention to. Aiming at the intelligent group optimization algorithm, along with the continuous increase of the iteration times, the diversity of the algorithm is gradually reduced and the phenomena of early maturing and the like are easily caused, and a hybrid algorithm based on the combination of an improved PSO algorithm and an improved DE algorithm is applied to the intelligent group optimization algorithm.
In practical intelligent algorithms, most of the initialized population of the algorithm is generated by a random method, so that the generated population cannot be guaranteed to be uniformly distributed in a solution space, and the efficiency of the solution algorithm is limited to a certain extent. In order to make the initial population have higher efficient population diversity and randomness, the invention combines an opposite-based learning (OBL) strategy to initialize the population. The reverse learning algorithm was first proposed by Tizhoosh teachings in 2005. The basic idea is as follows: in each search of the algorithm, first, an initial solution is uniformly and randomly generated, then, an inverse solution corresponding to each initial solution is generated according to each initial solution, individuals with higher adaptability are selected between the initial solution and the inverse solution, the individuals are placed into a final initial population, and the final initial population is applied to the evolution algorithm.
According to the invention, a reverse learning strategy is introduced first, so that the initial population is improved, and the randomness and diversity of the initial population are increased. Then, the populations are randomly divided into two independent groups, one group of the populations is evolved by adopting an evolution mechanism of a particle swarm algorithm, the other group of the populations is evolved by adopting an evolution mechanism of a differential evolution algorithm, and in the whole process of evolution optimization, an information exchange mechanism is introduced between the two populations to exchange the information of excellent individuals among the populations. Therefore, each population can greatly improve the performance of the whole algorithm by absorbing the information of excellent individuals from the other population, and the defects of the two algorithms in the process of independent optimization are effectively overcome. In addition, the nonlinear dynamic improved inertia weight w and the dynamic cross probability factor CR are introduced to respectively improve the PSO algorithm and the DE algorithm, so that the randomness and the ergodic performance of the population are increased, the convergence speed of the hybrid algorithm in the late stage is improved, and the whole optimizing capability of the hybrid algorithm is enhanced to a certain extent.
According to the NoC test, the optimal solution with the shortest test time and the lowest test power consumption in the test process can be efficiently and accurately found out by improving the mixing algorithm. Firstly, adopting a mapping rule, and enabling the sum of the test time and the test power consumption of the IP cores distributed in each subcube topological structure to be approximately equal. And secondly, increasing the population diversity distributed by each IP core to a plurality of TAMs through a reverse learning strategy. And finally, adding an inertia weight factor and a dynamic cross probability factor in the query process of the optimal solution to enhance the searching capability of the algorithm and reduce the searching time.
A flow chart of the improved mixing algorithm is shown in fig. 5. Combining NoC test characteristics and an adjustment strategy for an improved PSO algorithm and an improved DE algorithm, a NoC test flow based on an improved hybrid algorithm mainly comprises: initializing population, evaluating fitness values, adjusting adaptive parameters, updating population information, and the like. The specific implementation is as follows:
1) And randomly selecting N test planning paths from the N obtained test planning paths to form an initial population, and recoding the N selected test planning paths of the initial population by introducing a reverse learning strategy to obtain N new test planning paths to form a reverse population.
By introducing a reverse learning strategy, the assignment order of IP cores in each test planning path in the initial population can be recoded. For example, let x= (x) 1 ,x 2 ,…,x D ) Is a point in D-dimensional space, and x 1 ,x 2 ,…,x D ∈R,x j ∈[a j ,b j ],a j Representing the minimum coding of the split IP cores on the TAM. b j Representing the maximum encoding of the separated IP cores on the TAM. The inverse point x corresponding to x * =(x 1 * ,x 2 * ,…,x D * ) Wherein: x is x j * =a j +b j -x j . Based on the reverse learning strategy, a reverse population corresponding to the initial population can be generated according to the initial population, so that the diversity of the initial distribution population of particles is increased.
2) And taking the test time as a fitness value, and selecting n test planning paths with smaller fitness values (namely shorter test time) from the initial population and the reverse population to form an initial population.
3) The initialized population is aliquoted into two populations, an initial PSO population and an initial DE population. Wherein each of the initial PSO population and the initial DE population includes n/2 test plan paths (i.e., individuals).
4) Based on the current inertia weight factor w, updating the speed and the position of all individuals in the current PSO population by using a PSO algorithm, and selecting an individual with the best fitness value (namely the shortest test time) from the updated speed and the updated position as a PSO optimal individual pbest.
During each iteration period, the PSO algorithm realizes the search of searching the optimal position in the search space by tracking two parameter indexes, namely, the optimal individual fitness value which can be found by the particle through the particle is the optimal individual value pbest. The speed of flight and location updates in the search space are implemented as follows:
Figure BDA0002537227840000051
Figure BDA0002537227840000052
wherein w represents inertial weight; r is (r) 1 And r 2 Is distributed in [0,1]]Two uniform random numbers in between; c 1 And c 2 Are learning factors of particles; v max The maximum value of the particle speed in the particle flight process is used for restricting the particle speed and improving the search result.
5) Based on the current crossover probability factor CR, the DE algorithm is utilized to implement mutation, crossover and selection operations on all individuals in the current DE population, and the individual with the best fitness value (namely the shortest test time) is selected as the DE optimal individual pbest.
In the DE algorithm, firstly, mutation operation is carried out on an individual, and then the mutated individual and parameters of a target individual are mixed according to a certain rule to generate a test individual. And then comparing the evaluation function between the experimental individual and the target individual, and selecting and storing the optimal individual pbest.
Mutation operation: for each individual member of the population according to the following
Figure BDA0002537227840000061
Performing mutation operation to generate new variant +.>
Figure BDA0002537227840000069
Figure BDA0002537227840000063
Wherein,,
Figure BDA0002537227840000064
is a differential vector. F is [0,1]]The value of which has a great influence on the global optimizing ability of the algorithm.
Crossover operation: when the probability has a value of 0,1]When the individual
Figure BDA0002537227840000065
And individuals after mutation->
Figure BDA0002537227840000066
Crossing to obtain a new individual; otherwise, the original value is:
Figure BDA0002537227840000067
selection operation: comparing the size of the evaluation function between the target individual and the test individual obtained in the previous step, selecting the individual with better effect from the evaluation function, directly reserving the individual to the next generation, and directly eliminating the individual with poor evaluation function.
6) Judging whether the current iteration number run reaches the maximum iteration number run max
If so, comparing the fitness value of the PSO best individual pbest and the DE best individual pbest, taking the best individual pbest with the better fitness value (namely smaller test time) as the best individual gbest of the whole population, taking the best individual gbest as the final network-on-chip test planning path to output, and ending the algorithm.
If not, adding 1 to the current iteration number run, adjusting the inertia weight w of the PSO population and the cross probability factor CR of the DE population, and returning to 4) for continuous iteration.
In the PSO algorithm, the value of the inertia weight w is important. Research shows that the larger the value of w, the greater the influence degree of the current speed of the particles on the next generation speed, the faster the particles fly, and the stronger the global searching capability. The smaller the value of w, the smaller the influence degree of the current speed of the particles on the next generation speed, and the more favorable the local search of the algorithm. Thus, by improving the magnitude of the value of w, the speed term of the improved PSO algorithm can be improved. According to the iterative process and the particle flight state, the value of w is dynamically adjusted to linearly change, so that the purposes of convergence speed and global convergence balance in the searching process are achieved. The specific calculation formula is as follows:
Figure BDA0002537227840000068
wherein w is max And w min Representing given maximum and minimum inertial weight factors, run being the current iteration number, run max Is the maximum number of iterations. Due to inertial weight at [0.4,0.9 ]]The algorithm can obtain better optimizing performance in the range, so the invention takes w max =0.9,w min =0.4。
The crossover probability factor CR is taken as a very important parameter in the DE algorithm, the value range of the crossover probability factor CR is between [0,1], and the contribution degree of a variant individual to an experimental individual is determined by the parameter. The larger the CR value is, the larger the contribution of the variant individual to the test individual is, which is more beneficial to accelerating the convergence rate of the whole algorithm and improving the local searching capability of the algorithm. Conversely, the smaller the CR value, the less the variant will contribute to the test individual, and the more advantageous it is to maintain diversity in the population. Thus, by a reasonable adjustment of CR, the algorithm's balance between local and global searches can be coordinated. The invention adopts a linear cross probability factor adjustment strategy to effectively improve the value of CR, and the specific calculation formula is as follows:
Figure BDA0002537227840000071
wherein CR is max And CR (CR) min Representing given maximum and minimum crossover probability factors, run being the current iteration number, run max Is the maximum number of iterations. CR is generally taken max =0.9,CR min =0.1。
In order to verify the effectiveness of the invention, circuits such as d695 and g1023 are selected from the ITC'02 international standard circuit test set, and relevant parameters such as the number of input/output ports of the IP core, the number of test vectors, test time and test power consumption required in the test process are extracted from the circuits to carry out simulation experiments. First, the hypercube topology is encoded and individual IP cores are allocated into the topology using a mapping method. Then, an improved hybrid algorithm is adopted, namely, a reverse learning strategy is introduced to increase the randomness and the ergodic performance of the initial population, a dynamic inertia weight w and a crossover probability factor CR are added to respectively improve a particle swarm algorithm and a differential learning algorithm, and the randomness and the ergodic performance of the population are increased.
The distribution of the IP core mapping in two circuits to cores in a 2 x 2 four-dimensional hypercube structure is given in table 1. The mapping rules followed are: the sum of the test time, the test power consumption of the IP cores themselves arranged in each subcube topology is made approximately equal.
TABLE 1 setting of cores in reference circuits
Figure BDA0002537227840000072
In order to verify the influence of the algorithm provided by the invention on the test time, more experimental objects need to be compared. The total power consumption and the subcube power consumption are set to be 50% of the system power consumption, and three circuits d695, g1023 and p93791 are respectively tested under different TAM number limits. The results were compared with the Improved Bat Algorithm (IBA) and the Improved Firefly Algorithm (IFA) previously proposed, and are shown in fig. 6.
As can be seen from the test results of the two circuits in fig. 6: as the number of TAMs increases, the test time gradually decreases, with the magnitude of the decrease in test time increasing as the number of TAMs increases from two to three, and decreasing as the number of TAMs continues to increase to five. This is because as the number of TAMs increases, the number of IP core tests increases at the same time, the parallelism of the tests increases, and the contention for IP core test resources becomes more and more intense. The searching result of the algorithm is superior to the other two algorithms, so that the algorithm has good optimizing capability.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.

Claims (4)

1. The on-chip network test planning method based on the improved hybrid algorithm is characterized by comprising the following steps of:
step 1, setting a population scale n and a maximum iteration number run max
Step 2, distributing the IP cores to be tested of the network on chip into a hypercube topological structure according to a preset distribution principle through a mapping algorithm;
step 3, scheduling and testing the IP cores to be tested distributed in the hypercube topological structure by utilizing an E-cube routing algorithm with partial self-adaptation capability to obtain a test planning path;
step 4, randomly selecting n test planning paths from the test planning paths obtained in the step 3 to form an initial population, and recoding the n selected test planning paths of the initial population by introducing a reverse learning strategy to obtain n new test planning paths to form a reverse population;
step 5, selecting n test planning paths with shorter test time from the initial population and the reverse population obtained in the step 4 to form an initial population;
step 6, equally dividing the initialized population obtained in the step 5 into two populations, namely an initial PSO population and an initial DE population; wherein each of the initial PSO population and the initial DE population comprises n/2 test planning paths, namely individuals;
step 7, based on the current inertia weight factor w, updating the speed and the position of all individuals in the current PSO population by using a PSO algorithm, and selecting an individual with the shortest test time from the updated speed and the updated position as a PSO optimal individual;
step 8, based on the current crossover probability factor CR, carrying out mutation, crossover and selection operation on all individuals in the current DE population by using a DE algorithm, and selecting an individual with the shortest test time from the current DE population as the optimal DE individual;
step 9, judging whether the current iteration number run reaches the maximum iteration number run max
If so, comparing the test time of the PSO optimal individual and the test time of the DE optimal individual, taking the optimal individual with shorter test time as the optimal individual of the whole population, taking the optimal individual as the final network-on-chip test planning path to output, and ending the algorithm;
if not, adjusting the inertia weight w of the PSO population and the cross probability factor CR of the DE population, and returning to the step 7 for continuous iteration.
2. The network-on-chip test planning method according to claim 1, wherein in step 1, the allocation rule is that the test time and the test power consumption of the IP cores allocated in the subcube are equal.
3. The method for planning network-on-chip testing based on improved hybrid algorithm of claim 1, wherein in step 9, the adjustment formula of the inertia weight w is:
Figure FDA0002537227830000011
wherein w is max And w min Representing given maximum and minimum inertial weight factors, run being the current iteration number, run max For a given maximum number of iterations.
4. The method for network-on-chip test planning based on improved hybrid algorithm of claim 1, wherein in step 9, the adjustment formula of the crossover probability factor CR is:
Figure FDA0002537227830000021
wherein CR is max And CR (CR) min Representing given maximum and minimum crossover probability factors, run being the current iteration number, run max For a given maximum number of iterations.
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