CN111693847A - Chip testing method and device - Google Patents
Chip testing method and device Download PDFInfo
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- CN111693847A CN111693847A CN202010419859.1A CN202010419859A CN111693847A CN 111693847 A CN111693847 A CN 111693847A CN 202010419859 A CN202010419859 A CN 202010419859A CN 111693847 A CN111693847 A CN 111693847A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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Abstract
The embodiment of the application discloses a chip testing method and device. The method comprises the following steps: after detecting that a wafer CP test is carried out on a chip, acquiring output delay information of an input/output (IO) port of the chip, which is used for outputting a return result of a test vector; controlling the value of the output time delay to be reduced; and outputting a return result of the test vector according to the reduced output delay.
Description
Technical Field
The embodiment of the application relates to the field of information processing, in particular to a chip testing method and device.
Background
An integrated circuit Chip generally includes a CPU state and a test state, and before becoming a product, the integrated circuit Chip is subjected to wafer level CP (Chip bonding, wafer test) test in the test state. The clock and data of the pattern are Input into the chip through an Input/Output (IO) port for use, and the result is returned to the CP machine after the operation inside the chip is completed.
In practical applications, the efficiency of CP testing needs to be improved.
Disclosure of Invention
In order to solve any one of the above technical problems, embodiments of the present application provide a chip testing method and apparatus.
In order to achieve the purpose of the embodiments of the present application, an embodiment of the present application provides a chip testing method, including:
after detecting that a wafer CP test is carried out on a chip, acquiring output delay information of an input/output (IO) port of the chip, which is used for outputting a return result of a test vector;
controlling the value of the output time delay to be reduced;
and outputting a return result of the test vector according to the reduced output delay.
A chip testing apparatus, comprising:
the acquisition module is used for acquiring output delay information of an input/output (IO) port of a chip used for outputting a return result of a test vector after detecting that a wafer CP test is performed on the chip;
a control module configured to control a decrease in a value of the output delay;
and the output module is set to output the return result of the test vector according to the reduced output delay.
A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method as described above when executed.
An electronic device comprising a memory having a computer program stored therein and a processor arranged to execute the computer program to perform the method as described above.
One of the above technical solutions has the following advantages or beneficial effects:
after the wafer CP test of the chip is detected, the output delay information of the IO port of the returned result of the test vector is obtained, the numerical value of the output delay is controlled to be reduced, the returned result of the test vector is output according to the reduced output delay, the output speed of the returned result can be effectively improved by reducing the output delay of the IO port, the purpose of improving the test frequency is achieved, and therefore the CP test efficiency is improved.
Additional features and advantages of the embodiments of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the examples of the embodiments of the present application do not constitute a limitation of the embodiments of the present application.
Fig. 1 is a flowchart of a chip testing method provided in an embodiment of the present application;
fig. 2 is a structural diagram of a chip testing apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the embodiments of the present application, features in the embodiments and the examples may be arbitrarily combined with each other without conflict.
In the process of implementing the present application, the inventor conducts technical analysis on the related art, and finds that the related art has at least the following problems, including:
the CP machine test mainly works at about 10MHz, but the CP machine can not provide a higher frequency clock, the main reason is determined by the IO communication speed of the integrated circuit chip, and the IO communication speed of the integrated circuit chip is slow in the return stage.
Based on the above analysis, the embodiments of the present application provide the following solutions:
fig. 1 is a flowchart of a chip testing method according to an embodiment of the present disclosure. As shown in fig. 1, the method shown in fig. 1 includes:
in one exemplary embodiment, the default driving force for the IO port is configured to be low for various reasons of power consumption and application for the integrated circuit chip. In the CPU state the software will change these default parameters to suit the application. However, the test state is not as flexible as the CPU state, and when the default driving force is low and the load capacitance of the IO external pin card is large, the output transmission delay is increased.
By obtaining the output delay information of the IO port of the chip for outputting the return result of the test vector, the current state of the output delay in the CP test can be determined, and the subsequent adjustment of the output delay is facilitated.
in an exemplary embodiment, the signal output is a square wave, which becomes a triangular wave or a ramp wave due to the increase of the transmission delay, and finally the CP station cannot correctly recognize the high and low levels, i.e. the data.
In the related art, the CP apparatus works at a frequency of about 10MHz, and a sampling time point of the CP apparatus for the output data is greater than a transmission delay time. Different from the above, the method provided by the embodiment of the application automatically reduces the output delay, and solves the problem that the big test state output delay data cannot be correctly identified.
And 103, outputting a return result of the test vector according to the reduced output delay.
In an exemplary embodiment, since the output delay in the test state is reduced, the output speed of the returned result can be effectively increased, so that the output efficiency of the returned result is effectively increased, and the purpose of increasing the efficiency of the CP test is achieved.
According to the method provided by the embodiment of the application, after the wafer CP test is carried out on the chip, the output time delay information of the IO port of the return result of the test vector is obtained, the numerical value of the output time delay is controlled to be reduced, the return result of the test vector is output according to the reduced output time delay, the output speed of the return result can be effectively improved by reducing the output time delay of the IO port, the purpose of improving the test frequency is achieved, and therefore the CP test efficiency is improved.
In one exemplary embodiment, whether to perform a CP test on a chip is detected by:
identifying the time sequence of the received signal to obtain time sequence information, and determining to start CP testing on the chip if the time sequence information conforms to a preset testing time sequence; alternatively, the first and second electrodes may be,
detecting a preset input/output (IO) port for executing test operation, and if the IO port receives a signal, determining to start CP test on the chip.
Whether the CP test is carried out on the chip or not is determined by detecting whether the chip receives a special time sequence or a preset IO port for the CP test, and the method is simple and convenient to implement.
In an exemplary embodiment, the controlling the decrease in the value of the output delay includes:
acquiring the level information of the driving force of the IO port of the chip in a test state;
and increasing the level information of the driving force of the IO port.
Because the default value of the IO driving force of the chip is low level, the IO driving force is automatically increased under the test state, so that the output delay is reduced, but the configuration of the lower driving force of the CPU state is not influenced, thereby not influencing the normal application and the power consumption, and solving the problem that the output delay big data of the test state cannot be correctly identified
Once the chip enters the test state, the IO driving force is automatically configured by the hardware to a larger level. Therefore, the IO driving force of the CPU chip can be kept at a lower level, the IO driving force of the test chip can be changed into a higher level, and the requirement of testing speed is met.
In an exemplary embodiment, the controlling the decrease in the value of the output delay includes:
acquiring the working frequency of a CP (provider) machine used for receiving the returned result of the test vector;
and adjusting the size of the output time delay according to the working frequency.
When the output time delay is adjusted, the frequency of the test pattern is improved, the efficiency is improved, and the test cost is reduced on the premise of ensuring the correct identification and return of the CP machine by acquiring the working frequency of the CP machine and controlling the output time delay of the IO port according to the working frequency.
According to the method provided by the embodiment of the application, the driving force configuration of the IO is slightly changed, the configuration of the driving force by adding the test state mode information is added, the driving force of the chip IO is automatically changed to be in a larger level in the test state, the requirement of the test speed is met, the output delay of the test state can be reduced, the test pattern frequency is improved, the test efficiency is improved, and the test cost is reduced.
Fig. 2 is a structural diagram of a chip testing apparatus according to an embodiment of the present application. As shown in fig. 2, the apparatus shown in fig. 2 includes:
the acquisition module is used for acquiring output delay information of an input/output (IO) port of a chip used for outputting a return result of a test vector after detecting that a wafer CP test is performed on the chip;
a control module configured to control a decrease in a value of the output delay;
and the output module is set to output the return result of the test vector according to the reduced output delay.
In an exemplary embodiment, the obtaining module detects whether to perform a CP test on the chip by:
identifying the time sequence of the received signal to obtain time sequence information, and determining to start CP testing on the chip if the time sequence information conforms to a preset testing time sequence; alternatively, the first and second electrodes may be,
detecting a preset input/output (IO) port for executing test operation, and if the IO port receives a signal, determining to start CP test on the chip.
In one exemplary embodiment, the control module includes:
the chip testing device comprises a first acquisition unit, a second acquisition unit and a control unit, wherein the first acquisition unit is used for acquiring the level information of the driving force of an IO port of the chip in a testing state;
an adjustment unit configured to increase level information of the driving force of the IO port.
In one exemplary embodiment, the control module includes:
the second acquisition unit is used for acquiring the working frequency of the CP machine used for receiving the return result of the test vector;
and the second adjusting unit is set to adjust the size of the output time delay according to the working frequency.
The device that this application embodiment provided, after detecting to carry out wafer CP test to the chip, acquire the output time delay information of the IO port of the return result of test vector controls the numerical value of output time delay reduces, according to the output time delay after reducing, exports the return result of test vector through reducing the output time delay of IO port, can effectively improve the output speed of returning the result, reaches the purpose that improves the test frequency to improve the efficiency of CP test.
A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the above when executed.
An electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the method of any of the above.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A method of chip testing, comprising:
after detecting that a wafer CP test is carried out on a chip, acquiring output delay information of an input/output (IO) port of the chip, which is used for outputting a return result of a test vector;
controlling the value of the output time delay to be reduced;
and outputting a return result of the test vector according to the reduced output delay.
2. The method of claim 1, wherein detecting whether to perform CP testing on the chip comprises:
identifying the time sequence of the received signal to obtain time sequence information, and determining to start CP testing on the chip if the time sequence information conforms to a preset testing time sequence; alternatively, the first and second electrodes may be,
detecting a preset input/output (IO) port for executing test operation, and if the IO port receives a signal, determining to start CP test on the chip.
3. The method of claim 1, wherein said controlling the decrease in the value of the output delay comprises:
acquiring the level information of the driving force of the IO port of the chip in a test state;
and increasing the level information of the driving force of the IO port.
4. The method of any of claims 1 to 3, wherein said controlling the decrease in the value of said output delay comprises:
acquiring the working frequency of a CP (provider) machine used for receiving the returned result of the test vector;
and adjusting the size of the output time delay according to the working frequency.
5. A chip testing apparatus, comprising:
the acquisition module is used for acquiring output delay information of an IO port, which is used for outputting a return result of a test vector, of a chip after the CP test of the chip is detected;
a control module configured to control a decrease in a value of the output delay;
and the output module is set to output the return result of the test vector according to the reduced output delay.
6. The apparatus of claim 5, wherein the obtaining module detects whether to perform a CP test on the chip by:
identifying the time sequence of the received signal to obtain time sequence information, and determining to start CP testing on the chip if the time sequence information conforms to a preset testing time sequence; alternatively, the first and second electrodes may be,
detecting a preset input/output (IO) port for executing test operation, and if the IO port receives a signal, determining to start CP test on the chip.
7. The apparatus of claim 1, wherein the control module comprises:
the chip testing device comprises a first acquisition unit, a second acquisition unit and a control unit, wherein the first acquisition unit is used for acquiring the level information of the driving force of an IO port of the chip in a testing state;
an adjustment unit configured to increase level information of the driving force of the IO port.
8. The apparatus of any of claims 5 to 7, wherein the control module comprises:
the second acquisition unit is used for acquiring the working frequency of the CP machine used for receiving the return result of the test vector;
and the second adjusting unit is set to adjust the size of the output time delay according to the working frequency.
9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when executed.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 4.
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