CN111684602B - Array substrate, manufacturing method thereof and display panel - Google Patents

Array substrate, manufacturing method thereof and display panel Download PDF

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Publication number
CN111684602B
CN111684602B CN201980000058.7A CN201980000058A CN111684602B CN 111684602 B CN111684602 B CN 111684602B CN 201980000058 A CN201980000058 A CN 201980000058A CN 111684602 B CN111684602 B CN 111684602B
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insulating layer
electrode
array substrate
layer
gate
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CN111684602A (en
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李栋
李小龙
李良坚
田宏伟
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The array substrate comprises a display pixel area for providing pixel units arranged in an array, and further comprises: the semiconductor device comprises a substrate base plate, a first insulating layer, a second insulating layer and a first conductive pattern layer. The first insulating layer is arranged on the substrate, and a groove is arranged in the first insulating layer and is arranged in the display pixel area; the second insulating layer is arranged on the first insulating layer, and the second insulating layer is also filled in the groove; the first conductive pattern layer is disposed on the second insulating layer. The array substrate can have better shock resistance and bending resistance by arranging the grooves.

Description

Array substrate, manufacturing method thereof and display panel
Technical Field
The embodiment of the disclosure relates to an array substrate, a manufacturing method thereof and a display panel.
Background
In the display field, an Organic Light Emitting Diode (OLED) display panel has the characteristics of self luminescence, high contrast, low energy consumption, wide viewing angle, high response speed, wide use temperature range, simple manufacture and the like, and has wide development prospect. With the development of flexible electronic technology, flexible display devices having foldable properties are increasingly popular. For example, in order to realize a narrow-frame or even a borderless display of the display device, a bending process may be performed on a non-display area of the display device; or the display device may be subjected to a bending process for portability. How to optimize the manufacturing process of the display panel is a concern in the art.
Disclosure of Invention
Some embodiments of the present disclosure provide an array substrate including a display pixel region for providing pixel units arranged in an array, the array substrate further including: the display device comprises a substrate base plate, a first insulating layer and a second insulating layer, wherein the first insulating layer is arranged on the substrate base plate, a groove is arranged in the first insulating layer, and the groove is arranged in the display pixel area; the second insulating layer is arranged on the first insulating layer, and the second insulating layer is also filled in the groove; and a first conductive pattern layer disposed on the second insulating layer.
In at least one example, the second insulating layer is an organic insulating layer.
In at least one example, the recess exposes the substrate base plate.
In at least one example, the first conductive pattern layer includes a gate line or a portion of the gate line for the display pixel region.
In at least one example, the groove includes a first portion that is parallel to or overlaps with the gate line in a direction perpendicular to the substrate base plate.
In at least one example, the pixel cell includes a first transistor including a first gate electrode on a side of the second insulating layer proximate to the substrate and electrically connected to the gate line through a first via in the second insulating layer.
In at least one example, the array substrate further includes a gate connection electrode between the second insulating layer and the first conductive pattern layer, the first gate electrode being electrically connected to the gate line through the gate connection electrode.
In at least one example, the first transistor further includes a first source and a first drain disposed in the same layer and of the same material as the gate connection electrode.
In at least one example, the array substrate further includes a data line for the display pixel region, the data line and the first source electrode and the first drain electrode being disposed in the same layer and being the same material; the groove further includes a second portion parallel to the data line or overlapping the data line in a direction perpendicular to the substrate base plate.
In at least one example, the pixel cell further includes a second transistor including a second gate connected to the first source or the first drain of the first transistor.
In at least one example, the grooves are distributed around the second gate.
In at least one example, the recess further includes a third portion parallel to and disposed in correspondence with the second gate; and in the length direction of the third groove, the length of the third part is larger than that of the second grid electrode.
In at least one example, the second transistor includes a second source electrode and a second drain electrode between the second insulating layer and the first conductive pattern layer in a direction perpendicular to the substrate base plate.
In at least one example, the array substrate further includes a third insulating layer between the second source and drain electrodes and the first conductive pattern layer in a direction perpendicular to the substrate.
In at least one example, the array substrate further includes a fourth insulating layer and a pixel electrode stacked over the first conductive pattern layer, and the second source electrode or the second drain electrode is electrically connected to the pixel electrode through a second via hole in the fourth insulating layer.
In at least one example, the first conductive pattern layer further includes a driving connection electrode through which the second source electrode or the second drain electrode is connected to the pixel electrode.
In at least one example, the array substrate further includes a first capacitive electrode disposed between the first insulating layer and the second insulating layer in a direction perpendicular to the substrate.
In at least one example, the array substrate further includes a second capacitor electrode disposed on the same layer as the first gate electrode and facing the first capacitor electrode to form a capacitance.
Some embodiments of the present disclosure further provide a display panel including the above array substrate.
Some embodiments of the present disclosure further provide a method for manufacturing an array substrate, where the array substrate includes a display pixel area for providing pixel units arranged in an array, and the method includes providing a substrate; forming a first insulating layer on the substrate base plate, and forming a groove on the first insulating layer, wherein the groove is formed in the display pixel area; forming a second insulating layer on the first insulating layer, wherein the second insulating layer is also filled in the groove; and forming a first conductive pattern layer on the second insulating layer.
In at least one example, the first insulating layer is an organic insulating layer.
In at least one example, forming the first conductive pattern layer includes: forming a gate line for the display pixel region or forming a portion of the gate line.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the disclosure;
FIG. 2 is an enlarged schematic view of a portion of an array substrate according to an embodiment of the disclosure;
FIG. 3 is a schematic cross-sectional view of FIG. 2 along section line A-A';
FIG. 4 is a schematic diagram of a display panel according to an embodiment of the disclosure;
fig. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
An array substrate for a display device or an electronic device having the same is easily damaged by external stress. In addition, as technology advances and consumer needs change, manufacturers will push flexible electronic devices with foldable display screens. For example, a flexible electronic device includes a flexible substrate, and various circuit structures, electronic devices, and the like prepared on the flexible substrate. Portions of the flexible electronic device (e.g., display area, pad area, etc.) may be folded and secured as desired, or folded as desired during use to adjust the positional relationship between the different portions (e.g., multi-screen cell phone). Due to the bending stress, the layer structure on the substrate base plate is easy to break and fall off, so that the risk of poor occurrence of the device structure is caused.
Some embodiments of the present disclosure provide an array substrate including a substrate and a display pixel region for providing pixel units arranged in an array, and including: the first insulating layer is arranged on the substrate base plate, and a groove is formed in the first insulating layer; the second insulating layer is arranged on the first insulating layer, and the second insulating layer is also filled in the groove; the first conductive pattern layer is disposed on the second insulating layer.
In some embodiments of the present disclosure, by providing a groove in a first insulating layer in a display pixel region of an array substrate and filling a second insulating layer into the groove, a contact area of the second insulating layer and the first insulating layer may be increased, thereby releasing internal stress that occurs in the second insulating layer during bending of the array substrate and is liable to cause breakage, and causing strain under the stress to mainly occur in the groove region (strain absorbing region); in addition, if cracks are generated in the stacked structure of the array during bending of the array substrate, the grooves may also block propagation of the cracks. Therefore, the arrangement of the above embodiments of the present disclosure can reduce or eliminate the risk of falling off of the second insulating layer and the structure (such as the first conductive pattern layer) thereon in the bending process of the array substrate, and improve the impact resistance and bending resistance of the device of the display pixel area of the array substrate, thereby improving the performance and yield of the product.
It should be noted that the groove structure is a structure which is set according to the need, and is different from a surface irregularity structure which is unavoidable in a conventional manufacturing method, and is also different from a via structure which plays a role in connection.
Fig. 1 is a schematic plan view of an array substrate according to some embodiments of the present disclosure. As shown, the array substrate 200 includes a display pixel area 210, and the display pixel area 210 is used for providing a plurality of pixel units 201 arranged in an array. The array substrate further includes a plurality of gate lines 71 extending along the first direction D1, a plurality of data lines 61 extending along the second direction D2, the plurality of gate lines and the data lines intersecting each other to define a plurality of pixel regions, and the plurality of pixel units 201 are distributed in the plurality of pixel regions in one-to-one correspondence.
For example, the array substrate may further include a data driving circuit 6 for supplying a data signal to the pixel unit 201 and a gate driving circuit 7; the gate driving circuit is used for providing scanning signals for the pixel unit 201; in addition, the array substrate may further include other circuits or devices for providing other various control signals. The data driving circuit and the gate driving circuit are connected to the pixel units 201 through the data lines 61 and the gate lines 71, respectively, and each pixel unit 201 is connected to the gate line 61, the data line 71, etc. to receive corresponding electrical signals to emit light, thereby realizing display operation.
For example, the array substrate may be an Organic Light Emitting Diode (OLED) array substrate, or an array substrate for liquid crystal display. Embodiments of the present disclosure will be specifically described below by taking the array substrate as an organic light emitting diode array substrate as an example, but the embodiments of the present disclosure are not limited thereto.
For example, each pixel unit 201 includes a light emitting element (i.e., OLED) and a pixel circuit that drives the light emitting element to emit light. For example, the pixel circuit may comprise a conventional 2T1C pixel circuit, i.e. comprising two transistors, one being a switching transistor and the other being a driving transistor, and one capacitor. For another example, the pixel circuit may be a pixel circuit of another structure, for example, a 3T1C pixel based on the foregoing 2T1C pixel or a pixel circuit further including a compensation function, a reset function, or the like, which is not limited in the embodiments of the present disclosure.
FIG. 2 is an enlarged schematic view of a portion of a layout of a pixel cell in an array substrate of a specific example of an embodiment; fig. 3 is a schematic cross-sectional view of fig. 2 along section line A-A'. For clarity, fig. 2 illustrates only the semiconductor layer 240, the gate layer 250, and the groove region in the array substrate, and schematically illustrates the gate line 71 and the data line 61, and fig. 3 illustrates only the light emitting element 300, the first transistor 110, and the second transistor 120 in the pixel unit. For example, the first transistor 110 is a switching transistor, mainly functioning as a switch, controlling transmission of a data signal under control of the gate line 71; the second transistor 120 is a driving transistor, mainly functioning as a driving transistor, and supplies a driving current to a pixel electrode which is a cathode or an anode of the light emitting element.
It should be noted that the embodiments of the present disclosure are not limited to the specific connection manner between the first transistor and the second transistor and the light emitting element.
Referring to fig. 2 and 3, the array substrate 200 includes a substrate 211, and a first insulating layer 212, a second insulating layer 214, and a first conductive pattern layer 213 sequentially stacked on the substrate 211. The first insulating layer 212 is provided with a groove 220, the groove 220 is disposed in the pixel display area 210, and the second insulating layer 214 is also filled into the groove 220; for example, further, the second insulating layer 214 may have a flat surface, which serves as planarization.
For example, the second insulating layer 214 is an organic insulating layer. The organic insulating material has better flexibility than the inorganic insulating material, so that the impact resistance and bending resistance of the array substrate 200 can be further improved.
For example, the material of the second insulating layer 214 is at least one of polymethyl methacrylate, polycarbonate, polystyrene, epoxy, polyimide, and polyethylene.
For example, the first insulating layer 212 may be an organic insulating material such as a resin material of polyimide or the like; but also inorganic insulating materials such as silicon oxides, silicon nitrides or silicon oxynitrides or metal oxide insulating materials.
For example, the material of the first conductive pattern layer 213 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and an alloy material formed by combining the above metals; or a conductive metal oxide material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), or the like.
For example, the recess 220 can be disposed in any of the first insulating layer 212 where no via is disposed. The embodiment of the present disclosure does not limit the disposition area of the recess 220, that is, does not affect the formation of the device structure. For example, in at least one embodiment, the recess 220 may extend downward until the substrate 211 is exposed, i.e., the surface of the substrate 211 is exposed through the recess 220.
For example, the present disclosure is not limited to the planar shape of the recess 200 in a direction parallel to the substrate 211, including circular, triangular, rectangular, elliptical, T-shaped, stripe-shaped, folded-line-shaped, or other shapes defined by the peripheral device structures. For example, the length direction of the groove 220 is parallel to a bending axis (not shown) of the array substrate 200, so that the bending resistance of the array substrate 200 may be improved when the array substrate 200 is bent along the bending axis.
In at least one embodiment, for example, as shown in fig. 2, at least a portion of the recess 220 is distributed around the second transistor 120 with respect to the plane of the substrate base plate. For example, the grooves 220 are distributed around the second gate 121 of the second transistor 120, i.e. at least part of the grooves 220 are distributed around the second gate 121. For example, the grooves 220 are disposed on at least two sides of the second gate electrode 121, for example, on the substrate, and the extending direction of the grooves 220 and the extending direction of the second gate electrode 121 are parallel to each other. In this embodiment, the second transistor 120 is used as a driving transistor of the pixel unit, generally, the driving transistor occupies a larger area in the pixel unit, and the performance of the driving transistor has a more important effect on the display effect than the switching transistor, so it is also important to keep the performance stable, and the above arrangement can effectively protect the second transistor 120 from being damaged under the action of external force or bending. For example, as shown in fig. 2, at least a portion of the recess 220 may also be disposed between the first transistor 110 and the second transistor 120, e.g., between the first active layer 112 of the first transistor 110 and the second active layer 122 of the second transistor 120, relative to the plane of the substrate; or the recess 220 is provided between the first gate 111 of the first transistor 110 and the second gate 121 of the second transistor 120.
For example, the first conductive pattern layer 213 includes a gate line 71 or a portion of the gate line 71 for displaying the pixel region 210. The gate line 71 is disposed at a side of the second insulating layer 214 away from the substrate base 211, so that the disposition of the groove 220 is not limited by the gate line 71, whereby the disposition position of the groove 220 can be more flexible and the disposition area can be larger.
The first insulating layer 212 and the second insulating layer 214 are sequentially stacked between the substrate 211 and the first conductive layer 213, and may be laid out according to a specific array substrate structure, and are not limited to a specific insulating layer structure.
For example, the second insulating layer 214 is an organic insulating layer closest to the substrate base 211. In the case where the grooves 220 expose the substrate 211, such an arrangement may make the insulating material at a position corresponding to the grooves 220 in a direction perpendicular to the substrate 211 be an organic insulating material, and thus may better improve impact resistance and bending resistance of the array substrate 200.
For example, the groove 220 includes a first portion 221, and the first portion 221 is parallel to the gate line 71 (fig. 2) or overlaps the gate line 71 in a direction perpendicular to the substrate 211. For example, the length direction of the first portion 221 is parallel to the extending direction of the gate line. It should be noted that, the pattern in the present disclosure is not limited to extend along a straight line, but may extend along a curved line, such as a serpentine shape.
For example, the gate layer 250 includes the first gate 111 of the first transistor 110.
For example, the gate layer 250 also includes a second gate 121 of the second transistor 120.
For example, the semiconductor layer 240 is located at a side of the gate layer 250 close to the substrate 211, including the first active layer 112 of the first transistor 110 and the second active layer 122 of the second transistor 120.
For example, as shown in fig. 2, the recess 220 further includes a third portion 223, the third portion 223 being disposed parallel to and corresponding to the second gate electrode 121 of the second transistor, and the length of the third portion 223 being greater than the length of the second gate electrode 121 in the length direction (i.e., the first direction D1) of the third recess 223, thereby forming effective protection for the second transistor 120 as a pixel driving transistor. For example, since the region covered by the gate electrode in the semiconductor layer 240 generally serves as a channel region of the transistor, the third portion 223 of the groove is set to have a length in the first direction D1 greater than that of the second gate electrode 121, that is, greater than that of the channel region of the second transistor 120, so that the channel region can be effectively protected.
For example, different portions of the groove 220 may have different depths, and may be flexibly designed according to the actual available space, which is not limited by the disclosed embodiments.
In some examples, for example, the groove 220 may form a letter-like shape around the second gate electrode 121. Due to the presence of the semiconductor layer 240, the depth of the groove 220 may be shallower at a position overlapping with the semiconductor layer 240 (with respect to the substrate), for example, the groove 220 penetrates to the surface of the semiconductor layer 240 in the longitudinal direction, so that damage to the semiconductor layer 240 may be avoided.
The above description of the recesses is mainly given by way of example of the second transistors, and each transistor in each pixel may be similarly provided where space in the substrate allows, for example, the recesses are correspondingly provided around the gate of each transistor.
For example, the gate layer 250 is on a side of the second insulating layer 214 near the substrate 211.
For example, the first gate 111 of the first transistor 110 is electrically connected to the gate line 71 through the first via 241 in the second insulating layer 214.
For example, in a direction perpendicular to the substrate base plate (see direction D in fig. 3), the gate layer 250 may also be located between the first insulating layer 212 and the second insulating layer 214, e.g., the first insulating layer 212 serves as a gate insulating layer for the first transistor 110 and the second transistor 120. Embodiments of the present disclosure are not limited in this regard.
For example, the material of the gate layer 250 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and an alloy material combining the above metals; or a conductive metal oxide material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), or the like.
For example, the material of the semiconductor layer 240 includes, but is not limited to, silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, znO, AZO, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.).
In some embodiments of the present disclosure, the first transistor 110 and the second transistor 120 are both top gate structures, and in other embodiments, the first transistor 110 and the second transistor 120 may also be bottom gate structures. For example, the first transistor 110 is a top gate structure, and the second transistor 120 is a bottom gate structure. The transistor with the top gate structure has smaller parasitic capacitance so as to have faster starting speed; the transistor with the bottom gate structure has larger on-state current and electrical stability, thereby having stronger driving capability. For example, the first transistor 110 and the second transistor 120 are thin film transistors. The embodiments of the present disclosure are not limited with respect to the specific structure and type of the first transistor 110 and the second transistor 120.
For example, the first transistor 110 includes a first source 113 and a first drain 114. For example, the first source 113 or the first drain 114 is electrically connected to the second gate 121 of the second transistor 120.
For example, the first source electrode 113, the first drain electrode 114 are disposed in the same layer and of the same material as the data line 61, and thus may be obtained through the same patterning process. For example, the first source electrode 113 or the first drain electrode 114 is electrically connected to the data line 61 to receive a data signal for emitting light. For example, an electrode of the first source electrode 113 and the first drain electrode 114, which is not electrically connected to the second gate electrode 121 of the second transistor 120, is electrically connected to the data line 61.
For example, the groove 220 may further include a second portion 222, and the second portion 222 is parallel to the data line 61 or overlaps the data line in a direction perpendicular to the substrate base 211. For example, the length direction of the second portion 222 is parallel to the extending direction of the data line 61 (fig. 2).
For example, the array substrate 200 further includes a gate connection electrode 72, the gate connection electrode 72 being located between the gate electrode layer 250 and the first conductive pattern layer 213 for connecting the first gate electrode 111 and the gate line 71. The via hole depth is too large, so that the conductive material filled in the via hole is easy to wrinkle or break (especially in a bending state) to cause overlarge contact resistance or poor contact, and the arrangement of the gate connecting electrode to connect the first gate 111 and the gate line 71 can avoid the too deep depth of the continuous via hole directly connecting the first gate 111 and the gate line 71, thereby being beneficial to improving the yield and bending resistance of the array substrate.
For example, the gate connection electrode 72 may be provided in the same layer and material as any one of the conductive layers between the gate electrode layer 250 and the first conductive pattern layer 213, and thus may be obtained through the same patterning process.
For example, the gate connection electrode 72 is located between the second insulating layer 214 and the first conductive pattern layer 213; for example, the array substrate further includes a third insulating layer 216 disposed between the gate connection electrode 72 and the first conductive pattern layer 213. For example, the gate connection electrode 72 is electrically connected to the first gate electrode 111 through the first via hole 241 in the second insulating layer 214 and to the gate line 71 through the second via hole 261 in the third insulating layer 216, thereby electrically connecting the gate line 71 to the first gate electrode 111.
For example, the gate connection electrode 72 is provided in the same layer and material as the first source electrode 113 and the first drain electrode 114 of the first transistor 110, and thus may be obtained through the same patterning process. For example, in a direction perpendicular to the substrate base plate, the third insulating layer 216 is located between the second source electrode 123 and the second drain electrode 124 and the first conductive pattern layer 213.
For example, the second transistor 120 further includes a second source 123 and a second drain 124. For example, the second source electrode 123 and the second drain electrode 124 are located between the second insulating layer 214 and the first conductive pattern layer 213. For example, the second source electrode 123 and the second drain electrode 124 are disposed in the same layer and of the same material as the first source electrode 113 and the first drain electrode 114, and thus may be obtained through the same patterning process.
For example, the light emitting element 300 includes a first electrode 301, a light emitting layer 302, and a second electrode 303. Here, the first electrode 301 is a pixel electrode, and the second electrode 303 is a common electrode. One of the first electrode 301 and the second electrode 303 is an anode, and the other is a cathode. For example, in at least one example, the light emitting element 300 may include at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like in addition to the light emitting layer 302.
For example, the second source 123 or the second drain 124 of the second transistor 120 is electrically connected to the first electrode 301 (pixel electrode) of the light emitting element 300.
For example, the light emitting element 300 is located at a side of the first conductive pattern layer 213 away from the substrate 211. For example, the array substrate 200 further includes a fourth insulating layer 218 on the first conductive pattern layer 213, the light emitting element 300 is formed on the fourth insulating layer 218, and the second source electrode 123 or the second drain electrode 124 of the second transistor 120 is electrically connected to the first electrode 301 of the light emitting element 300 through a third via hole 281 in the fourth insulating layer 218.
For example, the array substrate 200 further includes a driving connection electrode 230, where the driving connection electrode 230 is located between the second source 123 (or the second drain 124) of the second transistor 120 and the pixel electrode of the light emitting element 300, and connects the second source 123 (or the second drain 124) of the second transistor 120 and the pixel electrode of the light emitting element 300. The driving connection electrode 230 may increase the pixel distribution density of the array substrate 200 and reduce the resistance between the second transistor 120 and the pixel electrode, in addition to having the effect of reducing the via depth similar to the gate connection electrode 72.
For example, as shown in fig. 3, the driving connection electrode 230 overlaps the groove 220 in a direction perpendicular to the substrate base 221.
For example, as shown in fig. 2, the driving connection electrode 230 is disposed in the same layer and made of the same material as the gate line 71, and thus can be obtained through the same patterning process, i.e., the first conductive pattern layer 213 further includes the driving connection electrode 230. The driving connection electrode 230 is electrically connected to the second source electrode 123 or the second drain electrode 124 of the second transistor 120 through the fourth via hole 264 in the third insulating layer 216, and is electrically connected to the first electrode 301 of the light emitting element 300 through the third via hole 281.
For example, the light emitting element 300 may be a top emission, bottom emission, or double-sided emission structure. For example, the light emitting element 300 is a top emission structure, the first electrode 301 has reflectivity and the second electrode 303 has transmissivity or semi-transmissivity, and for example, the first electrode 301 is a transparent conductive oxide material such as Indium Tin Oxide (ITO). For example, the first electrode 301 is a high work function material to function as an anode, such as an ITO/Ag/ITO stack structure; the second electrode 303 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag/Mg alloy material.
For example, the third insulating layer 216 and the fourth insulating layer 218 are planarizing layers. For example, the third insulating layer 216 and the fourth insulating layer 218 are each made of an organic material, for example, a resin such as Polyimide (PI).
For example, the array substrate 200 further includes a storage capacitor Cst, for example, for storing a data signal during operation of the pixel circuit. The arrangement mode and the connection mode of the storage capacitor can be adjusted according to a specific pixel circuit structure. For example, as shown in fig. 3, in a direction perpendicular to the substrate base plate, a first capacitor electrode 411 of the storage capacitor is disposed between the first insulating layer 212 and the second insulating layer 214; the second capacitor electrode 412 is disposed in the same layer and made of the same material as the first gate electrode 111 of the first transistor 110, and thus can be obtained by the same patterning process, and the first capacitor electrode 411 and the second capacitor electrode 412 are disposed opposite to each other to form the storage capacitor Cst.
For example, at least a portion of the recess 220 is disposed between the second transistor 120 and the storage capacitor Cst with respect to a plane in which the substrate is disposed.
For example, the array substrate 200 further includes a pixel defining layer 215 disposed on the first electrode 301 of the light emitting element 300 for isolating the light emitting layers of adjacent light emitting elements, thereby preventing cross color during a display operation. The pixel defining layer 215 forms an opening at a position corresponding to the first electrode 301 to at least partially expose the first electrode 301, and a light emitting layer 302 is formed in the opening. A second electrode 303 is formed on the light emitting layer 302 and the pixel defining layer. For example, the pixel defining layer 215 is an organic material such as a resin or an inorganic material such as silicon oxide.
For example, the array substrate 200 further includes a spacer layer 217 disposed on the pixel defining layer 215. For example, the spacer layer 217 is used to support the vapor deposition mask plate when the organic light emitting layer 302 is formed by vapor deposition, so as to isolate the pixel defining layer 215 from the vapor deposition mask plate to form protection for the pixel defining layer 215; the spacer layer 217 may also function to further isolate adjacent organic light emitting layers. The Spacer layer 217 generally includes a plurality of spacers (spacers) spaced apart, and the shape of the spacers is generally rectangular parallelepiped, columnar, spherical, hemispherical, or not limited thereto.
For example, the array substrate 200 further includes a protective layer 219 disposed on the second electrode 303. The protective layer 219 is, for example, an inorganic protective layer or an organic protective layer, or a laminate of an inorganic protective layer and an organic protective layer. In addition, a reducing material and/or a hygroscopic material may be included in the protective layer 219 to avoid adverse effects of oxygen/moisture on the light emitting element 300.
For example, the array substrate 200 further includes a gate insulating layer 207 disposed between the gate layer 250 and the semiconductor layer 240.
For example, the material of the gate insulating layer 207 is silicon oxide, silicon nitride, or silicon oxynitride.
For example, in at least one embodiment, the recess 220 also extends through the gate insulation layer 207 to expose the substrate base 211.
For example, the array substrate 200 further includes a buffer layer (not shown) disposed between the substrate 211 and the semiconductor layer 240 in a direction perpendicular to the substrate. The buffer layer serves to make the surface of the substrate 211 smoother and also prevents harmful impurities in the substrate 211 from entering the pixel circuit. For example, the recess 220 may expose the buffer layer without passing through the buffer layer to expose the substrate.
For example, the array substrate 200 is a flexible array substrate. For example, the substrate 211 is an organic flexible material such as Polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, polyethersulfone, or the like.
As shown in fig. 4, some embodiments of the present disclosure further provide a display panel 20, where the display panel 20 includes the above-mentioned array substrate 200. For example, the display panel is an OLED display panel, and accordingly, the array substrate included in the display panel is an OLED array substrate, and the light emitting element included in the pixel unit is an OLED. For example, the display panel further includes an encapsulation layer 501 and a cover plate 502 disposed on the array substrate 200, wherein the encapsulation layer 501 is configured to seal the light emitting element 300 to prevent penetration of external moisture and oxygen into the light emitting element and the pixel circuit to damage the device. For example, the encapsulation layer 501 includes an organic film or a structure in which organic films and inorganic films are alternately stacked. For example, a water-absorbing layer (not shown) may be further disposed between the encapsulation layer 501 and the array substrate 200, and configured to absorb moisture or sol that remains in the light-emitting element 300 during the previous manufacturing process. The cover 502 is, for example, a glass cover. For example, the cover plate 502 and the encapsulation layer 501 may be of unitary construction.
In another example, the display panel 20 is a liquid crystal display panel, and the display panel 20 further includes a color film substrate opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color film substrate.
Some embodiments of the present disclosure further provide a display device including the above array substrate or the display panel. The display device can be, for example, a liquid crystal display device, an OLED display device or electronic paper, a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a notebook computer, a navigator and other products or components with any display function.
Some embodiments of the present disclosure also provide a method of manufacturing an array substrate including a display pixel region for providing pixel units arranged in an array. The manufacturing method comprises the following steps: providing a substrate; forming a first insulating layer on the substrate base plate, and forming a groove on the first insulating layer, wherein the groove is formed in the display pixel area; forming a second insulating layer on the first insulating layer, wherein the second insulating layer is also filled in the groove; and forming a first conductive pattern layer on the second insulating layer.
Fig. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the disclosure. The method for manufacturing the array substrate according to the embodiment of the present disclosure will be exemplarily described with reference to fig. 1, 3 and 5, and the method for manufacturing the array substrate includes at least steps S51 to S53.
Step S51: providing a substrate, forming a first insulating layer on the substrate, and forming a groove on the first insulating layer, wherein the groove is formed in the display pixel area;
Step S52: forming a second insulating layer on the first insulating layer, wherein the second insulating layer is also filled in the groove; and
Step S53: and forming a first conductive pattern layer on the second insulating layer.
In one example of step S51, the substrate 211 is provided first, and then the first insulating layer 212 is formed on the substrate 211 and the groove 220 is formed in the first insulating layer 212. For example, the semiconductor layer 240, the gate insulating layer 207, and the gate layer 250 are sequentially formed on the substrate 211 before the first insulating layer 212 is formed.
For example, the substrate base 211 is an organic flexible material such as Polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, polyethersulfone, or the like.
For example, forming the gate layer includes forming a first conductive layer and patterning the conductive layer to form the gate 111 of the first transistor 110 and the second gate 121 of the second transistor 120.
For example, the material of the first conductive layer is a metal material, such as copper, aluminum, magnesium, molybdenum, chromium, an alloy of the above metals, or the like.
For example, forming the recess 220 includes etching the first insulating layer 212.
For example, the recess 220 does not overlap with the semiconductor layer 240 and the gate layer 250 in a direction perpendicular to the substrate 211.
For example, the recess 220 also penetrates the gate insulating layer 207 to expose the substrate 211.
For example, the first insulating layer 212 may be an organic insulating material such as a resin material of polyimide or the like; but also inorganic insulating materials such as silicon oxides, silicon nitrides or silicon oxynitrides or metal oxide insulating materials.
For example, conventional physical vapor deposition (e.g., forming a conductive layer) such as a sputtering process, chemical vapor deposition (e.g., forming an insulating layer), spin-on (e.g., forming an organic layer), photolithography (e.g., performing a patterning process), etc., may be employed in the forming process.
In one example of step S52, the material of the second insulating layer 212 is an organic insulating material, such as at least one of polymethyl methacrylate, polycarbonate, polystyrene, epoxy, polyimide, and polyethylene. For example, the formation method of the second insulating layer 212 includes spin coating or inkjet printing. For example, the method of forming the second insulating layer 212 further includes curing.
The organic insulating material has better flexibility than the inorganic insulating material, so that the impact resistance and bending resistance of the array substrate 200 can be further improved.
For example, step S52 further includes etching the second insulating layer 214 to form the first via 241 and source-drain contact holes of the first transistor 110 and the second transistor 120. The first via 241 also penetrates the first insulating layer 212 to expose at least a portion of the gate layer 250. The source/drain contact holes also penetrate through the first insulating layer 212 and the gate insulating layer 207 to expose at least a portion of the semiconductor layer 240, respectively.
In one example of step S53, the step further includes sequentially forming a second conductive layer and a third insulating layer 216 on the second insulating layer 214 before forming the first conductive pattern layer 213. For example, a patterning process is performed on the second conductive layer to form a first source 113 and a first drain 114 of the first transistor 110, and a second source 123 and a second drain 124 of the second transistor 120. For example, patterning the second conductive layer also forms a gate connection electrode 72 and a data line 61, the gate connection electrode 72 being electrically connected to the first gate electrode 111 through the first via 241. The first source electrode 113 and the first drain electrode 114 of the first transistor 110 are respectively contacted with the first active layer 112 through source-drain contact holes to form electrical connection, and the second source electrode 123 and the second drain electrode 124 of the second transistor 120 are respectively contacted with the second active layer 122 through source-drain contact holes to form electrical connection.
For example, step S53 further includes performing a patterning process on the third insulating layer 216 to form the second via 261 and the fourth via 262. The second via 261 exposes at least a portion of the gate connection electrode 72; the fourth via 262 exposes at least a portion of the second source 123 or the second drain 124 of the second transistor 120.
For example, forming the first conductive pattern layer 213 includes forming a third conductive layer and patterning the third conductive layer to form the gate line 71 and the driving connection electrode 230. The gate line 71 is electrically connected to the gate connection electrode 72 through the second via 261. The driving connection electrode 230 is electrically connected to the second source 123 or the second drain 124 of the second transistor 120 through the fourth via 262.
For example, the method for manufacturing an array substrate further includes forming a light emitting element 300 on the first conductive pattern layer 213, and forming the light emitting element 300 includes sequentially forming a first electrode 301, a light emitting layer 302, and a second electrode 303, where the first electrode 301 is electrically connected to the driving connection electrode 230.
For example, the method further includes forming a fourth insulating layer 218, a pixel defining layer 215, a spacer layer 217, and a protective layer 219. And will not be described in detail herein.
For example, the material of the conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and an alloy material formed by combining the above metals; or a conductive metal oxide material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), or the like.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (18)

1. An array substrate, includes display pixel district, display pixel district is used for providing the pixel unit of array arrangement, the pixel unit includes first transistor, first transistor includes first grid, array substrate still includes:
A substrate base plate is provided with a plurality of base plates,
The first insulating layer is arranged on the substrate base plate, a groove is formed in the first insulating layer, and the groove is arranged in the display pixel area;
the second insulating layer is arranged on the first insulating layer, and the second insulating layer is also filled in the groove;
A first conductive pattern layer disposed on the second insulating layer, the first conductive pattern layer including a gate line for the display pixel region;
the first grid electrode is positioned on one side, close to the substrate, of the second insulating layer, and is electrically connected with the grid line through a first via hole in the second insulating layer.
2. The array substrate of claim 1, wherein the second insulating layer is an organic insulating layer.
3. The array substrate of claim 1, wherein the recess exposes the substrate.
4. The array substrate of claim 1, the groove comprising a first portion, wherein the first portion of the groove is parallel to or overlaps with the gate line in a direction perpendicular to the substrate.
5. The array substrate of claim 1,
The array substrate further comprises a gate connection electrode, wherein the gate connection electrode is located between the second insulating layer and the first conductive pattern layer, and the first gate is electrically connected with the gate line through the gate connection electrode.
6. The array substrate of claim 5, wherein the first transistor further comprises a first source electrode and a first drain electrode, the array substrate further comprises a data line for the display pixel region,
The first source electrode, the first drain electrode and the data line are arranged on the same layer as the gate connection electrode and are made of the same material.
7. The array substrate of claim 6,
The groove further includes a second portion parallel to the data line or overlapping the data line in a direction perpendicular to the substrate base plate.
8. The array substrate of claim 7, wherein the pixel unit further comprises a second transistor,
The second transistor includes a second gate connected to the first source or the first drain of the first transistor.
9. The array substrate of claim 8, wherein the grooves are distributed around the second gate electrode.
10. The array substrate of claim 8, wherein the groove further comprises a third portion, the third portion being parallel to and disposed corresponding to the second gate electrode;
The length of the third portion is greater than the length of the second gate in the length direction of the third portion.
11. The array substrate of claim 8, the second transistor comprising a second source and a second drain, the array substrate further comprising a third insulating layer;
Wherein the second source electrode and the second drain electrode are located between the second insulating layer and the first conductive pattern layer in a direction perpendicular to the substrate base plate; the third insulating layer is located between the second source and drain electrodes and the first conductive pattern layer in a direction perpendicular to the substrate base plate.
12. The array substrate of claim 11, further comprising a fourth insulating layer and a pixel electrode stacked over the first conductive pattern layer,
And the second source electrode or the second drain electrode is electrically connected with the pixel electrode through a second via hole in the fourth insulating layer.
13. The array substrate of claim 12, wherein the first conductive pattern layer further comprises a driving connection electrode,
The second source electrode or the second drain electrode is connected with the pixel electrode through the driving connection electrode.
14. The array substrate of any one of claims 5-13, further comprising a first capacitive electrode, wherein the first capacitive electrode is disposed between the first insulating layer and the second insulating layer in a direction perpendicular to the substrate.
15. The array substrate of claim 14, further comprising a second capacitive electrode, wherein the second capacitive electrode is disposed on the same layer as the first gate electrode and forms a capacitance opposite the first capacitive electrode.
16. A display panel comprising an array substrate according to any one of claims 1-15.
17. The manufacturing method of the array substrate comprises a display pixel area for providing pixel units arranged in an array, wherein the pixel units comprise a first transistor, the first transistor comprises a first grid,
The manufacturing method comprises the following steps:
a substrate base plate is provided,
Forming a first insulating layer on the substrate base plate, and forming a groove on the first insulating layer, wherein the groove is formed in the display pixel area;
Forming a second insulating layer on the first insulating layer, wherein the second insulating layer is also filled in the groove;
Forming a first conductive pattern layer on the second insulating layer, the first conductive pattern layer including a gate line for the display pixel region;
the first grid electrode is positioned on one side, close to the substrate base plate, of the second insulating layer, and is electrically connected with the grid line through a first via hole in the second insulating layer.
18. The method of manufacturing of claim 17, wherein the first insulating layer is an organic insulating layer.
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