CN111680000B - Configuration system and method of field programmable gate array - Google Patents
Configuration system and method of field programmable gate array Download PDFInfo
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- CN111680000B CN111680000B CN202010376678.5A CN202010376678A CN111680000B CN 111680000 B CN111680000 B CN 111680000B CN 202010376678 A CN202010376678 A CN 202010376678A CN 111680000 B CN111680000 B CN 111680000B
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- G06F15/76—Architectures of general purpose stored program computers
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- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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Abstract
The application relates to the technical field of field programmable gate arrays, in particular to a configuration system and a configuration method of a field programmable gate array, wherein the system comprises the following components: NAND memory and FPGA; the NAND memory includes: the data array, join in marriage a yard array, first configuration interface and NAND controller, the FPGA includes: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller. The application stores the code matching file and the access data in the NAND memory together, realizes the configuration and storage integration of the FPGA, only needs one external memory for the whole system, saves the circuit cost of the independent FPGA configuration memory, saves the board-level area and reduces the board-level development difficulty. Meanwhile, the large capacity characteristic of the NAND memory can store a plurality of configuration versions for the FPGA, so that the flexibility of the configuration of the FPGA is improved.
Description
Technical Field
The application relates to the technical field of field programmable gate arrays, in particular to a configuration system and a configuration method of a field programmable gate array.
Background
As a flexible configurable device, a Field Programmable Gate Array (FPGA) is increasingly used in fields such as video image processing, communication, digital signal processing, etc. with the development of information industry and microelectronics, and the FPGA is required to have multiple functions and a higher data processing capability.
The traditional FPGA system needs to be connected with a configuration memory and a data memory for cooperation. The structure of the configuration memory is shown in fig. 1, and the configuration memory generally adopts a NOR memory for storing the configuration code of the FPGA, and the configuration code is transmitted to the FPGA after power-on, so that power-on configuration is completed. The data memory generally adopts a NAND memory for storing the FPGA access data.
However, the above prior art has the following technical drawbacks:
in the above conventional scheme, two memory chips are required to be arranged in board-level layout, which increases board-level area overhead and design complexity. And the capacity of the NOR memory is smaller and is in the range of tens to hundreds of megabits, and the NOR memory matched with the FPGA is generally only capable of storing one version of matching code.
Disclosure of Invention
The application aims to provide a configuration system and a configuration method of a field programmable gate array, which are used for solving the technical problem that an FPGA code matching file is required to be stored through a NOR memory in the prior art.
The embodiment of the application provides the following scheme:
according to a first aspect of the present application, an embodiment of the present application provides a configuration system of a field programmable gate array, including: NAND memory and FPGA;
the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller;
the code matching array is used for storing code matching files of a plurality of versions;
the first configuration interface is used for reading a first configuration code from the configuration code array after power-on, and sending the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration;
the data array is used for storing the access data of the FPGA;
the FPGA is used for sending a data read-write instruction to the NAND controller through the NAND interface;
and the NAND controller is used for performing read-write operation on the data array according to the data read-write instruction.
Preferably, the NAND memory further includes: a version switching module;
the FPGA is used for sending a version switching instruction to the NAND controller through the NAND interface;
the NAND controller is further used for sending the version switching instruction to the version switching module;
the version switching module is used for extracting version information of the second configuration code from the version switching instruction and changing the configuration code address accessed in the first configuration interface according to the version information;
the first configuration interface is further configured to read the second configuration code from the configuration code array according to the configuration code address, and send the second configuration code to the second configuration interface, so that the FPGA configures the second configuration code.
Preferably, the code matching array is further used for storing backup code matching of the code matching file;
the version switching module is further configured to detect whether the first configuration interface receives a configuration success signal returned by the second configuration interface; if the first configuration interface does not receive the configuration success signal, a secondary configuration instruction is sent to the first configuration interface;
the first configuration interface is further configured to read the backup configuration code of the first configuration code from the configuration code array according to the secondary configuration instruction, and send the backup configuration code of the first configuration code to the second configuration interface, so that the FPGA performs secondary configuration.
Preferably, the code matching array is further used for storing redundant code matching of the code matching file; the NAND memory further includes:
and the code allocation protection module is used for carrying out error checking and ECC (error correction) correction on the code allocation file and controlling the redundant code allocation.
Preferably, the NAND memory further includes:
and the first JTAG interface is used for burning the code matching files of the multiple versions into the code matching array.
Preferably, the FPGA further includes:
the second JTAG interface is used for carrying out initial configuration on the FPGA;
the FPGA is also used for accessing an external memory through the NAND interface and programming the code matching file in the external memory into the code matching array.
According to a second aspect of the present application, there is provided a method of configuring a field programmable gate array, a configuration system based on the field programmable gate array, the system comprising: NAND memory and FPGA; the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: a second configuration interface and a NAND interface; the method comprises the following steps:
after the NAND memory is electrified, a first configuration code is read from the configuration code array through the first configuration interface, and the first configuration code is sent to the second configuration interface of the FPGA so that the FPGA can be configured, and a plurality of versions of configuration code files are stored in the configuration code array;
the FPGA sends a data read-write instruction to the NAND controller through the NAND interface;
and the NAND controller performs read-write operation on the data array according to the data read-write instruction, and the data array stores the access data of the FPGA.
Preferably, the method further comprises:
the FPGA sends a version switching instruction to a version switching module of the NAND memory through the NAND interface;
the version switching module extracts version information of a second configuration code from the version switching instruction, and changes a configuration code address accessed in the first configuration interface according to the version information;
the first configuration interface reads the second configuration code from the configuration code array according to the configuration code address, and sends the second configuration code to the second configuration interface so that the FPGA can be configured.
Preferably, after the sending the second configuration code to the second configuration interface, the method further includes:
and if the version switching module does not receive a configuration success signal returned by the FPGA, reading the backup configuration code of the first configuration code from the configuration code array through the first configuration interface, and sending the backup configuration code of the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration, wherein the backup configuration code of the configuration code file is stored in the configuration code array.
Preferably, the method further comprises:
and the code allocation protection module of the NAND memory performs error checking and correction ECC checking on the code allocation file and controls redundant code allocation of the code allocation file, and the redundant code allocation of the code allocation file is stored in the code allocation array.
Compared with the prior art, the application has the following advantages and beneficial effects:
the configuration system of the field programmable gate array of the application comprises: NAND memory and FPGA; the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller; the code matching array is used for storing code matching files of a plurality of versions; the first configuration interface is used for reading a first configuration code from the configuration code array after power-on, and sending the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration; the FPGA is used for sending access data to the NAND controller through the NAND interface; the NAND controller is used for transmitting the access data to the data array; and the data array is used for storing the access data of the FPGA. According to the application, the code matching file and the access data are stored in the NAND memory, so that the configuration and storage integration of the FPGA is realized, a NOR memory in the prior art is eliminated, only one external memory is needed in the whole system, the circuit overhead of the independent FPGA configuration memory is saved, the board-level area is saved, and the board-level development difficulty is reduced. Meanwhile, the large capacity characteristic of the NAND memory can store a plurality of configuration versions for the FPGA, so that the flexibility of the configuration of the FPGA is improved.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present description, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art field programmable gate array system;
FIG. 2 is a schematic diagram of a configuration system of a field programmable gate array according to an embodiment of the present application;
fig. 3 is a flowchart illustrating a configuration method of a field programmable gate array according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present application are within the scope of protection of the embodiments of the present application.
First embodiment
Referring to fig. 2, fig. 2 is a schematic diagram of a configuration system of a field programmable gate array according to an embodiment of the application.
In this embodiment, the configuration system of the field programmable gate array includes: NAND memory and FPGA.
The NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller.
The code matching array is used for storing code matching files of multiple versions.
The first configuration interface is configured to read a first configuration code from the configuration code array after power is on, and send the first configuration code to the second configuration interface, so that the FPGA configures the FPGA.
In the embodiment, the configuration memory is canceled, the FPGA configuration control circuit is added in the NAND memory control circuit, and the configuration code file and the access data are stored in the NAND memory together, so that the NAND memory has the functions of FPGA configuration and data storage, and the whole system only needs one external memory, thereby saving the circuit cost of the independent FPGA configuration memory, conforming to the current application scene, saving the board-level area and reducing the board-level development difficulty. Moreover, the present embodiment is easy to implement, and the iterations can be updated. Some NAND controllers are currently implemented by FPGA or a combination of hardware and software. Based on the flexible and iterative nature of the NAND controller, the FPGA configuration functional logic is embedded in the NAND controller, so that the implementation is easy.
Specifically, the NAND memory includes: the system comprises a data array and a code matching array, wherein the code matching array is used for storing code matching files of multiple versions, and the data array is used for storing access data of the FPGA.
After the NAND memory is electrified, the first configuration interface reads a first configuration code from the configuration code array, the first configuration code is a configuration code file of a default version, and the first configuration code is sent to a second configuration interface of the FPGA so that the FPGA can be configured according to the first configuration code.
The data array is used for storing the access data of the FPGA; the FPGA is used for sending a data read-write instruction to the NAND controller through the NAND interface; and the NAND controller is used for performing read-write operation on the data array according to the data read-write instruction.
After the configuration is completed, the FPGA will perform a job, and store access data generated during the job in the data array, and also read out data stored in the data array, specifically: the FPGA sends a data read-write instruction to the NAND controller through the NAND interface; the NAND controller receives the data read-write instruction, and when the data read-write instruction is a data write instruction, the data carried by the data write instruction is written into the data array; when the data reading and writing instruction is a data reading instruction, corresponding data is read from the data array and transmitted to the FPGA, so that the configuration and storage integration of the FPGA is realized, and the performance of an FPGA system is improved.
In one possible implementation, the NAND memory further includes: and a version switching module. The FPGA is used for sending a version switching instruction to the NAND controller through the NAND interface; the NAND controller is further used for sending the version switching instruction to the version switching module; the version switching module is used for extracting version information of the second configuration code from the version switching instruction and changing the configuration code address accessed in the first configuration interface according to the version information; the first configuration interface is further configured to read the second configuration code from the configuration code array according to the configuration code address, and send the second configuration code to the second configuration interface, so that the FPGA configures the second configuration code.
In the traditional scheme, the capacity of a NOR memory matched with an FPGA is generally only enough to store one version of configuration code, the configuration memory only supports the FPGA configuration function, and the switching function of a plurality of configuration codes of the FPGA cannot be realized, so that the flexibility of the FPGA is lower. In order to improve the flexibility of the FPGA, a version switching module is arranged in the NAND memory, and the functions of the FPGA are updated by combining a plurality of versions of code matching files stored in the code matching array. When the function of the FPGA needs to be updated, namely, when the code matching version of the FPGA needs to be updated, the FPGA sends a version switching instruction to the version switching module through the NAND interface, so that when the version switching module receives the version switching instruction, the version information of a second code matching is extracted from the version switching instruction, and the code matching address accessed in the first configuration interface is modified into the address in the version information; the second configuration code is a configuration code required by the FPGA to update, the second configuration code is different from the first configuration code in version, and the version information comprises the version name of the second configuration code and the configuration code address of the second configuration code. The first configuration interface reads the second configuration code from the configuration code array according to the configuration code address, and sends the second configuration code to the second configuration interface so as to enable the FPGA to configure, thereby realizing the switching of the configuration code of the FPGA from the first configuration code to the second configuration code.
In a possible implementation manner, the code allocation array is further used for storing backup codes or redundant codes of the code allocation file; the version switching module is further configured to detect whether the first configuration interface receives a configuration success signal returned by the second configuration interface; if the first configuration interface does not receive the configuration success signal, a secondary configuration instruction is sent to the first configuration interface; the first configuration interface is further configured to read the backup configuration code or the redundant configuration code of the first configuration code from the configuration code array according to the secondary configuration instruction, and send the backup configuration code or the redundant configuration code of the first configuration code to the second configuration interface, so that the FPGA performs secondary configuration.
Considering that the FPGA may have an unsuccessful power-on configuration, the version switching module further has a function of repeating the power-on configuration, specifically: after a first configuration code is sent to the second configuration interface, if the configuration of the FPGA is successful, the FPGA returns a configuration success signal to the first configuration interface through the second configuration interface; if the FPGA configuration fails, the FPGA does not return a configuration success signal to the first configuration interface. After the first configuration interface sends the first configuration code to the second configuration interface, the version switching module waits for a preset time to detect whether the first configuration interface receives the configuration success signal, and if the first configuration interface does not receive the configuration success signal, a secondary configuration instruction is sent to the first configuration interface. And after receiving the secondary configuration instruction, the first configuration interface reads the backup configuration code or the redundant configuration code of the first configuration code from the configuration code array according to the secondary configuration instruction, and sends the backup configuration code or the redundant configuration code of the first configuration code to the second configuration interface so as to enable the FPGA to perform secondary configuration.
Of course, after the backup configuration code of the first configuration code is sent to the second configuration interface, if the configuration success signal returned by the FPGA is still not received within the preset time, the version switching module considers that the configuration fails, and sends a configuration instruction to the first configuration interface three times, so that the first configuration interface reads a third configuration code from the configuration code array, the third configuration code is different from the version of the first configuration code, and sends the third configuration code to the second configuration interface, so that the FPGA configures according to the third configuration code. And by analogy, each code matching file or backup code matching in the code matching array is read in sequence until the version switching module receives a successful configuration signal returned by the FPGA or traverses all code matching files, so that the problem that the FPGA is unsuccessful in power-on configuration is solved, and the reliability of the FPGA is improved.
In one possible implementation, the NAND memory further includes: and the code allocation protection module is used for carrying out error checking and correction (Error Correcting Code, ECC) check on the code allocation file and controlling the redundant code allocation. In the traditional scheme, the configuration memory has limited functions in terms of data protection and data recovery, the configuration code is very important data of the FPGA, the function failure of the FPGA is directly caused once the data is in error, and the NAND memory is easy to generate bad blocks compared with the NOR memory, so that in order to improve the reliability of the configuration code, the NAND controller is provided with management strategies such as bad block management, garbage collection and the like of the controller, and the NAND memory is also provided with the configuration code protection module for realizing Error Checking and Correction (ECC) check or redundant configuration code control on the configuration code file.
For example, the code matching array includes: three storage units are used for storing the code matching files of the versions, namely each code matching file has the same three files; the code matching protection module is specifically configured to perform triple modular redundancy processing on the code matching files in the three storage units. The voting circuit is a circuit processing mechanism, the basic idea is that three modules execute the same operation at the same time, a plurality of the same outputs are used as the correct outputs of the voting system, which is commonly called as three-out-two, and the three modules can mask the errors of the fault module as long as two identical errors do not occur at the same time, thereby ensuring the correct outputs of the system. In this embodiment, the first configuration codes are read from the three storage units at the same time, the voting circuit votes the first configuration codes from the three storage units, the result of three-module redundancy arbitration is used as the target configuration code, and the target configuration code is sent to the second configuration interface, so that the FPGA configures according to the target configuration code, and when an error occurs in a certain configuration code file, a correct configuration code file can still be obtained, thereby improving the reliability of configuration codes.
In one possible implementation, the NAND memory further includes: the first JTAG interface is used for writing the code matching files of the plurality of versions into the code matching array, and is a first mode for programming the code matching files into the code matching array.
In one possible implementation manner, the FPGA further includes: the second JTAG interface is used for carrying out initial configuration on the FPGA and loading an initial version for the FPGA; the FPGA is further used for accessing an external memory through the NAND interface after the initial configuration is completed, and programming the code matching file in the external memory into the code matching array, which is a second mode of programming the code matching file into the code matching array.
The technical scheme provided by the embodiment of the application has at least the following technical effects or advantages:
the configuration system of the field programmable gate array of the present embodiment includes: NAND memory and FPGA; the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller; the code matching array is used for storing code matching files of a plurality of versions; the first configuration interface is used for reading a first configuration code from the configuration code array after power-on, and sending the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration; the FPGA is used for sending access data to the NAND controller through the NAND interface; the NAND controller is used for transmitting the access data to the data array; and the data array is used for storing the access data of the FPGA. According to the embodiment, the code matching file and the access data are stored in the NAND memory together, so that the configuration and storage integration of the FPGA is realized, a NOR memory in the prior art is eliminated, only one external memory is needed in the whole system, the circuit cost of the independent FPGA configuration memory is saved, the board-level area is saved, and the board-level development difficulty is reduced. Meanwhile, the large capacity characteristic of the NAND memory can store a plurality of configuration versions for the FPGA, so that the flexibility of the configuration of the FPGA is improved.
Second embodiment
Based on the same inventive concept, as shown in fig. 3, the embodiment of the application further provides a configuration method of a field programmable gate array, the method is based on a configuration system of the field programmable gate array, and the system comprises: NAND memory and FPGA; wherein the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller. The method comprises the following steps:
step S10: after the NAND memory is electrified, a first configuration code is read from the configuration code array through the first configuration interface, and the first configuration code is sent to the second configuration interface of the FPGA so that the FPGA can be configured, and a plurality of versions of configuration code files are stored in the configuration code array.
Step S20: and the FPGA sends a data read-write instruction to the NAND controller through the NAND interface.
Step S30: and the NAND controller performs read-write operation on the data array according to the data read-write instruction, and the data array stores the access data of the FPGA.
In one possible embodiment, the method further comprises:
the FPGA sends a version switching instruction to a version switching module of the NAND memory through the NAND interface;
the version switching module extracts version information of a second configuration code from the version switching instruction, and changes a configuration code address accessed in the first configuration interface according to the version information;
the first configuration interface reads the second configuration code from the configuration code array according to the configuration code address, and sends the second configuration code to the second configuration interface so that the FPGA can be configured.
In a possible implementation manner, after the sending the second configuration code to the second configuration interface, the method further includes:
and if the version switching module does not receive a configuration success signal returned by the FPGA, reading the backup configuration code of the first configuration code from the configuration code array through the first configuration interface, and sending the backup configuration code of the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration, wherein the backup configuration code of the configuration code file is stored in the configuration code array.
In one possible embodiment, the method further comprises:
and the code allocation protection module of the NAND memory performs error checking and correction ECC checking on the code allocation file and controls redundant code allocation of the code allocation file, and the redundant code allocation of the code allocation file is stored in the code allocation array.
In one possible implementation, the NAND memory further includes: a first JTAG interface; before the step S10, the method further includes:
and burning the code matching files of the multiple versions into the code matching array through the first JTAG interface.
In one possible implementation, the FPGA further includes: a second JTAG interface; prior to the step S10, the method further comprises:
initial configuration is carried out on the FPGA through the second JTAG interface;
after initial configuration, the FPGA accesses an external memory through the NAND interface, and writes a code matching file in the external memory into the code matching array.
Compared with the prior art, the embodiment of the application has the following advantages and beneficial effects:
after the NAND memory is powered on, the first configuration code is read from the configuration code array through the first configuration interface, and the first configuration code is sent to the second configuration interface of the FPGA so that the FPGA can be configured, and a plurality of versions of configuration code files are stored in the configuration code array; the FPGA sends a data read-write instruction to the NAND controller through the NAND interface; and the NAND controller performs read-write operation on the data array according to the data read-write instruction, and the data array stores the access data of the FPGA. According to the embodiment, the code matching file and the access data are stored in the NAND memory together, so that the configuration and storage integration of the FPGA is realized, a NOR memory in the prior art is eliminated, only one external memory is needed in the whole system, the circuit cost of the independent FPGA configuration memory is saved, the board-level area is saved, and the board-level development difficulty is reduced. Meanwhile, the large capacity characteristic of the NAND memory can store a plurality of configuration versions for the FPGA, so that the flexibility of the configuration of the FPGA is improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (modules, systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A system for configuring a field programmable gate array, the system comprising: NAND memory and FPGA;
the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller;
the code matching array is used for storing code matching files of a plurality of versions;
the first configuration interface is used for reading a first configuration code from the configuration code array after power-on, and sending the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration;
the data array is used for storing the access data of the FPGA;
the FPGA is used for sending a data read-write instruction to the NAND controller through the NAND interface;
and the NAND controller is used for performing read-write operation on the data array according to the data read-write instruction.
2. The system of claim 1, wherein the NAND memory further comprises: a version switching module;
the FPGA is used for sending a version switching instruction to the NAND controller through the NAND interface;
the NAND controller is further used for sending the version switching instruction to the version switching module;
the version switching module is used for extracting version information of the second configuration code from the version switching instruction and changing the configuration code address accessed in the first configuration interface according to the version information;
the first configuration interface is further configured to read the second configuration code from the configuration code array according to the configuration code address, and send the second configuration code to the second configuration interface, so that the FPGA configures the second configuration code.
3. The system of claim 2, wherein the code allocation array is further configured to store backup code allocation of the code allocation file;
the version switching module is further configured to detect whether the first configuration interface receives a configuration success signal returned by the second configuration interface; if the first configuration interface does not receive the configuration success signal, a secondary configuration instruction is sent to the first configuration interface;
the first configuration interface is further configured to read the backup configuration code of the first configuration code from the configuration code array according to the secondary configuration instruction, and send the backup configuration code of the first configuration code to the second configuration interface, so that the FPGA performs secondary configuration.
4. A system according to any one of claims 1-3, wherein the code allocation array is further configured to store redundant codes of the code allocation file; the NAND memory further includes:
and the code allocation protection module is used for carrying out error checking and ECC (error correction) correction on the code allocation file and controlling the redundant code allocation.
5. The system of claim 4, wherein the NAND memory further comprises:
and the first JTAG interface is used for burning the code matching files of the multiple versions into the code matching array.
6. The system of claim 5, wherein the FPGA further comprises:
the second JTAG interface is used for carrying out initial configuration on the FPGA;
the FPGA is also used for accessing an external memory through the NAND interface and programming the code matching file in the external memory into the code matching array.
7. A method for configuring a field programmable gate array, the method comprising: NAND memory and FPGA; the NAND memory includes: the FPGA comprises a data array, a code matching array, a first configuration interface and a NAND controller, wherein the FPGA comprises: a second configuration interface and a NAND interface; the method comprises the following steps:
after the NAND memory is electrified, a first configuration code is read from the configuration code array through the first configuration interface, and the first configuration code is sent to the second configuration interface of the FPGA so that the FPGA can be configured, and a plurality of versions of configuration code files are stored in the configuration code array;
the FPGA sends a data read-write instruction to the NAND controller through the NAND interface;
and the NAND controller performs read-write operation on the data array according to the data read-write instruction, and the data array stores the access data of the FPGA.
8. The method of claim 7, wherein the method further comprises:
the FPGA sends a version switching instruction to a version switching module of the NAND memory through the NAND interface;
the version switching module extracts version information of a second configuration code from the version switching instruction, and changes a configuration code address accessed in the first configuration interface according to the version information;
the first configuration interface reads the second configuration code from the configuration code array according to the configuration code address, and sends the second configuration code to the second configuration interface so that the FPGA can be configured.
9. The method of claim 8, wherein after the sending the second configuration code to the second configuration interface, the method further comprises:
and if the version switching module does not receive a configuration success signal returned by the FPGA, reading the backup configuration code of the first configuration code from the configuration code array through the first configuration interface, and sending the backup configuration code of the first configuration code to the second configuration interface so as to enable the FPGA to perform configuration, wherein the backup configuration code of the configuration code file is stored in the configuration code array.
10. The method according to any one of claims 7-9, further comprising:
and the code allocation protection module of the NAND memory performs error checking and correction ECC checking on the code allocation file and controls redundant code allocation of the code allocation file, and the redundant code allocation of the code allocation file is stored in the code allocation array.
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