CN111668287A - Optimized deep trench semiconductor device terminal - Google Patents
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- CN111668287A CN111668287A CN201910164731.2A CN201910164731A CN111668287A CN 111668287 A CN111668287 A CN 111668287A CN 201910164731 A CN201910164731 A CN 201910164731A CN 111668287 A CN111668287 A CN 111668287A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000001413 cellular effect Effects 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 70
- 229920005591 polysilicon Polymers 0.000 claims description 57
- 238000002513 implantation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 abstract description 9
- 230000005684 electric field Effects 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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Abstract
The invention relates to the technical field of semiconductors, in particular to an optimized deep trench semiconductor device terminal, which comprises a virtual set dotted line, wherein the dotted line is a semiconductor active (cellular) region towards the left, the dotted line is a terminal protection region towards the right, the cellular active (cellular) region is positioned in the center of the device on the overlooking plane of the semiconductor device, the terminal protection region is positioned at the outer ring of the active region and surrounds the active region, the device is based on a first conductive type drift region grown on a first conductive type substrate, the lower end of the first conductive type substrate is connected with drain metal, a second conductive type body region is arranged on the first conductive type drift region, and a first groove and a second groove are positioned in the second conductive type body region and extend into an epitaxial layer. According to the invention, the second conductive type impurities are injected into the bottom of the deep groove to form a deeper field limiting ring, so that an electric field at the bottom of the groove is dispersed, the withstand voltage of the terminal is higher than that of the active region, and the reliability is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an optimized deep trench semiconductor device terminal.
Background
In the design of a power semiconductor device, the design of a terminal protection region is very important. The design of the active region determines the characteristics of the device, such as resistance, capacitance, breakdown voltage, etc., but it is limited by the effectiveness and area of the termination protection design. In a good terminal design, in order to ensure the reliability of a device, a voltage breakdown point is required to be located in an active region instead of a terminal protection region, and meanwhile, the occupied area of a terminal can directly influence the on-resistance of the active region.
The deep trench device occupies a larger and larger ratio in the power semiconductor device because the device performance is better than the traditional trench device. However, the conventional terminal design is difficult to solve the problem that the longitudinal electric field distribution of the deep trench device is not balanced at the terminal, so that the terminal design of the deep trench device becomes difficult. At present, an oxide layer is generally directly adopted as a terminal of a deep trench MOSFET, although the process compatibility is good, the withstand voltage of the terminal is lower than that of a cellular, the whole withstand voltage of a device is limited, and the designed on-resistance of the device is higher and the reliability is reduced.
In the prior art, as shown in fig. 1, the design is a traditional field limiting ring terminal design, and the design is usually only suitable for a planar device with transverse electric field distribution and is not suitable for a deep trench device with longitudinal electric field distribution; fig. 2 shows that for the design of a deep trench oxide junction voltage-withstanding terminal, a dotted line from left to right is an active region 001 and a terminal protection region 002, the terminal trench is directly resistant to voltage depending on the thickness of the oxide junction, and since an electric field is not uniform at the terminal and the breakdown voltage of the terminal is lower than that of the active region, a breakdown point usually occurs at a position close to the active region inside the terminal oxide junction, thereby directly affecting the reliability of the device.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides an optimized deep trench semiconductor device terminal.
In order to achieve the purpose, the invention adopts the following technical scheme:
an optimized deep channel semiconductor device terminal comprises a virtual set dotted line, wherein the dotted line is a semiconductor active (cellular) area towards the left, the dotted line is a terminal protection area towards the right, the cellular active (cellular) area is positioned in the center of the device on a top plan of the semiconductor device, the terminal protection area is positioned at the outer ring of the active area and surrounds the active area, the device is based on a first conductive type drift area grown on a first conductive type substrate, the lower end of the first conductive type substrate is connected with drain metal, a second conductive type body area is arranged on the first conductive type drift area, a first groove and a second groove are positioned in the second conductive type body area and extend into an epitaxial layer, an insulating medium layer with a certain thickness is grown in the first groove and the second groove to serve as a field shielding insulating layer, and then the first conductive polysilicon, the second conductive polysilicon, the third conductive polysilicon and the third polysilicon are filled in the field shielding insulating layer, The active region is provided with a first conductive type source region, the first conductive type source region is connected with source metal, active polycrystalline silicon and second conductive polycrystalline silicon are arranged in a groove of the active region and are respectively connected with the source metal and grid metal, a first second conductive type well region is arranged at the bottom of a deep groove of the terminal protection region and serves as a field limiting ring, a first floating mesa unconnected electrode is arranged in the first terminal conductive type well region A, the source polycrystalline silicon is outwards connected with a first second conductive type well region B, the source polycrystalline silicon is outwards connected with a first second conductive type well region C, the source polycrystalline silicon is outwards connected with a second conductive type second well region B, and by analogy, each source polycrystalline silicon is outwards connected with the next adjacent second conductive type second well region.
Preferably, the widths of the first trench in the active region and the second trench in the terminal protection region may be the same or different, and the depths may be the same or different, and the thicknesses of the field shielding insulating medium in the deep trench in the active region and the terminal protection region may be the same or different.
Preferably, in the active region, the distance between adjacent first trenches is the same, and in the termination protection region, the distance between a second trench and the last first trench of the active region is less than or equal to the distance between adjacent trenches of the active region, and then the distance between adjacent second trenches is the same as that of the active region or gradually increases along the direction from the active region to the termination protection region.
Preferably, the second conductivity type first well region a, the second conductivity type first well region B, and the second conductivity type first well region BThe first well region C and the second well region A of the second conductivity type can be formed by implantation in the same process, with implantation energy ranging from 10KeV to 200KeV and implantation dosage ranging from 10KeV12-1016。
Preferably, the number of the deep trenches and the field limiting rings of the termination protection region can be more than or equal to one, and is determined by the breakdown voltage of the epitaxial layer and the active region of the device.
Preferably, the active region structure may be an upper-lower structure or a left-right structure, the second conductive polysilicon may be longitudinally isolated from the source polysilicon by the insulating dielectric layer, or the second conductive polysilicon may surround the source polysilicon and be laterally isolated from the source polysilicon by the insulating dielectric layer.
Preferably, when the device is resistant to voltage, the first floating mesa design of the terminal enables the last mesa of the active region to be still in a charge balance state, the voltage of a drift region at the lower end of the trench transversely extends with the help of the deep trench field limiting ring, the terminal conductive polysilicon is connected to the next mesa, so that the field limiting ring effect can be effectively transmitted between trenches, the terminal voltage resistance is not limited by the voltage resistance of the active region due to reasonable arrangement of the terminal deep trench field limiting rings, and the voltage resistance higher than that of the active region is obtained.
Compared with the prior art, the invention provides an optimized deep trench semiconductor device terminal, which has the following beneficial effects:
the invention can provide effective terminal protection for deep trench devices; the second conductive type impurities are injected into the bottom of the deep groove to form a deeper field limiting ring, so that an electric field at the bottom of the groove is dispersed, the withstand voltage of a terminal is higher than that of an active region, and the reliability is improved; the deep trench oxide layer does not need to be very thick, so that the epitaxial layer design can be optimized, and the on-resistance of the trench MOSFET can be effectively improved; the deep groove depth design does not need to be increased along with the increase of voltage, and the process is superior; the process is compatible, extra thermal annealing is not needed, and the influence on the whole process of the device is small; the second conductive type second well region is circular, so that the width of the terminal protection region can be effectively reduced, and the chip area is saved.
Drawings
FIG. 1 is a conventional field limiting ring design;
FIG. 2 is a schematic diagram of a conventional deep trench oxide junction termination;
FIG. 3 is a cross-sectional view of the source metal after formation according to the present invention;
FIG. 4 is another form of the present invention;
FIG. 5 is a schematic cross-sectional view of an epitaxial wafer on a silicon substrate at a first step in the process of the present invention;
FIG. 6 is a schematic cross-sectional view of an active region and termination region deep trench formation;
FIG. 7 is a schematic diagram of a terminal second type implant forming a deep trench bottom second well region and a surface first well region;
FIG. 8 is a cross-sectional view of a deep trench after an oxide layer is formed therein;
FIG. 9 is a schematic cross-sectional view of the formation of source polysilicon in the deep trench oxide layer;
FIG. 10 is a schematic cross-sectional view of the active region source polysilicon being pulled back into the trench and covered with an insulating dielectric layer;
FIG. 11 is a schematic cross-sectional view of a gate oxide layer and a gate polysilicon layer after formation;
fig. 12 is a schematic cross-sectional view after the active region is implanted with the second-type body region and the first-type source region;
fig. 13 is a schematic diagram showing the potential distribution in the cross section when the device is resistant to voltage.
In the figure: a 001 semiconductor active (cell) region, a 002 terminal protection region, a1 drain metal, a 2 first conductivity type substrate, a 3 first conductivity type drift region, a 4 field shield insulating layer, a 5 first conductivity polysilicon, a 6 second conductivity type body region, a 7 first conductivity type source region, an 8 second conductivity polysilicon, a 9 third conductivity polysilicon, a 10 fourth conductivity polysilicon, a 11 fifth conductivity polysilicon, a 12 sixth conductivity polysilicon, a13 second conductivity type second well region a, a14 second conductivity type first well region a, a 15 second conductivity type first well region B, a 16 second conductivity type first well region C, a 17 second conductivity type second well region B, an 18 first trench, and a 19 second trench.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Referring to fig. 3-13, an optimized deep trench semiconductor device termination includes a virtual dotted line, the dotted line is a semiconductor active (cell) region 001 to the left and a termination protection region 002 to the right, in a top view of the semiconductor device, the cell active (cell) region 001 is located at the center of the device, the termination protection region 002 is located at the outer ring of the active region and surrounds the active region 001, the device is based on a first conductive type drift region 3 grown on a first conductive type substrate 2, the lower end of the first conductive type substrate 2 is connected to a drain metal 1, a second conductive type body region 6 is disposed above the first conductive type drift region, a first trench 18 and a second trench 19 are located in the second conductive type body region and go deep into an epitaxial layer 3, an insulating dielectric layer with a certain thickness is grown in the first trench 18 and the second trench 19 to serve as a field shielding insulating layer 4, then, the first conductive polysilicon 5, the second conductive polysilicon 8, the third conductive polysilicon 9, the fourth conductive polysilicon 10, the fifth conductive polysilicon 11, and the sixth conductive polysilicon 12 are filled, a first conductive source region 7 is arranged on a second conductive body region of the active region 001, the first conductive source region 7 is connected with source metal, active polar polysilicon 5 and the second conductive polysilicon 8 are arranged in a groove of the active region and are respectively connected with the source metal and gate metal, a second conductive first well region 13 is arranged at the bottom of a deep groove of the terminal protection region and serves as a field limiting ring, a terminal second conductive first well region A14 is a floating mesa unconnected electrode, the source polysilicon 10 is externally connected with a second conductive first well region B15, the source 11 is externally connected with a second conductive first well region C16, the source polysilicon 12 is externally connected with a second conductive second well region B17, and the like, each source polysilicon is connected to the next adjacent second conductive type second well region outwards.
The widths of the first trench 18 in the active region 001 and the second trench 19 in the terminal protection region 002 may be the same or different, and the depths may be the same or different, and the thicknesses of the field shielding insulating medium in the deep trench in the active region 001 and the terminal protection region may be the same or different.
In the active region 001, the distance between adjacent first trenches 18 is the same, and in the terminal protection region 002, the distance between the second trench 19 and the last first trench 18 of the active region is less than or equal to the distance between adjacent trenches of the active region, and then the distance between adjacent second trenches 19 is the same as that of the active region or gradually increases along the direction from the active region 001 to the terminal protection region 002.
The second conductive type first well region a14, the second conductive type first well region B15, the second conductive type first well region C16 and the second conductive type second well region a13 can be formed by implantation in the same process, the implantation energy range is 10KeV-200KeV, and the implantation dosage range is 10KeV12-1016。
The design number of the deep grooves and the field limiting rings of the terminal protection region can be more than or equal to one, and is determined by the breakdown voltage of the epitaxial layer and the active region of the device.
The active region structure can be an upper structure, a lower structure or a left-right structure, the second conductive polysilicon 8 can be longitudinally isolated from the source polysilicon by the insulating medium layer 4, or the second conductive polysilicon 8 can surround the source polysilicon and is laterally isolated from the source polysilicon by the insulating medium layer 4.
When the device is resistant to voltage, the last mesa of the active region can still be in a charge balance state due to the first floating mesa design of the terminal, the voltage of a drift region at the lower end of the trench transversely extends with the help of a deep trench field limiting ring, the field limiting ring effect can be effectively transmitted between trenches due to the connection of the terminal conductive polycrystalline silicon to the next mesa, the terminal voltage resistance is not limited by the voltage resistance of the active region due to the reasonable arrangement of the terminal deep trench field limiting rings, and therefore the voltage resistance higher than that of the active region is obtained.
In this embodiment, taking a power semiconductor device with an N-type deep trench as an example, an N-type silicon substrate 2 is disposed on a drain metal 1, an N-type epitaxial layer 3 is disposed on the N-type silicon substrate 2, a first trench 18 and a second trench 19 are located in a p-type body region and extend into the epitaxial layer 3, an insulating dielectric layer with a certain thickness is grown in the first trench 18 and the second trench 19 to serve as a field shielding insulating layer 4 and is filled with a first conductive polysilicon 5, a second conductive polysilicon 8, a third conductive polysilicon 9, a fourth conductive polysilicon 10, a fifth conductive polysilicon 11 and a sixth conductive polysilicon 12, a first conductive source region 7 is disposed on the p-type body region of an active region 001, the first conductive source region 7 is connected to a source metal, an active polysilicon 5 and a second conductive polysilicon 8 are disposed in the trench of the active region and are respectively connected to the source metal and a gate metal, a gate oxide layer is disposed on the periphery of the gate polysilicon, a first p-type well region is arranged at the bottom of the deep trench of the terminal protection region and serves as a field limiting ring, and a second p-type well region is arranged on the surface of the terminal. The first second p-type well region 14 at the terminal is floating mesa and is not connected with an electrode, the source polysilicon 10 is connected with the second p-type well region 15 outwards, the source polysilicon 11 is connected with the second p-type well region 16 outwards, the source polysilicon 12 is connected with the second p-type well region 17 outwards, and so on, and each source polysilicon is connected with the next adjacent p-type well region mesa outwards.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. An optimized deep channel semiconductor device terminal comprises a virtual set dotted line, wherein the dotted line is a semiconductor active (cellular) area towards the left, the dotted line is a terminal protection area towards the right, the cellular active (cellular) area is positioned in the center of the device on a top plan of the semiconductor device, the terminal protection area is positioned at the outer ring of the active area and surrounds the active area, the device is based on a first conductive type drift area grown on a first conductive type substrate, the lower end of the first conductive type substrate is connected with drain metal, a second conductive type body area is arranged on the first conductive type drift area, a first groove and a second groove are positioned in the second conductive type body area and extend into an epitaxial layer, an insulating medium layer with a certain thickness is grown in the first groove and the second groove to serve as a field shielding insulating layer, and then the first conductive polysilicon, the second conductive polysilicon, the third conductive polysilicon and the third polysilicon are filled in the field shielding insulating layer, The active region is provided with a first conductive type source region, the first conductive type source region is connected with source metal, active polycrystalline silicon and second conductive polycrystalline silicon are arranged in a groove of the active region and are respectively connected with the source metal and grid metal, a second conductive type second well region A is arranged at the bottom of a deep groove of the terminal protection region and serves as a field limiting ring, the terminal second conductive type first well region A is a floating mesa unconnected electrode, the source polycrystalline silicon is outwards connected with a second conductive type first well region B, the source polycrystalline silicon is outwards connected with a second conductive type first well region C, the source polycrystalline silicon is outwards connected with a second conductive type second well region B, and by analogy, each source polycrystalline silicon is outwards connected with the next adjacent second conductive type second well region.
2. The optimized deep trench semiconductor device terminal as claimed in claim 1, wherein the width of the first trench in the active region and the second trench in the terminal protection region may be the same or different, and the depth thereof may be the same or different, and the thickness of the field shield insulating medium in the deep trench may be the same or different between the active region and the terminal protection region.
3. The optimized deep trench semiconductor device terminal as claimed in claim 1, wherein the spacing between adjacent first trenches in said active region is the same, and the spacing between a second trench and the last first trench of the active region in the terminal protection region is less than or equal to the spacing between adjacent trenches of the active region, and then the spacing between adjacent second trenches is the same as the active region or gradually increases along the direction of the active region toward the terminal protection region.
4. The optimized deep trench semiconductor device terminal of claim 1 wherein the second conductivity type first well region a, the second conductivity type first well region B, the second conductivity type first well region C and the second conductivity type second well region a are formed by a single implantation process with an implantation energy ranging from 10KeV to 200KeV and an implantation dose ranging from 10KeV12-1016。
5. The optimized deep trench semiconductor device terminal as claimed in claim 1, wherein the designed number of deep trenches and field limiting rings of the terminal protection region can be more than or equal to one, and is determined by the breakdown voltage of the epitaxial layer and the device active region.
6. The optimized deep trench semiconductor device termination of claim 1 wherein said active region structure is either a top-bottom structure or a left-right structure, and wherein said second conductive polysilicon is either vertically above and laterally separated from said source polysilicon by an insulating dielectric layer, or wherein said second conductive polysilicon surrounds and is laterally separated from said source polysilicon by an insulating dielectric layer.
7. The optimized deep trench semiconductor device termination of claim 1, wherein when the device is withstanding voltage, the termination first floating mesa design allows the last mesa in the active region to remain in charge balance and the lower drift voltage of the trench to laterally spread with the help of deep trench field-limiting rings, the termination conductive polysilicon connected to the next mesa allows the field-limiting ring effect to be effectively transferred between the trenches, and the proper termination deep trench field-limiting ring arrangement allows the termination withstanding voltage to be independent of the active region withstanding voltage, thereby obtaining a higher withstanding voltage than the active region.
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| CN201910164731.2A CN111668287A (en) | 2019-03-05 | 2019-03-05 | Optimized deep trench semiconductor device terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024041001A1 (en) * | 2022-08-25 | 2024-02-29 | 中国电子科技集团公司第二十四研究所 | High-voltage power semiconductor device and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024041001A1 (en) * | 2022-08-25 | 2024-02-29 | 中国电子科技集团公司第二十四研究所 | High-voltage power semiconductor device and manufacturing method therefor |
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