CN111666595A

CN111666595A - Physical unclonable function structure based on delay configurable oscillator

Info

Publication number: CN111666595A
Application number: CN202010659520.9A
Authority: CN
Inventors: 郭阳; 邓丁; 屈婉霞; 扈啸; 胡春媚; 侯申
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2020-07-09
Filing date: 2020-07-09
Publication date: 2020-09-15
Anticipated expiration: 2040-07-09
Also published as: CN111666595B

Abstract

A physically unclonable function structure based on a delay configurable oscillator, comprising: n identical ring oscillators with configurable time delay are connected in parallel, time delay control signals at the same position of each ring oscillator are assigned by time delay control excitation in a unified mode, and N is an even number; the output ports of N/2 ring oscillators are connected with the data input port of one N/2-to-1 selector, and the output ports of the rest N/2 ring oscillators are connected with the data input port of the other N/2-to-1 selector; the output ports of the two data selectors are respectively connected with the clock ports of the two counters, and the count value output ports of the two counters are connected with the comparison value input port of the comparator with the offset option. The invention has the advantages of high flexibility, small area overhead, large excitation response space, controllable reliability and the like.

Description

Physical unclonable function structure based on delay configurable oscillator

Technical Field

The invention mainly relates to the field of chip identification and authentication, in particular to a physical unclonable function structure based on a delay configurable oscillator.

Background

In order to prevent the chips from being cloned, the IP from being stolen, and the processed data from being intercepted, designers mostly need to give one or more keys as a "security root" to each chip. Conventional approaches typically store these keys in non-volatile memory of the chip. However, with the development of reverse engineering and hardware attack techniques, an attacker can break the key of each chip by means of focused ion beams, scanning electron microscopes, and the like, and further make all security mechanisms based on the key behave as dummies. The Physical Unclonable Function (PUF) extracts the unique process deviation of each chip by utilizing the characteristic that the chip has inevitable process deviation in the production and manufacturing process, and has the advantages of unpredictability, Unclonable property, low cost and the like as a 'fingerprint' for identifying and authenticating the identity of the chip. Therefore, PUFs are of great interest once proposed.

A ring oscillator physical unclonable function (ropf) is constructed based on the inherent bias of device cell delay, the conventional structure of which is shown in fig. 1. N ring oscillators formed by connecting end to end 1 NAND gate and m (m is an even number) inverters are constructed. The output of N ring oscillators is respectively connected with the data input ports of two N-to-1 data selectors, the data output ports of the two N-to-1 data selectors are respectively connected with the clock ports of two counters, and the data output ports of the two counters are connected with the data input ports of the comparators. Although the structures of the N ring oscillators are completely the same, in the actual production process, more or less deviation from the expected value is inevitable due to the delay of the NAND gates and the inverters in each ring oscillator. Therefore, the oscillation period of each ring oscillator is not exactly the same. Two of the N oscillator output signals (the two selectors cannot select the output signal of the same oscillator) are selected by configuring selection signals (called excitation) of the two data selectors, and are respectively used as clock signals of the two counters to drive the counters to work. Let the enable signal be "1" and all oscillation loops start to oscillate. After a certain time (hereinafter referred to as oscillation measurement time t), the count values in the counters respectively reflect the number of oscillations of the two selected oscillation rings in the period. The magnitude of the two count values is compared by a comparator to obtain a comparison result (called response), and if the count value1 > the count value2, the response is "1", and if the count value1 < > the count value2, the response is "0".

Since process variations are unique for each chip, the resulting responses are different even if the same excitation is applied to different chips (i.e., two oscillation rings at the same location are selected for comparison); due to unavoidable and uncontrollable process variations, an attacker cannot clone a chip with exactly the same stimulus → Response mapping (CRP).

However, the conventional oscillation ring type physical unclonable function also has the following disadvantages:

(1) the number of CRPs was too small.

The ROPUF formed by N ring oscillators can only generate N (N-1)/2 CRPs at most, and is difficult to adapt to the application scene of 'authentication' requiring multiple excitation replacement.

(2) The area overhead is too large.

(3) There is a correlation between CRPs.

For example, if the oscillation frequency of the oscillation ring a is known to be greater than that of the oscillation ring b, and the frequency of the oscillation ring b is known to be greater than that of the oscillation ring c, it can be inferred that the oscillation frequency of the oscillation ring a is greater than that of the oscillation ring c without actual testing. Thus, if the attacker intercepts the first two responses (i.e., f)_a＞f_b，f_b＞f_c) Then f can be predicted_a＞f_c。

(4) The reliability is low.

Although the oscillation frequencies of the oscillation rings are different due to process variations, the range of the variations is limited after all. If the actual oscillation frequencies of the two oscillation rings are very close, different responses can be obtained under the influence of measurement noise, environmental changes and the like under the condition of multiple measurements.

In view of the disadvantage of the correlation between CRP, there was a study to change the structure of fig. 1 to that shown in fig. 2. In fig. 2, only the output signals of N/2 oscillator loops are connected to the data input of data selector 1, and the output signals of the remaining N/2 oscillator loops are connected to the data input of data selector 2. The ROPUF with the structure of FIG. 2 has at most N although the correlation between CRP is eliminated²4 CRP. Therefore, if the structure of fig. 2 is to have the same number of CRPs as the structure of fig. 1, the number N of ring oscillators to be constructed must be larger, i.e., the area overhead is larger.

Aiming at the defect of low reliability, the traditional solution method comprises a majority voting mechanism and a maximum differentiation mechanism. The majority voting mechanism (majorityvoting) measures and compares K (K is an odd number) times for two oscillation rings selected by a certain excitation, and determines the final response of the excitation according to a minority majority-obeying principle. Obviously, this method will extend the time to generate a response by at least a factor of K. The most differentiated mechanism (also called 1-out-of-Kmask mechanism) is to divide N ring oscillators into

A small group with capacity of K, applying excitation

1 of the small groups is selected and the frequencies of the K ring oscillators in the small group are measured, and only the comparison results of the 2 oscillator rings in which the frequency differences are the largest are taken as the final response. Obviously, this approach will reduce the ring oscillator utilization by a factor of K.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a physical unclonable function structure based on a delay configurable oscillator, which has the advantages of high flexibility, small area overhead, large excitation response space and controllable reliability.

In order to solve the technical problems, the invention adopts the following technical scheme:

a physically unclonable function structure based on a delay configurable oscillator, comprising:

n identical ring oscillators with configurable time delay are connected in parallel, time delay control signals at the same position of each ring oscillator are assigned by time delay control excitation in a unified mode, and N is an even number;

the output ports of N/2 ring oscillators are connected with the data input port of one N/2-to-1 selector, and the output ports of the rest N/2 ring oscillators are connected with the data input port of the other N/2-to-1 selector;

the output ports of the two data selectors are respectively connected with the clock ports of the two counters, and the count value output ports of the two counters are connected with the comparison value input port of the comparator with the offset option.

As a further improvement of the invention: the excitation C is controlled by time delay_DAnd selection compare stimulus C_MTwo-part, i.e. C ═ C_M1，C_M2，C_D}，C_MComprising C_M1，C_M2(ii) a If the offset enable is 0, then the response R is only represented by the response value R_VComposition is carried out; if the offset enable is 1, the response is represented by the response value R_VAnd a valid flag R_FComposition, i.e. R ═ { R ═ R_V，R_F}。

As a further improvement of the invention: the ring oscillator determines the stage number m of the oscillator according to the requirements of area overhead and CRP number, randomly selects the type of the delay controllable unit and connects the selected delay controllable unit with an AND gate or an NAND gate end to end in series according to a chain rule to form the delay controllable ring oscillator; the oscillation frequency of the whole ring oscillator is changed by changing the delay control excitation.

As a further improvement of the invention: the chaining rule includes:

(1) the RO _ I port of the current stage is connected with the RO _ F port of the previous stage, and the RO _ F port of the current stage is connected with the RO _ I port of the next stage;

(2) inserting an AND gate or an NAND gate at the chain head of each delay configurable ring oscillator as a control unit of an oscillation mode;

(3) in each delay configured ring oscillator, there must be an odd number of cells that can act as an anti-phase to RO _ I.

As a further improvement of the invention: the input signal of the delay controllable unit comprises: a delay control signal Cl and an oscillation input signal RO _ I; the output signals of the delay controllable unit are as follows: an oscillation output signal RO _ F; for the delay controllable units of D1 and D3, RO _ I is-RO _ F, that is, the delay controllable units have an inverting function; for delay-controllable units of type D2 and type D4, RO _ I is RO _ F, i.e. the logic value does not change.

As a further improvement of the invention:

for delay-controllable unit type D1, when Cl is 1, the rise time of RO _ F is D_AND+d_NORWhen Cl is 0, the rise time of RO _ F is d_NOR；

For delay-controllable unit type D2, when Cl is 1, the fall time of RO _ F is D_AND+d_ORWhen Cl is 0, the fall time of RO _ F is d_OR；

For delay-controllable unit type D3, when Cl is 1, the fall time of RO _ F is D_NANDWhen Cl is 0, the fall time of RO _ F is d_OR+d_NAND；

For delay-controllable unit type D4, when Cl is 1, the rise time of RO _ F is D_ANDWhen Cl ═ O, the rise time of RO _ F is d_OR+d_AND。

As a further improvement of the invention: the comparator with the offset option comprises a subtracter, a comparator and a scanning chain with the length of p; the subtracter is used for calculating the magnitude of two comparison values, namely Value1 and Value2, wherein the absolute Value of the difference between the two comparison values is called as an absolute difference, Dif _ abs; if Value1 is greater than Value2, the comparison result Rv is 1; if Value1 < ═ Value2Then compare the result R_VIs 0; assuming that the flip-flops in the scan chain are all reset at low level and the shift function is enabled at high level, the reset ports of the flip-flops in the scan chain are directly connected to the shift enable signal BIAS _ EN. The BIAS configuration port BIAS _ CFG is connected with a scanning input port of a first trigger in the scanning chain; in a scanning state, each trigger in the scanning chain is assigned through an offset configuration port BIAS _ CFG, and the values of all the triggers form a p-bit offset BIAS [ p-1: 0 ]]。

As a further improvement of the invention: if the reset level is the same as the offset enable level, an inverter is inserted and connected.

Compared with the prior art, the invention has the advantages that:

the invention relates to a physical unclonable function structure based on a delay configurable oscillator, which is used for identifying and authenticating a chip. The invention has the advantages of high flexibility, small area overhead, large excitation-response space, controllable reliability and the like. The invention can be used as ROPUF to serve the fields of hardware identification, authentication and the like.

Drawings

Fig. 1 is a structural diagram of a conventional oscillation ring type physical unclonable function.

FIG. 2 is a structural diagram of a ringing-type physically unclonable function for eliminating CRP correlation.

Fig. 3 is a schematic diagram of a physical unclonable function structure based on a delay configurable oscillator according to the present invention.

FIG. 4 is a schematic diagram of four delay control units according to an embodiment of the present invention; wherein (a) is a delay control unit of D1 type; (b) is a D2 type delay control unit; (c) is a D3 type delay control unit; (d) is a delay control unit D4.

FIG. 5 is a diagram illustrating the control of the RI _ F fall time in a D2 type cell by Cl in an embodiment of the present invention; wherein (a) is in the Cl 0 state; (b) in the Cl-1 state.

FIG. 6 is a schematic diagram of a delay configurable ring oscillator according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a comparator with offset option in an embodiment of the present invention

Fig. 8 is a schematic diagram of a physical unclonable function structure based on a delay configurable oscillator in a specific application example of the present invention.

FIG. 9 is a signal timing diagram illustrating the application of 64 stimuli to an embodiment of the present invention in a specific application example; wherein (a) is a case where reliability control is not performed; (b) in the case of reliability control.

Detailed Description

The invention will be described in further detail below with reference to the drawings and specific examples.

As shown in fig. 3, the physical unclonable function structure (ROPUF) based on a configurable delay oscillator of the present invention includes:

n (N is an even number) identical ring oscillators (each oscillator has the length of m levels) with configurable time delay, time delay control signals at the same position of each ring oscillator are connected in parallel, and are assigned by time delay control excitation in a unified mode;

the output ports of N/2 ring oscillators are connected with the data input port of one N/2-to-1 selector (called a first data selector), and the output ports of the rest N/2 ring oscillators are connected with the data input port of another N/2-to-1 selector (called a second data selector).

The output ports of the two data selectors (the first data selector and the second data selector) are respectively connected with the clock ports of the two counters, and the count value output ports (namely, the first count value and the second count value) of the two counters are connected with the comparison value input port of the comparator with the offset option.

In a specific application example, in the above-mentioned delay configurable ROPUF structure of the present invention, the stimulus C is controlled by the delay control stimulus C_DAnd selection compare stimulus C_M(including C)_M1，C_M2) Two-part, i.e. C ═ C_M1，C_M2，C_D}. If the offset enable is 0, then the response R is simply composed ofResponse value R_VComposition (with no reliability control at this point, i.e. by default each R_VAre both effective and reliable). If the offset enable is 1, the response is represented by the response value R_VAnd a valid flag R_FComposition, i.e. R ═ { R ═ R_V，R_FIn this case, the reliability control function is provided, when R is_FWhen 1, R represents the corresponding time_VThe method is effective and reliable; when the RF is 0, R corresponding to the time is represented_VInvalid and unreliable).

As shown in fig. 4, in a specific application example, the input signal of the delay controllable unit includes: a delay control signal Cl and an oscillation input signal RI _ I. The output signals of the delay controllable unit are as follows: the oscillation output signal RO _ F. For delay controllable units of D1 and D3, RO _ I is RO _ F, i.e., has an inverting function. For delay-controllable units of type D2 and type D4, RO _ I is RO _ F, i.e. the logic value does not change.

Assume that the rise delay of a particular type of gate is equal to the fall delay and equal to the propagation delay of that gate. With d_AND，d_OR，d_NAND，d_NORRespectively representing the propagation delay of an AND gate, an OR gate, a NAND gate and a NOR gate.

For delay-controllable units of type D1, Cl can adjust the rise time of RO _ F. Specifically, when Cl ═ 1, the rise time of RO _ F is d_AND+d_NORWhen Cl is 0, the rise time of RO _ F is d_NOR。

For delay-controllable units of type D2, Cl can adjust the fall time of RO _ F. Specifically, when Cl is 1, the fall time of RO _ F is d_AND+d_ORWhen Cl is 0, the fall time of RO _ F is d_OR。

For delay-controllable units of type D3, Cl can adjust the fall time of RO _ F. Specifically, when Cl is 1, the fall time of RO _ F is d_NANDWhen Cl is 0, the fall time of RO _ F is d_OR+d_NAND。

For delay-controllable units of type D4, Cl can adjust the rise time of RO _ F. Specifically, when Cl ═ 1, the rise time of RO _ F is d_ANDWhen Cl is 0, RThe rise time of I _ F is d_OR+d_AND。

As shown in fig. 5, the principle of controllable delay of D2 type cell is shown, and so on for 3 other principles of controllable delay of cell. In a D2 type cell, the transition time of RO _ F depends on two input signals of the or gate: RO _ I AND the output signal of AND gate AND _ OUT. When Cl is 0, the output of the and gate in the cell is fixed to 0 regardless of the value of RO _ I. If the falling jump of RO _ I occurs, the falling jump can be transferred to RO _ F only through the OR gate in the unit because the output of the AND gate is equal to 0 at this time, so the falling time of RO _ F is d_OR. When Cl is 1, if RO _ I generates a falling jump, the output of the AND gate is at d_ANDThen becomes 0, so the falling transition of RO _ I must go through d_AND+d_ORBefore it is delivered to RO _ F, i.e. the falling time of RO _ F is d_AND+d_OR。

The present invention utilizes the above 4 delay controllable units, and as shown in fig. 6, the present invention obtains a ring oscillator with configurable delay.

Firstly, determining the number m of the stages of the oscillator according to the requirements of the area overhead and the CRP number;

then, randomly selecting the type of the delay controllable unit and connecting the selected delay controllable unit and an AND gate (or an NAND gate) end to end in series according to a certain serial rule to form the delay controllable ring oscillator. By varying the delay control excitation (C1, C2, … …, C)_m-1，C_m) The oscillation frequency of the entire ring oscillator can be changed.

And (3) chain chaining rule:

(1) the RO _ I port of the present stage is connected to the RO _ F port of the previous stage, and the RO _ F port of the present stage is connected to the RO _ I port of the next stage.

(2) And an AND gate or a NAND gate is inserted at the chain head of each delay configurable ring oscillator to be used as a control unit of the oscillation mode.

(3) In each delay configured ring oscillator, there must be an odd number of cells that can act as an anti-phase to RO _ I. (each nand gate, D1, D3 cell counts as inverting logic).

In a specific application example, as shown in fig. 7, the comparator with offset option of the present invention is used to provide a choice whether to perform reliability screening for the frequency comparison of the ropf.

The comparator with offset option comprises a subtracter, a comparator and a scan chain with the length p. The subtractor is used to calculate the magnitude of the comparison Value 1(Value1) and the comparison Value 2(Value2), and the absolute Value of the difference between them (called the absolute difference, diff _ abs). If Value1 > Value2, the results are compared (R)_V) Is 1; if Value1 < ═ Value2, the results are compared (R)_V) Is 0. Assuming that all the flip-flops in the scan chain are reset at low level and the offset function is enabled at high level, the reset port of the flip-flop in the scan chain is directly connected with the offset enable signal (BIAS _ EN) (if the reset level is the same as the offset enable level, an inverter needs to be inserted for connection). The offset configuration port (BIAS _ CFG) is connected to the scan input port of the first flip-flop in the scan chain. In the scanning state, each trigger in the scanning chain can be assigned through an offset configuration port (BIAS _ CFG), and the values of all the triggers form p-bit offset amount BIAS [ p-1: 0 ]]. The magnitude of the offset is determined by the PUF designer based on the desired frequency of the oscillator, oscillation measurement time, environmental noise, and reliability requirements.

If the offset enable signal (BIAS _ EN) is 0, all flip-flops in the scan chain are in the reset state, i.e., the BIAS [ p-1: 0 ]]0. Since the absolute value of the difference between the comparison value1 and the comparison value2 is constantly equal to or greater than 0, the result of the comparison between the absolute difference and the offset (called the valid flag, R)_F) The constant value is 1, and the function of reliable screening is not provided.

If the offset enable signal (BIAS _ EN) is 1, the offset BIAS [ p-1: 0 ] is configured]Then, the comparator judges the magnitude relationship between the comparison value1 and the comparison value2, and also compares the absolute difference Dif _ abs and the offset Bias [ p-1: 0 ]]A comparison is made. If Dif _ abs is less than Bias, that is, the difference between Value1 and Value2 is smaller than the preset offset, it indicates that the difference between the oscillation frequencies of the two oscillation rings for comparison is not large enough, and the obtained comparison is performedResults R_VMay be less stable, valid (R) marker_F) And 0 is output. If Dif _ abs ═ Bias, that is, the difference between Value1 and Value2 is greater than or equal to the preset offset, it means that the difference between the oscillation frequencies of the two oscillation rings for comparison is large enough, and the comparison result R is obtained_VMore stable, effective marker (R)_F) And outputting 1. The larger the configured offset Bias, is, the more significant it is marked as being (i.e., R)_F1) comparison result R_VIs higher, and therefore, the comparator compares the comparison result R_VAnd the system has a reliability screening control function.

Fig. 8 shows an embodiment of the present invention. In the application embodiment, 128 identical 4-stage delay configurable oscillators are constructed, so that the delay of the delay configurable oscillators is 2 in total⁴With 16 arrangements, C is excited by time-delay control_D[3∶0]And (5) controlling. The number of stages playing a role of inversion in the oscillation ring is 3 (NAND gate 1 stage + D3 type unit 1 stage + D1 type unit 1 stage), is an odd number, and meets the 3 rd constraint of the chaining rule. The output signals of the 128 oscillators are divided into two groups, the first group comprising the output signals of the first 64 oscillators: RO ₁1，RO₁2，……，RO₁64; the second group includes the output signals of the last 64 oscillators: RO ₂1，RO₂2，……，RO₂64. The 64 oscillation signals in each group are respectively connected with the input port of a 64-to-1 selector, and the output port of the selector is connected with the clock port of the counter. Selecting excitation C by controlling comparison_M1[5∶0]And C_M2[5∶0]Any one of the oscillation signals in the first group and the second group can be respectively selected to drive the following counter to perform the counting operation.

Referring to fig. 9, a timing diagram of the signals during the 64 excitations applied to the example structure and oscillation measurements made is shown. FIG. 9(a) shows a scenario where reliability control is not performed (i.e., no offset function is used), so BIAS _ EN and BIAS _ CFG remain at 0 throughout the process, and R is_FThe output is always 1. FIG. 9(b) is a scenario for controlling reliability (i.e., using offset work)Can). Before the oscillation measurement, the comparator needs to be configured with an offset. It is therefore necessary to place the scan chain in the scan state and have BIAS _ EN at 1, with the offset input serially through the BIAS _ CFG port. After the offset configuration is finished, the scan chain is returned to the normal working state and BIAS _ EN is kept to be 1. After each segment of oscillation is completed, the oscillation enable signal is pulled low, and the excitation C15: 0 can be collected]＝{C_M1[5∶0]，C_M2[5∶0]，C_D[3∶0]Response under { R ═ R }_V，R_F}. If R is_FWhen the number is 1, R in this case is described_VThe method is reliable and effective; if R at this time_FWhen it is 0, R in this case is indicated_VUnreliable and should be discarded.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims

1. A physically unclonable function architecture based on a delay configurable oscillator, comprising:

2. The latency-based configurability of claim 1Physical unclonable function structure of a built-in oscillator, characterized in that said excitation C is controlled by a delay C_DAnd selection compare stimulus C_MTwo-part, i.e. C ═ C_M1，C_M2，C_D}，C_MComprising C_M1，C_M2(ii) a If the offset enable is 0, then the response R is only represented by the response value R_VComposition is carried out; if the offset enable is 1, the response is represented by the response value R_VAnd a valid flag R_FComposition, i.e. R ═ { R ═ R_V，R_F}。

3. The physical unclonable function structure based on the delay configurable oscillator according to claim 1 or 2, wherein the ring oscillator determines the number m of the oscillator according to the requirements of area overhead and CRP number, randomly selects the type of the delay controllable unit, and connects the selected delay controllable unit with an AND gate or an NAND gate end to end in series according to the chain rule to form the delay controllable ring oscillator; the oscillation frequency of the whole ring oscillator is changed by changing the delay control excitation.

4. A delay configurable oscillator based physically unclonable function structure as claimed in claim 3, wherein said chaining rules comprise:

(1) the R0_ I port of the current stage is connected with the R0_ F port of the previous stage, and the R0_ F port of the current stage is connected with the R0_ I port of the next stage;

(3) in each delay configured ring oscillator, there must be an odd number of cells that can invert the R0_ I.

5. The physically unclonable function structure based on configurable delay oscillator of claim 3, wherein the input signal of the delay controllable unit comprises: a delay control signal Cl, an oscillation input signal R0_ I; the output signals of the delay controllable unit are as follows: an oscillation output signal R0_ F; for the delay controllable units of D1 type and D3 type, R0_ I is — R0_ F, that is, has an inverting function; for delay controllable units of D2 and D4, R0_ I is R0_ F, i.e., the logic value is not changed.

6. The physically unclonable function architecture based on delay configurable oscillator of claim 5, characterized in that:

for the delay controllable unit of type D1, when Cl is 1, the rise time of R0_ F is D_AND+d_NORWhen CI is 0, the rise time of R0_ F is d_NOR；

For the delay controllable unit of D2 type, when CI is 1, the falling time of R0_ F is D_AND+d_ORWhen Cl is 0, the fall time of R0_ F is d_0R；

For the delay controllable unit of D3 type, when CI is 1, the falling time of R0_ F is D_NANDWhen CI is 0, the fall time of R0_ F is d_0R+d_NAND；

For the delay controllable unit of type D4, when CI is 1, the rise time of R0_ F is D_ANDWhen Cl is 0, the rise time of R0_ F is d_0R+d_AND。

7. The physically unclonable function architecture based on delay configurable oscillator of claim 5, characterized in that: the comparator with the offset option comprises a subtracter, a comparator and a scanning chain with the length of p; the subtracter is used for calculating the magnitude of two comparison values, namely Value1 and Value2, wherein the absolute Value of the difference between the two comparison values is called as an absolute difference, Dif _ abs; if Value1 > Value2, the result R is compared_VIs 1; if Value1 < ═ Value2, the result R is compared_VIs 0; assuming that the flip-flops in the scan chain are all reset at low level and the shift function is enabled at high level, the reset ports of the flip-flops in the scan chain are directly connected to the shift enable signal BIAS _ EN. The BIAS configuration port BIAS _ CFG is connected with a scanning input port of a first trigger in the scanning chain; in the scanning state, the ports BIAS-CFG are configured to beEach flip-flop in the scan chain is assigned with a value, and the values of all the flip-flops form a p-bit offset Bias [ p-1: 0]。

8. The physically unclonable function architecture based on delay configurable oscillator of claim 7, characterized in that: if the reset level is the same as the offset enable level, an inverter is inserted and connected.