CN111651136B

CN111651136B - FIFO memory, electronic chip and terminal

Info

Publication number: CN111651136B
Application number: CN202010642490.0A
Authority: CN
Inventors: 汪文义
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2023-06-30
Anticipated expiration: 2040-07-06
Also published as: CN111651136A

Abstract

The embodiment of the application provides a FIFO memory, an electronic chip and a terminal, wherein the FIFO memory comprises: a forward pass control module; the forward direction through control module is used for controlling a forward direction through function to be in an open state or a closed state, wherein the forward direction through function refers to a function of transmitting data input from a data writing port to a data reading port; when the forward pass-through function is in an on state, if the register file of the FIFO memory is empty and there is a write operation corresponding to the write data port, data written from the write data port is transferred to the read data port. According to the technical scheme provided by the embodiment of the application, when the forward through control module controls the forward through function to be opened, if the register file of the FIFO memory is empty, the data written from the write data port is allowed to be directly transmitted to the read data port, so that the time delay between the write data and the read data when the register file is empty can be reduced, and the operation efficiency is improved.

Description

FIFO memory, electronic chip and terminal

Technical Field

The embodiments of the present disclosure relate to the field of memory technologies, and in particular, to a first-in first-out (First IN First Out, FIFO) memory, an electronic chip, and a terminal.

Background

FIFO memory is a buffer device used to collect data into a walking machine and store, an important component of an electronic chip.

In the related art, when the synchronous FIFO memory is in operation, data written by an external circuit from a write data port is stored in a register file (RegFile), and then the external circuit reads the written data from the register file through a read data port.

Disclosure of Invention

The embodiment of the application provides a FIFO memory, an electronic chip and a terminal. The technical scheme is as follows:

in one aspect, embodiments of the present application provide a FIFO memory, the FIFO memory comprising: the FIFO memory includes: the device comprises a forward straight-through control module, a write enabling port, a write data port, a read data port, an empty signal port, a write control module and a read pointer;

the forward straight-through control module is respectively and electrically connected with the write enabling port, the write data port, the read data port, the null signal port, the write control module and the read pointer;

the forward direction through control module is used for controlling a forward direction through function to be in an open state or a closed state, wherein the forward direction through function is a function of transmitting data input from the write data port to the read data port;

when the forward pass-through function is in the open state, if a register file of the FIFO memory is empty and there is a write operation corresponding to the write data port, data written from the write data port is transferred to the read data port.

In another aspect, an embodiment of the present application further provides an electronic chip, where the electronic chip includes the FIFO memory according to one aspect.

In yet another aspect, an embodiment of the present application provides a terminal, where the terminal includes an electronic chip as described in another aspect.

The technical scheme provided by the embodiment of the application can bring beneficial effects at least including:

by additionally arranging the forward through control module for controlling the opening or closing of the forward through function on the original structure of the FIFO memory, when the forward through control module controls the opening of the forward through function, if a register file of the FIFO memory is empty, the data written from a data writing port is allowed to be directly transmitted to a data reading port, the register file is not required to be written first and then read out, the time delay from the data writing to the data reading when the register file is empty can be reduced, and the operation efficiency is improved.

Drawings

Fig. 1 is a block diagram of a FIFO memory provided by the related art;

FIG. 2 is a timing diagram of the operation of a FIFO memory provided in the related art;

FIG. 3 is a block diagram of a FIFO memory provided in accordance with one embodiment of the present application;

FIG. 4 is a flowchart of the operation of the FIFO memory provided in one embodiment of the present application;

FIG. 5 is a block diagram of a FIFO memory according to another embodiment of the present application;

FIG. 6 is a flowchart of the operation of the FIFO memory provided in accordance with another embodiment of the present application;

fig. 7 is a block diagram of a terminal according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Referring to fig. 1, a schematic diagram of a FIFO memory according to the related art is shown.

The FIFO memory comprises a write control module, a register file, a read control module, a write pointer, a read pointer, a clock signal port, a write enable port, a write data port, a full signal port, a read enable port, a read data port and an empty signal port.

The write control module is electrically connected with the write enabling port, the write data port, the register file and the write pointer respectively.

The read control module is electrically connected with the read enabling port, the read data port, the register file and the read pointer respectively.

The register file is electrically connected with the full signal port, the empty signal port, the write pointer and the read pointer.

The write pointer is electrically connected with the full signal port and the empty signal port; the read pointer is electrically connected with the empty signal port and the full signal port.

The write control module is used for controlling the writing of the FIFO memory, such as controlling write enable signals, write addresses, whether the FIFO memory is full, whether the FIFO memory is wrongly written, and the like.

The read control module is used for controlling the reading of the FIFO memory, such as controlling a read enable signal, reading an address, whether the FIFO memory is empty or not, whether the FIFO memory is misplaced or not, and the like.

The register file is a register array formed by a plurality of registers and is used for temporarily storing data between a memory and a CPU operation unit.

The clock signal port is used for inputting a clock signal, and the clock signal is the basis of sequential logic and is used for determining when the state in the logic unit is updated, and the clock signal port is a signal quantity which has a fixed period and is irrelevant to operation. The frequency of the clock signal is set experimentally or empirically. In synchronous FIFIO memories, the clock signal plays the role of a timer, ensuring that the associated electronic components are operated synchronously, and can also be used to synchronize different processes of the CPU, changing the periodic output by rising or falling edges.

The write enable port is used for outputting a write enable signal, and when the write enable signal is in a high level, the write enable signal is valid and allows data to be written; when the write enable signal is low, the write enable signal is disabled and data is not allowed to be written.

The read enable port is used for outputting a read enable signal, and when the read enable signal is in a high level, the read enable signal is valid and allows data to be read; when the read enable signal is low, the read enable signal is disabled and the data is not allowed to be read.

The full signal port is used for outputting a full signal, and when the full signal is at a high level, the full signal is effective, and the full signal is effective for indicating that the register file is full and data cannot be written; when the full signal is low, the full signal is disabled, and the full signal is disabled to indicate that the register file is not full, and data is allowed to be written.

The empty signal port is used for outputting an empty signal, and when the empty signal is at a high level, the empty signal is valid, and the empty signal is valid and used for indicating that the register file is empty and cannot read data; when the null signal is low, the null signal is disabled, which is used to indicate that the register file is not null, allowing data to be read.

The read pointer is used to indicate the read address of the next data to be read. The write pointer is used to indicate the write address of the next data to be written. The FIFO memory determines whether the full/empty signal is valid by the read pointer and the write pointer. If the read address indicated by the read pointer is the same as the write address indicated by the write pointer, the null signal is valid; if the difference between the read address indicated by the read pointer and the write address indicated by the write pointer is the buffer depth, the full signal is valid. The cache depth refers to the amount of data that the register file can store.

The write data port is used for external circuitry to write data in the register file. The read data port is used for external circuitry to read data from the register file.

In the related art, since one clock cycle is required for both the read operation and the write operation, there is at least two clock cycle delay between the write and the read of the same data. Referring to FIG. 2 in combination, a schematic diagram of the operation of a FIFIO memory of the related art is shown. The FIFO memory writes three data of D0, D1, D2 respectively in 3-5 clock cycles, DO is allowed to be read out in 5 clock cycles, D1 is allowed to be read out in 6 clock cycles, and D2 is allowed to be read out in 7 clock cycles.

Based on this, the embodiment of the application provides a FIFO memory, by adding a forward pass control module for controlling the forward pass function to be opened or closed on the original structure of the FIFO memory, when the forward pass control module controls the forward pass function to be opened, if the register file of the FIFO memory is empty, the data written from the write data port is allowed to be directly transmitted to the read data port, without writing into the register file first and reading out from the register file, so that the time delay between writing data and reading out data when the register file is empty can be reduced, and the operation efficiency is improved.

Referring to fig. 3, a schematic diagram of a FIFO memory according to an embodiment of the application is shown.

The FIFO memory includes: the device comprises a forward straight-through control module, a write enabling port, a write data port, a read data port, a null signal port, a write control module and a read pointer. In addition, the FIFO memory includes a read control module, a register file, a full signal port, a read enable port, a clock signal port, a write pointer, and the like. The functions of the above modules, ports and pointers may refer to the embodiment shown in fig. 1, and are not described herein.

The forward straight-through control module is electrically connected with the write enabling port, the write data port, the read data port, the null signal port, the write control module and the read pointer respectively.

The forward direction through control module is used for controlling the forward direction through control function to be in an open state or a closed state. The forward pass-through function refers to a function of transmitting data input from a write data port to a read data port. When the forward pass-through function is in an on state, if the register file is empty and there is a write operation corresponding to the write data port, data written from the write data port is transferred to the read data port.

The register file being empty means that there is no data to be read out in the register file, when the register file is empty, the empty signal port outputs an empty signal of high level, and the read enable port outputs a read enable signal of low level. In the embodiment of the application, when the data to be read does not exist in the register file, the data written from the write data port is directly transmitted to the read data port, and compared with the prior art that the data is stored in the register file and then read from the register file, the time delay of at least two clock cycles can be saved, and the operation efficiency is improved.

Optionally, the forward pass control module includes a multiplexer. The multiplexer refers to a logic circuit which selects any corresponding path according to the requirement in the process of multiplexing data transmission. In the embodiment of the present application, the multiplexer is a data selector. A first switch is present between the first end of the multiplexer and the write data port and a second switch is present between the multiplexer and the register file. The second end of the multiplexer is electrically connected with the read data port. According to the structure of the multiplexer, it can be seen that in the embodiment of the present application, the multiplexer is used to select one path of data from the data written by the write data port and the data stored in the register file to transmit to the read data port.

When the forward pass function is in an open state, if the register file of the FIFO memory is empty, the first switch is in a closed state, the multiplexer is communicated with the write data port, and the multiplexer is not communicated with the register file. If there is a write operation corresponding to the write data port, the data written by the write operation is directly transmitted to the read data port, so that data pass-through is realized, the time delay from writing the data to reading the data can be reduced, and the operation efficiency is improved.

When the forward pass function is in an open state, if the register file of the FIFO memory is not empty, the first switch is in an open state, the second switch is in a closed state, the multiplexer is not communicated with the write data port, and the multiplexer is communicated with the register file. At this time, if there is a write operation corresponding to the write data port and there is a read operation corresponding to the read data port, the data written from the write data port is stored in the register file, and data read from the register file is selected. It should be noted that, the storage address of the data to be written is determined according to the write pointer, the storage address of the data to be read is determined according to the read pointer, and the data to be written and the data to be read are not the same data.

Optionally, when the forward pass function is in an on state, if the register file of the FIFO memory is empty and there is a write operation corresponding to the write data port, the empty signal output by the empty signal port is switched from a high level to a low level.

In the related art, when the register file is empty, the empty signal port outputs an empty signal of high level to indicate that the register file is empty and no further readout is allowed, and at this time, the read enable signal is of low level. In the embodiment of the application, when the register is empty but there is a write operation corresponding to the write data port, the high-level empty signal is pulled low to indicate that there is data that can be read out, and at this time, the external circuit directly reads the data written from the write data port from the read data port according to the low-level empty signal. Further, when the forward pass function is in an on state, if the register file of the FIFO memory is empty and there is a write operation corresponding to the write data port, the read enable signal output from the read enable port is switched from a low level to a high level.

Referring in conjunction to FIG. 4, a flowchart illustrating the operation of the FIFO memory according to one embodiment of the present application is shown. The workflow diagram includes the steps of:

step 401, register file is empty;

step 402, detecting whether there is a write operation to a write data port;

if so, step 403 is executed, and if not, execution is resumed from step 401;

step 403, switching the null signal output by the null signal port from high level to low level;

step 404, determining whether there is a read operation to the read data port;

if yes, go to step 405, if no, go to step 406.

Step 405, completing a read operation;

in step 406, the register file is not empty and the empty signal port outputs a low level empty signal.

Optionally, the forward pass function is in an on state or an off state, which is determined according to the operating scenario in which the FIFO memory is located. By the mode, the running mode of the FIFO memory can be flexibly adapted to different scenes.

Illustratively, when the running scenario in which the FIFO memory is located is a delay sensitive scenario, the forward pass-through function is in an on state; when the running scene of the FIFO memory is not a delay sensitive scene, the forward direction through function is in a closed state. The time delay sensitive scene refers to a scene requiring a time delay less than a preset threshold, which is set according to experiments or experience, which is not limited in the embodiment of the present application.

In summary, according to the technical scheme provided by the embodiment of the application, the forward through control module for controlling the forward through function to be opened or closed is additionally arranged on the original structure of the FIFO memory, and when the forward through control module controls the forward through function to be opened, if the register file of the FIFO memory is empty, the data written from the write data port is allowed to be directly transmitted to the read data port, the register file is not required to be written first and then read from the register file, so that the time delay between the write data and the read data when the register file is empty can be reduced, and the operation efficiency is improved.

Referring to fig. 5 in combination, a schematic diagram of a FIFO memory according to another embodiment of the application is shown. Based on the FIFO memory provided based on the embodiment shown in fig. 3, the FIFO memory further comprises a reverse pass control module, a full signal port, a read enable port, and a write pointer.

The reverse straight-through control module is electrically connected with the full signal port, the read enabling port and the write pointer respectively.

The reverse through control module is used for controlling the reverse through function to be in an open state or a closed state. The reverse pass-through function refers to a function that allows a read operation to be performed on a read data port and a write operation to be performed on a write data port in the same clock cycle when the register file is full.

The register file being full means that the data is not allowed to be rewritten in the register file, and when the register file is full, the full signal port outputs a high-level full signal, and the write enable port outputs a low-level write enable signal. In the embodiment of the present application, when the register file is full, if the FIFO memory receives a read operation corresponding to the read data port, a write operation corresponding to the write data port is allowed to be performed on the FIFO memory, so that the situation that the write operation is not allowed to be performed on the FIFO memory when the register file is full is avoided, and more data is allowed to be written in.

Alternatively, when the reverse pass-through function is in an on state, if there is a read operation corresponding to the read data port, the full signal output from the full signal port is switched from a high level to a low level.

In the related art, when the register file is full, the full signal port outputs a high-level full signal to indicate that the register file is full and no re-writing is allowed, and the write enable signal is low. In the embodiment of the present application, when the register is full, if there is a read operation corresponding to the read data port, the high full signal is pulled low to indicate that the write data is allowed, and at this time, the external circuit writes the data in the register file according to the low full signal. Further, when the reverse pass function is in an on state, if the register file of the FIFO memory is full and there is a read operation corresponding to the read data port, the write enable signal output from the write enable port is switched from a low level to a high level.

Referring in conjunction to FIG. 6, a flowchart illustrating the operation of the FIFO memory according to one embodiment of the present application is shown. The workflow diagram includes the steps of:

step 601, register file is full;

step 602, judging whether a read operation to a read data port exists;

if yes, go to step 603, if not, resume execution from step 601;

step 603, switching the full signal output by the full signal port from high level to low level;

step 604, determining whether there is a write operation to the write data port;

if yes, go to step 605, if no, go to step 606.

Step 605, the write operation is completed;

in step 606, the register file is not full and the full signal port outputs a low full signal.

Optionally, the reverse pass function is in an on state or an off state, which is determined according to an operation scenario in which the FIFO memory is located. Illustratively, when the running scene in which the FIFO memory is located is an area-sensitive scene, the reverse pass-through function is in an on state; when the running scene of the FIFO memory is not an area sensitive scene, the reverse straight-through function is in a closed state. The area sensitive scene refers to a scene in which the amount of data to be written is greater than a preset amount. The preset number is set according to experiments or experience, and the embodiment of the present application is not limited thereto.

In summary, according to the technical solution provided in the embodiments of the present application, a reverse pass-through control module for controlling the opening or closing of the reverse pass-through function is additionally provided on the original structure of the FIFO memory, where the reverse pass-through control module is electrically connected to the full signal port and the read enable port, respectively, and when the reverse pass-through function is opened, if the register file of the FIFO memory is full, the write operation is allowed to be performed on the write data port and the read operation is allowed to be performed on the read data port in the same clock cycle, so that the register file can write more data.

The embodiment of the application also provides a FIFO memory, which comprises a reverse straight-through control module, a full signal port and a write enabling port;

the reverse straight-through control module is electrically connected with the full signal port and the write enabling port respectively.

The reverse pass-through control module is used for controlling a reverse pass-through function to be in an open state or a closed state, wherein the reverse pass-through function is a function which allows writing operation to be performed on a write data port and reading operation to be performed on a read data port in the same clock cycle when a register file is full.

The embodiment of the application also provides an electronic chip, which comprises the FIFO memory shown in fig. 3 or the FIFO memory shown in fig. 5.

The embodiment of the application also provides a terminal, which comprises an electronic chip, wherein the electronic chip comprises the FIFO memory shown in figure 3 or the FIFO memory shown in figure 5.

Fig. 7 shows a block diagram of a terminal 700 according to an exemplary embodiment of the present application. The terminal 700 may be: smart phones, tablet computers, MP3 players, MP4 players, notebook computers or desktop computers. Terminal 700 may also be referred to by other names of user devices, portable terminals, laptop terminals, desktop terminals, etc.

In general, the terminal 700 includes: a processor 701 and a memory 702.

Processor 701 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 701 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 701 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 701 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content required to be displayed by the display screen.

Memory 702 may include one or more computer-readable storage media, which may be non-transitory. The memory 702 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 702 is used to store a computer program for execution by processor 701 to implement the song playing methods provided by the method embodiments in the present application.

In some embodiments, the terminal 700 may further optionally include: a peripheral interface 703 and at least one peripheral. The processor 701, the memory 702, and the peripheral interface 703 may be connected by a bus or signal lines. The individual peripheral devices may be connected to the peripheral device interface 703 via buses, signal lines or a circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 704, touch display 705, camera 706, audio circuitry 707, positioning component 708, and power supply 709.

A peripheral interface 703 may be used to connect at least one Input/Output (I/O) related peripheral to the processor 701 and memory 702. In some embodiments, the processor 701, memory 702, and peripheral interface 703 are integrated on the same chip or circuit board; in some other embodiments, either or both of the processor 701, the memory 702, and the peripheral interface 703 may be implemented on separate chips or circuit boards, which is not limited in this embodiment.

The Radio Frequency circuit 704 is configured to receive and transmit Radio Frequency (RF) signals, also known as electromagnetic signals. The radio frequency circuitry 704 communicates with a communication network and other communication devices via electromagnetic signals. The radio frequency circuit 704 converts an electrical signal into an electromagnetic signal for transmission, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 704 includes: antenna systems, RF transceivers, one or more amplifiers, tuners, oscillators, digital signal processors, codec chipsets, subscriber identity module cards, and so forth. The radio frequency circuitry 704 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: the world wide web, metropolitan area networks, intranets, generation mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and/or wireless fidelity (Wireless Fidelity, wiFi) networks. In some embodiments, the radio frequency circuitry 704 may also include circuitry related to near field wireless communication (Near Field Communication, NFC), which is not limited in this application.

The display screen 705 is used to display a User Interface (UI). The UI may include graphics, text, icons, video, and any combination thereof. When the display 705 is a touch display, the display 705 also has the ability to collect touch signals at or above the surface of the display 705. The touch signal may be input to the processor 701 as a control signal for processing. At this time, the display 705 may also be used to provide virtual buttons and/or virtual keyboards, also referred to as soft buttons and/or soft keyboards. In some embodiments, the display 705 may be one, providing a front panel of the terminal 700; in other embodiments, the display 705 may be at least two, respectively disposed on different surfaces of the terminal 700 or in a folded design; in still other embodiments, the display 705 may be a flexible display disposed on a curved surface or a folded surface of the terminal 700. Even more, the display 705 may be arranged in a non-rectangular irregular pattern, i.e. a shaped screen. The display 705 may be made of a liquid crystal display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (OLED), or other materials.

The camera assembly 706 is used to capture images or video. Optionally, the camera assembly 706 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal and the rear camera is disposed on the rear surface of the terminal. In some embodiments, the at least two rear cameras are any one of a main camera, a depth camera, a wide-angle camera and a tele camera, so as to realize that the main camera and the depth camera are fused to realize a background blurring function, and the main camera and the wide-angle camera are fused to realize a panoramic shooting and Virtual Reality (VR) shooting function or other fusion shooting functions. In some embodiments, camera assembly 706 may also include a flash. The flash lamp can be a single-color temperature flash lamp or a double-color temperature flash lamp. The dual-color temperature flash lamp refers to a combination of a warm light flash lamp and a cold light flash lamp, and can be used for light compensation under different color temperatures.

The audio circuit 707 may include a microphone and a speaker. The microphone is used for collecting sound waves of users and environments, converting the sound waves into electric signals, and inputting the electric signals to the processor 701 for processing, or inputting the electric signals to the radio frequency circuit 704 for voice communication. For the purpose of stereo acquisition or noise reduction, a plurality of microphones may be respectively disposed at different portions of the terminal 700. The microphone may also be an array microphone or an omni-directional pickup microphone. The speaker is used to convert electrical signals from the processor 701 or the radio frequency circuit 704 into sound waves. The speaker may be a conventional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, not only the electric signal can be converted into a sound wave audible to humans, but also the electric signal can be converted into a sound wave inaudible to humans for ranging and other purposes. In some embodiments, the audio circuit 707 may also include a headphone jack.

The positioning component 708 is operative to position the current geographic location of the terminal 700 to enable navigation or location based services (Location Based Service, LBS). The positioning component 708 may be a positioning component based on the U.S. global positioning system (Global Positioning System, GPS), the chinese beidou system, or the russian galileo system.

A power supply 709 is used to power the various components in the terminal 700. The power supply 709 may be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 709 includes a rechargeable battery, the rechargeable battery may be a wired rechargeable battery or a wireless rechargeable battery. The wired rechargeable battery is a battery charged through a wired line, and the wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery may also be used to support fast charge technology.

In some embodiments, the terminal 700 further includes one or more sensors 77. The one or more sensors 77 include, but are not limited to: acceleration sensor 711, gyroscope sensor 712, pressure sensor 713, fingerprint sensor 714, optical sensor 715, and proximity sensor 717.

The acceleration sensor 711 can detect the magnitudes of accelerations on three coordinate axes of the coordinate system established with the terminal 700. For example, the acceleration sensor 711 may be used to detect the components of the gravitational acceleration in three coordinate axes. The processor 701 may control the touch display 707 to display a user interface in a landscape view or a portrait view based on the gravitational acceleration signal acquired by the acceleration sensor 711. The acceleration sensor 711 may also be used for the acquisition of motion data of a game or a user.

The gyro sensor 712 may detect a body direction and a rotation angle of the terminal 700, and the gyro sensor 712 may collect a 3D motion of the user to the terminal 700 in cooperation with the acceleration sensor 711. The processor 701 may implement the following functions based on the data collected by the gyro sensor 712: motion sensing (e.g., changing UI according to a tilting operation by a user), image stabilization at shooting, game control, and inertial navigation.

The pressure sensor 713 may be disposed at a side frame of the terminal 700 and/or a lower layer of the touch display 707. When the pressure sensor 713 is disposed at a side frame of the terminal 700, a grip signal of the user to the terminal 700 may be detected, and the processor 701 performs left-right hand recognition or quick operation according to the grip signal collected by the pressure sensor 713. When the pressure sensor 713 is disposed at the lower layer of the touch display screen 707, the processor 701 performs control of the operability control on the UI interface according to the pressure operation of the user on the touch display screen 707. The operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

The fingerprint sensor 714 is used to collect a fingerprint of the user, and the processor 701 identifies the identity of the user according to the fingerprint collected by the fingerprint sensor 714, or the fingerprint sensor 714 identifies the identity of the user according to the collected fingerprint. Upon recognizing that the user's identity is a trusted identity, the processor 701 authorizes the user to perform relevant sensitive operations including unlocking the screen, viewing encrypted information, downloading software, paying for and changing settings, etc. The fingerprint sensor 714 may be provided on the front, back or side of the terminal 700. When a physical key or vendor Logo is provided on the terminal 700, the fingerprint sensor 714 may be integrated with the physical key or vendor Logo.

The optical sensor 715 is used to collect the ambient light intensity. In one embodiment, the processor 701 may control the display brightness of the touch display 707 based on the ambient light intensity collected by the optical sensor 715. Specifically, when the intensity of the ambient light is high, the display brightness of the touch display screen 707 is turned high; when the ambient light intensity is low, the display brightness of the touch display screen 707 is turned down. In another embodiment, the processor 701 may also dynamically adjust the photographing parameters of the camera assembly 707 based on the ambient light intensity collected by the optical sensor 715.

A proximity sensor 717, also referred to as a distance sensor, is typically provided on the front panel of the terminal 700. The proximity sensor 717 is used to collect the distance between the user and the front of the terminal 700. In one embodiment, when the proximity sensor 717 detects that the distance between the user and the front surface of the terminal 700 gradually decreases, the processor 701 controls the touch display 707 to switch from the bright screen state to the off screen state; when the proximity sensor 717 detects that the distance between the user and the front surface of the terminal 700 gradually increases, the touch display 707 is controlled by the processor 701 to switch from the off-screen state to the on-screen state.

Those skilled in the art will appreciate that the structure shown in fig. 7 is not limiting of the terminal 700 and may include more or fewer components than shown, or may combine certain components, or may employ a different arrangement of components.

It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The foregoing description of the exemplary embodiments of the present application is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and scope of the invention.

Claims

1. A first-in first-out FIFO memory, the FIFO memory comprising: the device comprises a forward straight-through control module, a write enabling port, a write data port, a read data port, an empty signal port, a write control module and a read pointer;

the forward direction through control module is used for controlling a forward direction through function to be in an open state or a closed state, wherein the forward direction through function is a function of transmitting data input from the write data port to the read data port; when the running scene of the FIFO memory is a time delay sensitive scene, the forward direction through function is in the open state; when the running scene of the FIFO memory is not a time delay sensitive scene, the forward direction through function is in the closed state; wherein the time delay sensitive scene is a scene requiring a time delay less than a preset threshold;

2. The FIFO memory of claim 1, wherein the forward pass control module comprises a multiplexer having a first switch between a first end and the write data port, a second end electrically connected to the read data port;

when the forward pass function is in the open state, if the register file is empty, the first switch is in the closed state, and the multiplexer is communicated with the write data port.

3. The FIFO memory of claim 2, wherein when the forward pass function is in the on state, the first switch is in an on state if the register file is not empty, the multiplexer not communicating with the write data port.

4. A FIFO memory as in claim 3, wherein a second switch is present between the first end of the multiplexer and the register file;

when the forward pass function is in the open state, if the register file is not empty, the second switch is in the closed state, and the multiplexer is communicated with the register file.

5. The FIFO memory according to claim 1, wherein when the forward pass-through function is in the on state, if the register file is empty and there is a write operation corresponding to the write data port, the empty signal output from the empty signal port is switched from a high level to a low level.

6. The FIFO memory according to any one of claims 1 to 5, further comprising a reverse pass control module, a full signal port, a read enable port, a write pointer;

the reverse straight-through control module is respectively and electrically connected with the full signal port, the read enabling port and the write pointer;

the reverse pass-through control module is used for controlling a reverse pass-through function to be in an open state or a closed state, wherein the reverse pass-through function is a function which allows write operation to be performed on the write data port and read operation to be performed on the read data port in the same clock cycle when the register file is full.

7. The FIFO memory of claim 6, wherein when the reverse pass-through function is in the open state and the register file is full, the full signal output by the full signal port is switched from a high level to a low level if there is a read operation corresponding to the read data port.

8. The FIFO memory of claim 6, wherein the reverse pass-through function is in the on state or the off state is determined according to an operating scenario in which the FIFO memory is located.

9. The FIFO memory of claim 8, wherein the memory is configured to store the data,

when the running scene of the FIFO memory is an area sensitive scene, the reverse straight-through function is in the open state;

when the running scene of the FIFO memory is not an area sensitive scene, the reverse straight-through function is in the closed state;

the area sensitive scenes are scenes in which the number of data to be written is larger than the preset number.

10. An electronic chip comprising a FIFO memory according to any one of claims 1 to 9.

11. A terminal comprising the electronic chip of claim 10.