CN111628783A - EG-LDPC decoder - Google Patents
EG-LDPC decoder Download PDFInfo
- Publication number
- CN111628783A CN111628783A CN201910145843.3A CN201910145843A CN111628783A CN 111628783 A CN111628783 A CN 111628783A CN 201910145843 A CN201910145843 A CN 201910145843A CN 111628783 A CN111628783 A CN 111628783A
- Authority
- CN
- China
- Prior art keywords
- data
- matrix
- arithmetic unit
- memory
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 134
- 239000013598 vector Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 10
- 125000004122 cyclic group Chemical group 0.000 claims description 19
- 238000004364 calculation method Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 2
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Algebra (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Error Detection And Correction (AREA)
Abstract
The invention relates to an EG-LDPC decoder and a method thereof, wherein the EG-LDPC decoder comprises: the device comprises a controller, a shift operator, a data memory group, an H matrix memory, a receiving memory, a data operator and a result operator. The shift arithmetic unit is accessed to original data to form a data circulation matrix and input the data circulation matrix to the data memory; the H matrix memory stores the position of 1 in the H matrix component vector, and the output of the H matrix memory is connected to the address bit of the data memory group; the output end of the data memory group is connected with the input end of the data arithmetic unit, the received data vectors are subjected to exclusive OR, and the output end of the data arithmetic unit is connected with the result arithmetic unit; the result arithmetic unit adds the XOR result of all the H matrix partial vectors received and corrects the error bit, and the output end of the result arithmetic unit is accessed to the receiving memory. The invention has the advantages that: resources occupied by storage are reduced; the decoding efficiency of the decoder is improved.
Description
Technical Field
The invention relates to a decoder and a method of an European geometric low-density parity check (EG-LDPC) code.
Background
Low Density Parity Check Code (LDPC) has been widely studied and applied as a good Code that can approach the shannon limit. To date, LDPC has been determined to be applied to long code block coding schemes for 5G mobile broadband service data information. The core idea of LDPC is to spread the information into a sparse vector space to achieve good decoding performance.
At the beginning of the LDPC discovery (Gallager, 1963), the current computing devices were neglected because the computing devices were too large to bear enough load, and re-entered into human sight after 30 years (Tanner, 1981) (MacKay, 1999), found good coding and decoding performance. Constructing a random sparse matrix can well approach the Shannon limit during decoding, but the hardware implementation is more complex due to the randomness of the matrix. Structured LDPC can reduce hardware complexity relative to random LDPC. Among them, the Euclidean Geometry low density parity check code (EG-LDPC) (y. Kou and s. Lin, 2001) is a method of designing an LDPC using lines and dots based on Euclidean Geometry over a finite field. The generation matrix and the check matrix of the EG-LDPC have algebraic structures, 4 loops cannot be generated by constructed code words, the realization complexity is reduced, and the realization of hardware is facilitated. However, the H matrix of EG-LDPC has heavy rows and columns and is not suitable for the use of belief propagation algorithm. And a bit-flipping (BF) algorithm (j.h. Kim, 2010) (j.t. Zhang, 2007) and a Majority-Logic Decoding (MLD) algorithm (a, Thangaraj, 2002) (t.m.n. Ngatched, 2011) (r. pelro, 2013) (h.q. Chen, 2015) can well utilize the advantages of EG-LDPC to detect and correct errors.
The I-type 2-dimensional EG-LDPC can be decoded as a large number of logics, when the code words are decoded, the check on the code word sequence can be completed only by circularly shifting the sub-matrix of the H matrix of the EG-LDPC, and therefore the hardware is simple to implement. But for a code length of
The code word needs to be circularly shifted to the sub-matrix
Second, multiplexing of single component vectors in H matrix
Secondly; in that
In the H matrix of order, 1 has information value and 0 does not have information value, while the H matrix of EG-LDPC is sparse matrix, and each component of the sparse matrixThe number of 1's in the vector is only
Therefore, cyclic shifts with a majority of positions 0 in the sub-matrix of the entire H matrix are not needed. The invention designs the EG-LDPC decoder, and the calculation result shows that the resources occupied by storage are reduced, and the decoding efficiency is improved.
Disclosure of Invention
The invention provides an EG-LDPC decoder, aiming at reducing the storage occupation resources of the decoder and increasing the decoding efficiency of the decoder.
The invention is realized by the following steps: an EG-LDPC decoder comprising: the device comprises a controller, a shift operator, a data memory group, an H matrix memory, a receiving memory, a data operator and a result operator.
The controller generates RAM read-in and read-out states and addresses of the data memory group, and RAM read-in and read-out addresses of the H matrix memory and the receiving memory.
The shift arithmetic unit is accessed to original data to form a data circulation matrix and input the data circulation matrix to the data memory group; the output end of the H matrix memory is connected to the address bit of the data memory group; the output end of the data memory group is connected with the input end of the data arithmetic unit; the output end of the data arithmetic unit is connected to the input end of the result arithmetic unit; and the output end of the result arithmetic unit is connected to the input end of the receiving memory.
The data memory group comprises 2 RAMs; the H matrix memory stores the position of 1 in the H matrix component vector; the receive memory receives the final correction data.
The shift operator includes
A D flip-flop; the data arithmetic unit comprises
An exclusive OR unit for the digital signal to be processed,
a D flip-flop; the result arithmetic unit includes
An adder is provided, which is used for adding the adder,
a D trigger is arranged on the first side of the circuit,
and an exclusive OR.
The EG-LDPC decoding method comprises the following steps.
In the first step, the controller generates the read-in and read-out state and address of RAM in the data memory group, and the data arithmetic unit carries out
Sub-cyclic shift formation
Inputting the order data circulation matrix into a RAM of a data memory group, and replacing the circulation shift of the H matrix submatrix by the data circulation matrix; the shift result is input to the data memory group according to the address sequence, the read-in and read-out states of 2 RAMs in the data memory group should appear alternately, and when 1 RAM is in the read-out state, the current data cyclic matrix is ready; the other RAM is in the read state, which receives the circulant matrix for the next data vector.
And secondly, the controller generates a read address of the RAM of the H-matrix memory, and the output vector of the read address is accessed to the address bit of the RAM in the data memory group to read corresponding data. Wherein the H matrix sub-matrix component vector of EG-LDPC should satisfy:
the first of each vector
The values of the positions are all 1; to pair
No more than 1 vector with a median of 1 in its position.
After determining the submatrix of the H matrix, the RAM of the H matrix memory only stores the position of each component vector as 1, namely each position in the RAM
Each address describes the position of all 1's of a component vector.
The output of the H-matrix memory RAM generates the read address of the data memory bank RAM, and the output vector of the corresponding data circular matrix can be expressed as 1 circular shift in the sub-vector of the H-matrix sub-matrix
And sequentially outputting the bit calculation corresponding to the data vector.
Third, the XOR operation of the data circulant matrix output vectors by the data operator should be received
And when the data vectors are matched, completing one vector operation. The data arithmetic unit outputs the arithmetic result to the result arithmetic unit and initializes the result arithmetic unit.
Fourthly, the controller generates the read-in address of the receiving memory and the result arithmetic unit uses
An adder adds the received data at the corresponding position when receiving
And when the data vectors are matched, all the component calculation is completed.
Addition result
Indicating that the corresponding bit position is in error. On the contrary, when
And when the bit is correct, the corresponding bit is indicated to be correct. Wherein
And adding the sum of exclusive OR and data vector of all the component vectors of the H matrix submatrix.
And judging the error bit position, the exclusive OR of the error position bit and 1 and the exclusive OR of the error position bit and 0 according to the addition result and the vector quantity stored in the H matrix in advance, finishing data correction, and inputting the corrected data vector quantity into a receiving memory.
The invention has the advantages that: the position of 1 in the H matrix is stored in place of the H matrix sub-matrix. For EG-LDPC, when
In time, the method can reduce the resource occupied by storage.
The use of a data rotation matrix instead of a rotation of the H matrix components reduces the resources occupied by storage.
The component of the data cyclic matrix represents the cyclic shift of the corresponding position bit in the component of the H matrix
The bit value read the second time; the memory depth in the RAM of the H-matrix memory is
Sequential calling of H-matrix memory RAM
Decoding can be completed for each address. For a clock frequency of N MHz, the throughput can reach N Mbit/s, as shown in equation 5.
Wherein
In order to be able to measure the clock frequency,
is the length of the code word or words,
the clock cycles required to complete the decoding.
Compared with the traditional large number logic decoding which uses the data vector and the H matrix component vector for decoding to realize the throughput of N Mbit/s, the method needs to realize the N Mbit/s
The RAMs form an H-matrix memory bank. Therefore, the invention also improves the decoding efficiency.
Drawings
For a more clear description of the objects and advantages of the invention, reference is now made to the following examples, which are provided for illustration purposes and which are to be construed as being included in the appended claims.
FIG. 1 is a schematic circuit diagram of an EG-LDPC decoder according to the present invention;
FIG. 2 is a diagram of a conventional one-step majority logic decoding scheme.
Detailed Description
Referring to fig. 1, a preferred embodiment of an EG-LDPC decoder according to the present invention comprises: the device comprises a controller, a shift operator, a data memory group, an H matrix memory, a receiving memory, a data operator and a result operator. The shift arithmetic unit is accessed to the original data to form
The order data circulant matrix is input to the data memory bank,
is the data length; the H matrix memory stores the position of 1 in the H matrix component vector, and the storage width of the RAM of the H matrix memory is
Storage depth of
. The H matrix memory outputs address bits connected to the data memory; the output end of the data memory group is connected with the input end of the data arithmetic unit, and the data length is
The output end of the output end is connected to the input end of the result arithmetic unit; the result arithmetic unit carries out addition operation on the XOR result of all the partial vectors, judges and corrects the error bit position, and the corrected result is output to the input end of the receiving memory.
The controller generates RAM read-in and read-out states and addresses of the data memory group, and RAM read-in and read-out addresses of the H matrix memory and the receiving memory.
The data memory group comprises 2 RAMs; the H matrix memory stores the position of 1 in the H matrix vector in the form of an address; the receive memory receives the final correction data.
Wherein the data circulant matrix of the data memory bank is as shown in equation 6, wherein
Is the data bit.
The shift operator includes
A D flip-flop; the data arithmetic unit comprises
An exclusive OR unit for the digital signal to be processed,
a D flip-flop; the result arithmetic unit includes
An adder is provided, which is used for adding the adder,
a D trigger is arranged on the first side of the circuit,
and an exclusive OR.
The principle of the conventional one-step large number logic decoding algorithm is described as follows with reference to fig. 2.
In the code word length of
Can be found in the H matrix of EG-LDPC
The component vectors form a submatrix.
The first of each vector
The values of the positions are all 1; to pair
No more than 1 vector with a median of 1 in its position.
The H matrix submatrix is shown in equation 7.
Assuming the total number of errors in the erroneous codeword
When it comes to
When the position is wrong, the above-mentioned steps are performed
After XOR-summing of the personal vector and the code word, the added value
(ii) a Otherwise the first step
The bit is correct and the bit is correct,
. Since the H matrix of EG-LDPC is a circulant matrix, the above will be described
Cyclic shift of vector
Once calculated, decoding can be accomplished through the data vector.
With reference to fig. 2, to reduce the memory occupation resources of the decoder, the decoding efficiency is increased.
Firstly, the invention stores the position of 1 in the H matrix vector in the form of address.
Wherein the storage of H matrix component vector by memory is converted into corresponding 1 address in component vector for storage, and the resource occupied by each component vector is stored by
Become into
Wherein
The number of bits required for the memory address.
So when
In time, the method can reduce the resource occupied by storage.
And secondly, the invention replaces the cyclic shift of the component vector of the H matrix sub-matrix with the data cyclic matrix.
In which the H matrix is a sub-matrix
The cyclic shift of the fractional vectors may correspond to the cyclic shift of the codeword, with equation 6, equation 7, and equation 8, with a shift of the H matrix fractional vector one bit to the right being equivalent to a shift of the data circulant matrix one bit to the left.
Further, the calculation of the single component vector of the data circulant matrix and the H-submatrix can be expressed as formula 9, which can be understood as cyclic shift of the component vector
And (5) carrying out check calculation on the data vector.
Further, because the data circulant matrices are symmetric matrices, the vector component of each data circulant matrix can be understood as cyclic shift of the data bit and the data vector in the vector component of the H matrix submatrix
And outputting the calculated sequence of the corresponding bit after the next time.
The steps of an EG-LDPC decoding method are as follows.
In the first step, the controller generates the read-in and read-out state and address of RAM in the data memory group, and the data arithmetic unit carries out
Sub-cyclic shift formation
Inputting the order data circulation matrix into a RAM of a data memory group, and replacing the circulation shift of the H matrix submatrix by the data circulation matrix; the shift results are input to the data memory groups in the order of addresses, 2 of the data memory groupsThe read-in and read-out states of the RAMs should appear alternately, and when 1 RAM is in the read-out state, the current data cycle matrix is prepared; the other RAM is in the read state, which receives the circulant matrix for the next data vector.
And secondly, the controller generates a read address of the RAM of the H-matrix memory, and the output vector of the read address is accessed to the address bit of the RAM in the data memory group to read corresponding data. Wherein the H matrix sub-matrix components should satisfy:
the first of each vector
The values of the positions are all 1; to pair
No more than 1 vector with a median of 1 in its position.
After determining the submatrix of the H matrix, the RAM of the H matrix memory only stores the position of each component vector as 1, namely each position in the RAM
Each address describes the position of a 1 in a component vector.
The output of the RAM of the H-matrix memory generates the read address of the data memory bank RAM, and the output vector of the corresponding data circulation matrix can be expressed as 1 circulation shift in the component vector of the H-matrix sub-matrix
And sequentially outputting the bit calculation corresponding to the data vector.
Third, the XOR operation of the data circulant matrix output by the data operator should be received
And when the data vectors are matched, completing one vector operation. The data operator outputs the result to the result operator and returns to zero.
Fourthly, the controller generates the read-in address of the receiving memory and the result arithmetic unit uses
An adder adds the received data at the corresponding position when receiving
And when the data vectors are matched, all the component calculation is completed.
Addition result
Indicating that the corresponding bit position is in error. Otherwise, the reverse is carried out
And when the bit is correct, the corresponding bit is indicated to be correct. Wherein
And adding the sum of exclusive OR and data vector of all the component vectors of the H matrix submatrix.
And judging the error bit position, the exclusive OR of the error position bit and 1 and the exclusive OR of the error position bit and 0 according to the addition result and the vector quantity stored in the H matrix in advance, finishing data correction, and inputting the corrected data vector quantity into a receiving memory.
In summary, the EG-LDPC decoder of the present invention uses the position of 1 in the stored H matrix instead of the H matrix sub-matrix; replacing cyclic shifts of the H matrix components with a data cyclic matrix; calling in H-matrix memory
Decoding can be completed by each address, so that resources occupied by storage are reduced, and decoding efficiency is improved.
The above detailed description of the embodiments is intended to be illustrative only and is not intended to be limiting, as various changes in form and detail can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.
Claims (9)
1. An EG-LDPC decoder characterized by: the device comprises a controller, a shift arithmetic unit, a data memory group, an H matrix memory, a receiving memory, a data arithmetic unit and a result arithmetic unit; the shift arithmetic unit is accessed to original data to form a data circulation matrix and input the data circulation matrix to the data memory group; the output end of the H matrix memory is connected to the address bit of the data memory; the output end of the data memory group is connected with the input end of the data arithmetic unit; the output end of the data arithmetic unit is connected to the input end of the result arithmetic unit; and the output end of the result arithmetic unit is connected to the input end of the receiving memory.
2. The decoder of claim 1, wherein: the controller generates read-in and read-out states and addresses of the data memory group RAM, and read-in and read-out addresses of the RAM of the H-matrix memory and the receiving memory.
3. The decoder of claim 1, wherein: the data memory group comprises 2 RAMs; the H matrix memory stores the position of 1 in the H matrix component vector; the receive memory receives the final correction data.
4. The decoder of claim 1, wherein: the shift operator includes
A D flip-flop; the data arithmetic unit comprises
An exclusive OR unit for the digital signal to be processed,
a D flip-flop; the result arithmetic unit includes
An adder is provided, which is used for adding the adder,
a D trigger is arranged on the first side of the circuit,
an exclusive OR unit for the digital signal to be processed,
is the data length.
5. Method for decoding corresponding to the decoder according to claim 1, characterized in that an encoder according to any of claims 1-4 is used, said method comprising the steps of:
the controller generates a read-in state and an address of an RAM in the data memory group, the shift arithmetic unit carries out cyclic shift on received original data and generates a corresponding address, and a shift result is input into the data memory group according to the address sequence;
the controller generates an H matrix memory RAM reading address, and the H matrix memory outputs address bits of the RAM in the access data memory group to read corresponding data;
the data arithmetic unit performs XOR operation on the vectors output by the data memory group, and the data arithmetic unit receives
When the data vector is generated, one-time vector division operation is completed, and the data arithmetic unit outputs the result to the result arithmetic unit and initializes the result;
the controller generates a read-in address of the receiving memory, the result arithmetic unit adds the values of all the partial vectors of the H matrix, judges and corrects the error bit and outputs the error bit to the receiving memory.
6. The encoder of claim 5, wherein:
the step 1) is specifically as follows: data arithmetic unit performs
Sub-cyclic shift formation
Inputting the order data circulation matrix into a RAM of a data memory group, and replacing the circulation shift of the H matrix submatrix by the data circulation matrix; the read-in and read-out states of 2 RAMs in the data memory group should appear alternately, and when 1 RAM is in the read-out state, the current data cycle matrix is ready; the other RAM is in read-in state and receives the circulant matrix of the next data vector. Wherein the data circulant matrix of the data memory bank is as shown in equation 2:
wherein
Is the data bit.
7. The encoder of claim 5, wherein: the step 2) is specifically as follows: the H matrix submatrix for constructing the EG-LDPC is shown as formula 2:
after determining the submatrices of the H matrix, the H matrix memory RAM only stores the position of each component vector as 1, namely each position in the RAM
Each address describes the position of all 1's in a component vector.
8. The encoder of claim 5, wherein: the step 3) is specifically as follows: of H-matrix sub-matrices
The cyclic shift of the fractional vectors may correspond to a cyclic shift of the codeword, and a shift of the H matrix vector by one bit to the right is equivalent to a shift of the data cyclic matrix by one bit to the left, according to equation 1, equation 2, or equation 3:
further, the calculation of the single component vector of the data circulant matrix and the H-submatrix can be expressed as equation 4, which represents the cyclic shift of the component vector
And (3) carrying out check calculation on the data vector:
further, the data circulant matrix is a symmetric matrix, and the vector of each data circulant matrix can be understood as: cyclic shift of check bit at corresponding position of component of H matrix submatrix
Sequentially outputting the bit calculation corresponding to the data vector;
further, in the component vector according to the H sub-matrix
1 position, taken out
And carrying out XOR on the vectors corresponding to the data cyclic matrix to complete the check operation of the vectors on all bits of the data vector.
9. The encoder of claim 5, wherein: the step 4) is specifically as follows: the result arithmetic unit receives the XOR sum of the partial vector and the data vectorThe result operator receives
The data bit is obtained by adding the data vectors at corresponding positions
Result of addition
，
Indicating that the corresponding bit position is in error, otherwise
Indicating a correct.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910145843.3A CN111628783A (en) | 2019-02-27 | 2019-02-27 | EG-LDPC decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910145843.3A CN111628783A (en) | 2019-02-27 | 2019-02-27 | EG-LDPC decoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111628783A true CN111628783A (en) | 2020-09-04 |
Family
ID=72260494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910145843.3A Pending CN111628783A (en) | 2019-02-27 | 2019-02-27 | EG-LDPC decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111628783A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113541863A (en) * | 2021-06-02 | 2021-10-22 | 香港中文大学（深圳） | Data encoding method, data decoding method, electronic device, and storage medium |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040199859A1 (en) * | 2002-02-28 | 2004-10-07 | Wataru Matsumoto | Ldpc code inspection matrix generation method and inspection matrix generation device |
| CN101106437A (en) * | 2007-08-08 | 2008-01-16 | 清华大学 | A decoding method for limited geometrical low density checksum code |
| AU2007237272A1 (en) * | 2007-11-30 | 2009-06-18 | Canon Kabushiki Kaisha | Reliable error detection and error correction encoding for very small block lengths |
| US20090265600A1 (en) * | 2005-08-10 | 2009-10-22 | Mitsubishi Electric Corporation | Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder |
| CN101707485A (en) * | 2009-02-03 | 2010-05-12 | 天津博微科技有限公司 | LDPC decoding method combining bit flipping (BF) and majority logic (MLG) |
| US20100199142A1 (en) * | 2007-04-13 | 2010-08-05 | University College Dublin, National University Of Ireland | Encoding scheme, and a decoding scheme using a series of ldpc codes based on finite inversive spaces |
| CN102075198A (en) * | 2011-01-11 | 2011-05-25 | 上海交通大学 | Quasi-cyclic low-density odd-even check convolution code coding-decoding system and coding-decoding method thereof |
| US20110307754A1 (en) * | 2006-09-18 | 2011-12-15 | Fengwen Sun | family of ldpc codes for video broadcasting applications |
| JP2016208309A (en) * | 2015-04-23 | 2016-12-08 | 三菱電機株式会社 | Error correction decoding device, reception device and error correction decoding method |
| CN209731214U (en) * | 2019-02-27 | 2019-12-03 | 西南科技大学 | A kind of EG-LDPC decoder |
-
2019
- 2019-02-27 CN CN201910145843.3A patent/CN111628783A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040199859A1 (en) * | 2002-02-28 | 2004-10-07 | Wataru Matsumoto | Ldpc code inspection matrix generation method and inspection matrix generation device |
| US20090265600A1 (en) * | 2005-08-10 | 2009-10-22 | Mitsubishi Electric Corporation | Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder |
| US20110307754A1 (en) * | 2006-09-18 | 2011-12-15 | Fengwen Sun | family of ldpc codes for video broadcasting applications |
| US20100199142A1 (en) * | 2007-04-13 | 2010-08-05 | University College Dublin, National University Of Ireland | Encoding scheme, and a decoding scheme using a series of ldpc codes based on finite inversive spaces |
| CN101106437A (en) * | 2007-08-08 | 2008-01-16 | 清华大学 | A decoding method for limited geometrical low density checksum code |
| AU2007237272A1 (en) * | 2007-11-30 | 2009-06-18 | Canon Kabushiki Kaisha | Reliable error detection and error correction encoding for very small block lengths |
| CN101707485A (en) * | 2009-02-03 | 2010-05-12 | 天津博微科技有限公司 | LDPC decoding method combining bit flipping (BF) and majority logic (MLG) |
| CN102075198A (en) * | 2011-01-11 | 2011-05-25 | 上海交通大学 | Quasi-cyclic low-density odd-even check convolution code coding-decoding system and coding-decoding method thereof |
| JP2016208309A (en) * | 2015-04-23 | 2016-12-08 | 三菱電機株式会社 | Error correction decoding device, reception device and error correction decoding method |
| CN209731214U (en) * | 2019-02-27 | 2019-12-03 | 西南科技大学 | A kind of EG-LDPC decoder |
Non-Patent Citations (3)
| Title |
|---|
| PEDRO REVIRIEGO等: "Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》, vol. 21, no. 1, 2 January 2012 (2012-01-02), pages 156 - 159, XP011482848, DOI: 10.1109/TVLSI.2011.2179681 * |
| 张士伟: "基于EG-LDPC码字构成及编解码实现", 《中国优秀硕士学位论文全文数据库信息科技辑》, no. 2, 15 February 2016 (2016-02-15), pages 136 - 122 * |
| 施宇根: "用于存储器加固的MC与LDPC研究与设计", 《中国优秀硕士学位论文全文数据库信息科技辑》, no. 9, 15 September 2019 (2019-09-15), pages 135 - 106 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113541863A (en) * | 2021-06-02 | 2021-10-22 | 香港中文大学（深圳） | Data encoding method, data decoding method, electronic device, and storage medium |
| CN113541863B (en) * | 2021-06-02 | 2024-01-09 | 香港中文大学（深圳） | Data encoding method, data decoding method, electronic device, and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7657816B2 (en) | Low-complexity hybrid LDPC code encoder | |
| JP5199463B2 (en) | Turbo LDPC decoding | |
| US7543212B2 (en) | Low-density parity-check (LDPC) encoder | |
| US7395494B2 (en) | Apparatus for encoding and decoding of low-density parity-check codes, and method thereof | |
| JP4516602B2 (en) | Data encoding and decoding method and apparatus | |
| JP4320418B2 (en) | Decoding device and receiving device | |
| US7716553B2 (en) | System and method for designing RS-based LDPC code decoder | |
| US7188297B2 (en) | Method and apparatus for encoding and decoding data | |
| EP2031759B1 (en) | Coding method and device for Quasi-Cyclic LDPC codes | |
| US20060036933A1 (en) | Method and apparatus for encoding and decoding data | |
| US20120317457A1 (en) | High-performance ecc decoder | |
| WO2004027616A1 (en) | Method and apparatus for encoding data | |
| WO2010000152A1 (en) | Method and device for burst correction | |
| JP2011514743A (en) | Method and system for detecting and correcting phased burst errors, erasures, symbol errors, and bit errors in received symbol sequences | |
| US9104589B1 (en) | Decoding vectors encoded with a linear block forward error correction code having a parity check matrix with multiple distinct pattern regions | |
| TWI540844B (en) | Double qc-ldpc code | |
| US10833704B1 (en) | Low-density parity check decoder using encoded no-operation instructions | |
| Liu et al. | A revolving iterative algorithm for decoding algebraic cyclic and quasi-cyclic LDPC codes | |
| CN108270518B (en) | Decoding method for decoding received information and related decoding device | |
| CN109935263B (en) | Encoding and decoding method of nonvolatile memory and storage system | |
| JP2008526086A (en) | Decoding apparatus and method using channel code | |
| WO2013189274A1 (en) | Circuit, encoder and method for parallel bch coding | |
| US20020083391A1 (en) | Method and apparatus for encoding a product code | |
| EP2309650B1 (en) | A systematic encoder with arbitrary parity positions | |
| CN111628783A (en) | EG-LDPC decoder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |