CN111625477B

CN111625477B - Processing method and device for read request for accessing erase block

Info

Publication number: CN111625477B
Application number: CN202010652412.9A
Authority: CN
Inventors: 袁戎; 路向峰
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2023-09-05
Anticipated expiration: 2036-07-01
Also published as: CN107562639B; CN111625477A; CN107562639A

Abstract

A method and apparatus for processing a read request to access an erase block are provided. The disclosed method for processing IO requests comprises the following steps: in response to receiving a first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; replaying the first read request if a physical block or block stripe containing a first physical address is in an erased state; wherein the first physical address recorded by the first FTL entry is obtained even if the first FTL entry is locked.

Description

Processing method and device for read request for accessing erase block

Technical Field

The present application relates to solid state storage devices, and more particularly to the handling of read requests to access erase blocks while the solid state storage device is handling IO requests.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the storage device 102 via, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The Memory device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, either in software, hardware, firmware, or a combination thereof. The control component 104 may be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integr ated Circuit ), or a combination thereof. The control component 104 can also include a processor or controller. The control component 104 loads firmware from the firmware memory 110 at runtime. Firmware memory 110 may be NOR flash, ROM, EEPROM, or may be part of NVM chip 105.

In solid state storage devices, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper level software such as the operating system. The physical address is an address for accessing a physical storage unit of the solid state storage device. Address mapping can also be implemented in the prior art using an intermediate address modality. For example, logical addresses are mapped to intermediate addresses, which in turn are further mapped to physical addresses.

The table structure storing mapping information from logical addresses to physical addresses is called FTL table. FTL tables are important metadata in solid state storage devices. Typically, the data items of the FTL table record address mapping relationships in units of data pages in the solid-state storage device.

FTL tables include a plurality of FTL table entries (or entries). In one embodiment, a correspondence of one logical page address to one physical page is recorded in each FTL table entry. In another example, correspondence between consecutive logical page addresses and consecutive physical pages is recorded in each FTL table entry. In yet another embodiment, a correspondence of logical block addresses to physical block addresses is recorded in each FTL table entry. In still another embodiment, the FTL table records a mapping relationship between a logical block address and a physical block address, and/or a mapping relationship between a logical page address and a physical page address.

Fig. 2 is a schematic diagram of a prior art control component accessing FTL table. The control component 204 includes multiple CPUs (CPU 210, CPU 212, and CPU 214) that interface with flash memory, through which the control component's CPU accesses the NVM chips in the solid-state storage device. FTL table is stored in a memory external to control component 204 and includes a plurality of entries (entry 220, entry 222, and entry 224). Each of the plurality of CPUs is capable of independently accessing the FTL table. Since FTL entries may be accessed by multiple CPUs simultaneously, a lock is provided for each FTL entry for data consistency. Referring to FIG. 2, to update the FTL entry 224, the CPU 210 checks the lock 234 of the FTL entry 224, and in the event that the lock 234 indicates that the FTL entry 224 is not locked, the CPU 210 obtains the lock 234 (e.g., sets the lock 234 to the locked state) and obtains the FTL entry 224 (time t 1). Next, CPU 210 operates on the acquired FTL entry 224 and updates FTL entry 224 at time t4 and releases lock 234 (e.g., sets lock 234 to an unlocked state). During times t1-t4, other CPUs (CPU 212 and CPU 214) retrieve the presence of lock 234 and temporarily relinquish access to FTL entry 224. In FIG. 2, at time t2, CPU 212 attempts to access FTL entry 224, but finds lock 234 unavailable, and then relinquishes access to FTL entry 224. Similarly, CPU214 also relinquishes access to FTL entry 224 at time t3 because lock 234 is not available. And after time t4, CPU 210 releases lock 234, and CPU 212 and the one of CPUs 214 that preempt lock 234 will access FTL entry 234. In another example, during the period t1-t4, one task of CPU 210 obtains lock 234, and another task in CPU 210 temporarily relinquishes access to FTL entry 224 because lock 234 is not obtained.

The locks of FTL entries may be stored in the same location of the corresponding FTL entries or the locks of multiple FTL entries may be stored centrally in additional storage space.

Disclosure of Invention

In solid state storage devices, multiple IO requests are processed simultaneously, almost every IO request requiring access to the FTL table. And the lock mechanism serializes the access to the FTL table entry, reduces the parallel processing capacity of solid state storage, and increases the processing delay of IO requests.

In the present application, there is provided a first method of processing an IO request according to the first aspect of the present application, including: in response to receiving a first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; and replaying the first read request if the physical block containing the first physical address is in an erased state.

According to the first method for processing IO request of the first aspect of the application, there is provided a second method for processing IO request of the first aspect of the application, further comprising: if the first physical block including the first physical address is in a written state, data is read from the first physical address in response to the first read request.

According to the first or second method for processing IO requests of the first aspect of the application, there is provided a third method for processing IO requests according to the first aspect of the application, further comprising: in response to receiving an erase request for a first physical block, setting a state of the first physical block to an erased state; and in response to receiving a programming request for the first physical block, setting a state of the first physical block to a written state.

According to one of the first to third methods of processing IO requests of the first aspect of the present application, there is provided a fourth method of processing IO requests according to the first aspect of the present application, wherein said replaying said read request comprises: accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; replaying the first read request if a first physical block containing a first physical address is in an erased state; and if the first physical block containing the first physical address is in the written state, reading data from the first physical address in response to the first read request.

According to a second aspect of the present application, there is provided a first method of processing an IO request according to the second aspect of the present application, comprising: in response to receiving a first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the large block containing the first physical address is in the erased state, the first read request is replayed.

According to the first method for processing IO request of the second aspect of the application, there is provided the second method for processing IO request of the second aspect of the application, further comprising: if the large block containing the first physical address is in a written state, data is read from the first physical address in response to the first read request.

According to the first or second method for processing IO requests of the second aspect of the present application, there is provided a third method for processing IO requests according to the second aspect of the present application, further comprising: in response to receiving an erase request for a first chunk, setting a state of the first chunk to an erased state; and in response to receiving a programming request for the first chunk, setting the state of the first chunk to a written state.

According to the first to third methods of processing IO requests of the second aspect of the present application, there is provided a fourth method of processing IO requests according to the second aspect of the present application, wherein the replaying the read request includes: accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; replaying the first read request if a first chunk containing a first physical address is in an erased state; and if the first large block containing the first physical address is in the written state, reading data from the first physical address in response to the first read request.

According to a fifth aspect of the present application, there is provided a method for processing an IO request, wherein a first physical address recorded by a first FTL entry is obtained even if the first FTL entry is locked.

According to a third aspect of the present application, there is provided a first method of processing an IO request according to the third aspect of the present application, comprising: in response to receiving a first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; data is read from a first physical address.

According to a first method for processing IO requests in the third aspect of the application, there is provided a second method for processing IO requests in the third aspect of the application, further comprising: and if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is in an erased state, replaying the first read request.

According to a second method for processing an IO request according to the third aspect of the present application, there is provided a third method for processing an IO request according to the third aspect of the present application, further comprising: and in response to replaying the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, indicating that the first read request operation fails.

According to a second method for processing an IO request according to the third aspect of the present application, there is provided a fourth method for processing an IO request according to the third aspect of the present application, further comprising: and in response to replaying the first read request, replaying the first read request if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state and if the physical block containing the first physical address is in an erased state.

According to a fourth method for processing an IO request according to the third aspect of the present application, there is provided a fifth method for processing an IO request according to the third aspect of the present application, further comprising: in response to replaying the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the first physical block containing the first physical address is in a written state, reading the data from the first physical address in response to the first read request.

According to a fourth method for processing an IO request according to the third aspect of the present application, there is provided a sixth method for processing an IO request according to the third aspect of the present application, further comprising: and in response to replaying the first read request, replaying the first read request if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state and if the large block containing the first physical address is in an erased state.

According to a sixth method for processing an IO request according to the third aspect of the present application, there is provided a seventh method for processing an IO request according to the third aspect of the present application, further comprising: in response to replaying the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the large block containing the first physical address is in a written state, reading the data from the first physical address in response to the first read request.

According to a fourth aspect of the present application, there is provided a first method of processing an IO request according to the fourth aspect of the present application, comprising: in response to receiving a write request, accessing a first FTL entry corresponding to the write request, and if the first FTL entry is not locked, locking the first FTL entry; in response to receiving a read request, accessing a first FTL entry corresponding to the read request, if the first FTL entry is locked, and if a physical block containing a first physical address is in an erased state, replaying the first read request; and allocating a first physical address for the write request, updating the first FTL table entry with the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to the first method for processing IO request of the fourth aspect of the application, there is provided the second method for processing IO request of the fourth aspect of the application, further comprising: in response to receiving a read request, accessing a first FTL entry corresponding to the read request, if the first FTL entry is locked, and if a first physical block comprising a first physical address is in a written state, reading data from the first physical address in response to the first read request.

According to a fourth aspect of the present application, there is provided a third method for processing an IO request according to the fourth aspect of the present application, wherein if a first FTL entry is locked while a write request is being processed, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a fourth aspect of the present application, there is provided a fourth method for processing an IO request in a fourth aspect of the present application, wherein after a lock of the first FTL entry is released, the first FTL entry is acquired, and the first FTL entry is locked.

According to a fourth aspect of the present application, there is provided a fifth method for processing an IO request, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is terminated.

According to a fifth aspect of the present application, there is provided a first method of processing an IO request according to the fifth aspect of the present application, comprising: in response to receiving a write request, accessing a first FTL entry corresponding to the write request, and if the first FTL entry is not locked, locking the first FTL entry; in response to receiving a read request, accessing a first FTL entry corresponding to the read request, and replaying the first read request if a physical block containing a first physical address is in an erased state; and allocating a first physical address for the write request, updating the first FTL table entry with the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to a first method for processing an IO request according to a fifth aspect of the present application, there is provided a second method for processing an IO request according to the fifth aspect of the present application, further comprising: and in response to receiving the read request, accessing a first FTL entry corresponding to the read request, and if a first physical block containing a first physical address is in a written state, reading data from the first physical address to respond to the first read request.

According to a fifth aspect of the present application, there is provided a third method of processing an IO request according to the fifth aspect of the present application, wherein if a first FTL entry is locked while processing a write request, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a fifth aspect of the present application, there is provided a fourth method for processing an IO request in a fifth aspect of the present application, wherein after the lock of the first FTL entry is released, the first FTL entry is acquired, and the first FTL entry is locked.

According to a fifth aspect of the present application, there is provided a method for processing an IO request, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is terminated.

According to a sixth aspect of the present application, there is provided a method of processing an IO request according to the first aspect of the present application, comprising: in response to receiving a write request, accessing a first FTL entry corresponding to the write request, and if the first FTL entry is not locked, locking the first FTL entry; in response to receiving a read request, accessing a first FTL entry corresponding to the read request, and replaying the first read request if a first chunk including a first physical address is in an erased state; and allocating a first physical address for the write request, updating the first FTL table entry with the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to a first method for processing an IO request according to a sixth aspect of the present application, there is provided a second method for processing an IO request according to the sixth aspect of the present application, further comprising: in response to receiving a read request, accessing a first FTL entry corresponding to the read request, and if a first chunk including a first physical address is in a written state, reading data from the first physical address to respond to the first read request.

According to a third aspect of the present application, there is provided a method for processing an IO request, wherein when a write request is processed, if a first FTL entry is locked, processing of the write request is suspended until the lock of the first FTL entry is released.

According to a third method for processing an IO request in a sixth aspect of the present application, there is provided a method for processing an IO request in a fourth aspect of the present application, wherein after the lock of the first FTL entry is released, the first FTL entry is acquired, and the first FTL entry is locked.

According to a seventh aspect of the present application, there is provided an apparatus for processing an IO request according to the seventh aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received first reading request, accessing a first FTL table entry corresponding to the first reading request and acquiring a first physical address recorded by the first FTL table entry; and the read request replay module is used for replaying the first read request if the physical block containing the first physical address is in an erased state.

According to an eighth aspect of the present application, there is provided an apparatus for processing an IO request according to the eighth aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received first reading request, accessing a first FTL table entry corresponding to the first reading request and acquiring a first physical address recorded by the first FTL table entry; and the read request replay module is used for replaying the first read request if the large block containing the first physical address is in an erased state.

According to a ninth aspect of the present application, there is provided an apparatus for processing an IO request according to the ninth aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received first reading request, accessing a first FTL table entry corresponding to the first reading request and acquiring a first physical address recorded by the first FTL table entry; and the reading module is used for reading the data from the first physical address.

According to a tenth aspect of the present application, there is provided an apparatus for processing an IO request according to the tenth aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; the read request replay module is used for responding to the received read request, accessing a first FTL (flash translation layer) table item corresponding to the read request, and replaying the first read request if the first FTL table item is locked and if a physical block containing a first physical address is in an erased state; the write request processing module is used for distributing a first physical address for the write request, updating the first FTL table entry by the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to an eleventh aspect of the present application, there is provided an apparatus for processing an IO request according to the eleventh aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; the read request replay module is used for responding to the received read request, accessing a first FTL table item corresponding to the read request, and replaying the first read request if a physical block containing a first physical address is in an erased state; the write request processing module is used for distributing a first physical address for the write request, updating the first FTL table entry by the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a twelfth aspect of the present application, there is provided an apparatus for processing an IO request according to the first aspect of the present application, comprising: the FTL table entry acquisition module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; the read request processing module is used for responding to a received read request, accessing a first FTL table item corresponding to the read request, and replaying the first read request if a first large block containing a first physical address is in an erased state; the write request processing module is used for distributing a first physical address for the write request, updating the first FTL table entry by the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a thirteenth aspect of the present application there is provided a computer program comprising computer program code which, when loaded into a computer system and executed thereon, causes the computer system to perform the method of handling IO requests provided according to the first to sixth aspects of the present application.

According to a fourteenth aspect of the present application there is provided a program comprising program code which, when loaded into a storage device and executed thereon, causes the storage device to perform the method of handling IO requests provided according to the first to sixth aspects of the present application.

Drawings

The application, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a prior art memory device;

FIG. 2 is a schematic diagram of a control component of a prior art memory device accessing an FTL table;

FIG. 3A is a schematic diagram of a control component of a storage device accessing an FTL table according to an embodiment of the present application;

FIG. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present application;

FIG. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present application; and

FIG. 4A is a flow chart of accessing an FTL table for processing a write command according to an embodiment of the present application;

FIG. 4B is a flow chart of accessing an FTL table for processing a read command according to an embodiment of the present application;

FIG. 5A is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present application;

FIG. 5B is a sequence diagram of processing IO requests in accordance with yet another embodiment of the present application;

FIG. 6 is a schematic diagram of organizing physical blocks of an NVM into a block stripe according to an embodiment of the application;

FIG. 7 is a schematic diagram of a control component of a memory device accessing an FTL table according to still another embodiment of the present application;

FIG. 8A is a flow chart of accessing an FTL table for processing a write command according to yet another embodiment of the present application;

FIG. 8B is a flow chart of accessing an FTL table for processing a read command according to yet another embodiment of the present application;

FIG. 9A is a flow chart of accessing an FTL table for processing IO commands according to an embodiment of the present application;

FIG. 9B is a flow chart of accessing an FTL table for processing IO commands according to yet another embodiment of the present application; and

fig. 9C is a flow chart of accessing FTL tables for processing IO commands according to yet another embodiment of the present application.

Detailed Description

In the NVMe (Non-Volatile Memory express, high-speed nonvolatile storage) protocol, different IO command types are defined. For a part of IO commands, no requirement is made on the sequentiality between IO commands. For example, if a read command to logical address x is submitted and a write command to logical address x is also submitted, the NVMe protocol allows the solid state storage device to execute the two IO commands in any order if no ordering is required between them in the two IO commands, although the execution result of the write command would affect the execution result of the read command.

Aiming at the characteristic of the NVMe protocol, in the embodiment of the application, the processing mode of the IO request is improved so as to improve the processing capacity of the IO command of the solid-state storage device and reduce the processing delay of the IO command. Those skilled in the art will appreciate that while embodiments in accordance with the present application are described with the NVMe protocol as an example, embodiments in accordance with the present application may be implemented in other protocols that do not require execution order between IO commands.

Referring to fig. 3A, a schematic diagram of a control component of a storage device accessing FTL tables according to an embodiment of the present application is shown. The control unit 304 of the solid state disk includes a plurality of CPUs (CPU 310, CPU 312, and CPU 314), each of which has access to FTL tables external to the control unit 304. FTL tables are stored in, for example, DRAM (Dynamic Random Access Memory ). The CPU of the control unit also accesses the NVM chip via a flash memory interface (not shown). By way of example, CPU 310 processes a write command from a host, accesses FTL entry 324 at time t1 (indicated by W-t1 of FIG. 3A) according to the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing to the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 3A, CPU 310 accesses lock 334 corresponding to FTL entry 324. In the example of FIG. 3, lock 334 indicates that FTL entry 324 is not locked, and CPU 310 modifies lock 334 to indicate locking of FTL entry 324. In an embodiment in accordance with the application, when a write command is processed, a lock of the FTL entry that the write command is to modify is to be acquired. When a lock cannot be acquired, processing of the write command is temporarily suspended and release of the lock is awaited. In the example of FIG. 3A, after time t1, CPU 310 obtains a lock for FTL entry 324. At this point, when the other CPU is to access the FTL entry 324 for processing a write command, processing of the write command to access the FTL entry 324 is aborted because the discovery lock 334 indicates that the FTL entry 324 has been locked.

Still referring to fig. 3a, the cpu 314 processes a read command from the host and accesses the FTL entry 324 at time t2 based on the logical address of the read command. Although FTL entry 324 is already locked, in an embodiment in accordance with the present application, CPU 314 ignores the lock of FTL entry 324, still acquires FTL entry 324, and acquires the physical address to be accessed according to FTL entry 324. Further, the CPU 314 or other CPU reads data via the physical address and provides the read data to the host as a response to the read command. Since whether the FTL entry 324 is locked is not checked when the read command is processed, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces the time for read command processing because there is no need to wait for the lock of FTL entry 324 to be released while processing the read command.

In the example of FIG. 3A, to process a write command, CPU 310 allocates a new physical address for the write command and updates FTL entry 324 with the new physical address, and at time t3, CPU 310 completes the update of FTL entry 324 (indicated by W-t3 in FIG. 3). And also writing data to the new physical address in response to the write command. The data may be written to the new physical address by CPU 310 or other CPU. Thus, at time t2 prior to time t3, CPU 314 obtains the old physical address from FTL entry 324, and after time t3, obtains the new physical address from FTL entry 324 in response to the read command (updated by CPU 310 when the write command is processed). Thus, when processing a read command, if the CPU 314 accessed the FTL entry 324 before time t3, it will get a different physical address to access the FTL entry 324 after time t3, and thus read a different data. Such a result conforms to a protocol such as NVMe protocol that does not require the processing order of the IO commands.

In one example, lock 334 and FTL entry 324 are stored separately from each other. To process a read command, the CPU314 accesses the FTL entry 324 without accessing the lock 334. In another example, lock 334 is stored in the same memory location as FTL entry 324. While processing the read command, the CPU314 accesses the FTL entry 324 and will obtain the contents of the lock 334, but the CPU314 need not process the contents of the lock 334, but only care about the physical address provided by the FTL entry 324.

With continued reference to fig. 3A, the granularity of the lock is for each FTL entry. In response to the IO command, CPU 312 accesses FTL entry 328. For read commands, CPU 312 ignores lock 338 corresponding to FTL entry 328; for a write command, CPU 312 checks lock 338 corresponding to FTL entry 328, continues processing of the write command when lock 338 indicates FTL entry 328 is not locked, pauses processing of the write command when lock 338 indicates FTL entry 328 is locked, or defers updating of FTL entry 328.

Fig. 3B is a schematic diagram of a control component of a storage device accessing FTL tables according to another embodiment of the present application. Read or write commands from the host access data of different lengths and access different numbers of FTL entries. In an embodiment according to the application, the granularity of locking is per FTL entry. For example, CPU310 processes a write command from a host, the write command accesses 3 logical addresses, and CPU310 accesses FTL entry 320, FTL entry 322, and FTL entry 324 (indicated by W1-t1, W2-t1, and W3-t1 of FIG. 3B) at time t1 based on the logical address indicated by the write command to allocate a physical address for the write command. CPU310 also requests locks corresponding to the FTL entries when accessing the FTL entries, and requests locks corresponding to FTL entries 320, FTL entries 322, and FTL entries 324 by accessing locks 330, 332, and 334. When the corresponding lock is acquired, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry with the new physical address, and when the corresponding lock cannot be acquired, the CPU310 suspends the operation on the corresponding FTL entry, waiting for the corresponding lock to be released. For example, CPU310 obtains the lock of FTL entry 320 and FTL entry 322, but does not obtain the lock of FTL entry 324, CPU310 continues to update FTL entry 320 and FTL entry 322 and suspends operation of FTL entry 324 until lock 334 of FTL entry 324 is released and obtained by CPU310, CPU310 continues to update FTL entry 324. In response to the FTL entry being updated, data is also written to the new physical address in response to the write command. After the new physical addresses of the three FTL entries corresponding to the write command are written into the data, the write command processing is completed.

Still referring to FIG. 3B, CPU 314 processes a read command from the host, and accesses FTL entry 324 (denoted R-t2 in FIG. 3B) at time t2 based on the logical address of the read command. Although FTL entry 324 has been locked by CPU310 when processing a write command, in an embodiment according to the present application, CPU 314 ignores the lock of FTL entry 324, still acquires FTL entry 324, and acquires the physical address to be accessed according to FTL entry 324. Further, the CPU 314 or other CPU reads data via the physical address and provides the read data to the host as a response to the read command. Since whether the FTL entry 324 is locked is not checked when the read command is processed, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces the time for read command processing because there is no need to wait for the lock of FTL entry 324 to be released while processing the read command.

Fig. 3C is a schematic diagram of a control component of a memory device accessing FTL tables according to still another embodiment of the present application. In the illustrated embodiment, multiple IO commands may be processed in parallel on the same CPU. By way of example, CPU310 processes a write command from a host, and CPU310 accesses FTL entry 324 (indicated by W1-t2 of FIG. 3C) at time t1 based on the logical address indicated by the write command to assign a physical address to the write command. The CPU310 also requests a lock corresponding to an entry when accessing the FTL entry, and requests a lock corresponding to the FTL entry 324 by accessing the lock 334. Upon acquisition of the corresponding lock, CPU310 performs a subsequent operation, allocates a new physical address and updates the corresponding FTL entry 324 with the new physical address at time t3 (updating of the FTL entry 324 indicated by W3-t3 of FIG. 3C). Between times t1 and t3, CPU310 also accesses FTL entry 324 at time t2 in response to a host read command. While at time t2, lock 334 indicates FTL entry 324 is locked, for a read command, CPU310 still accesses and uses FTL entry 324, reading data using the physical address provided by FTL entry 324, even if there is a lock on FTL entry 324. In a further embodiment, CPU310 caches the FTL entry 324 taken at time t1 and retrieves the contents of the FTL entry 324 from the CPU310 cache at time t 2. And for processing read commands, the data is read using the physical address provided by the cached FTL entry 324, whether or not the FTL entry 324 cached by the CPU310 is updated. At time t2, CPU 314 accesses FTL entry 324 (shown as R3-t2 in FIG. 3C) in response to the logical address of another read command. Because of the read command, although lock 334 indicates FTL entry 324 is locked, CPU 314 still accesses and uses FTL entry 324 and reads data with the physical address provided by FTL entry 324.

Fig. 4A is a flow chart of accessing FTL tables for processing write commands according to an embodiment of the present application. In an embodiment according to the application, in response to receiving a write command to access a logical address of a first FTL entry (410), it is checked whether the first FTL entry is locked (420). If the first FTL entry is locked, the subsequent processing of the first FTL entry is suspended, and the lock of the first FTL entry is waited for to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, the first FTL entry is locked (430) for processing the write command, such that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is allocated for the write command, a first FTL entry is updated with the first physical address, the updated FTL entry is written to the FTL table, and the first FTL entry is unlocked (440). The assignment of a new physical address for a write command may utilize a variety of ways known in the art. And writing data corresponding to the write command to the first physical address (450).

In another example, when the first FTL entry corresponding to the logical address of the write command is accessed in response to receiving the second write command, the processing of the second write command is completed if the first FTL entry is found to be locked, and no physical address is allocated to the second write command, and no data corresponding to the second write command is written into the nonvolatile memory.

Fig. 4B is a flow chart of accessing FTL tables for processing read commands according to an embodiment of the present application. In response to receiving the read command, a logical address of the read command corresponds to the first FTL entry (432). For a read command, it is not checked whether the first FTL entry is locked. Even though the first FTL entry has been locked (see step 430 of fig. 4A) due to processing of the write command, the locked first FTL entry is retrieved and used from the FTL table (434) when the read command is processed. And reading out the data (436) as a response to the read command based on the first physical address.

In another example, when the first FTL entry is obtained for processing the read command, if the first FTL entry is locked, it indicates that there is a write command in execution accessing the first FTL table, and data to be written by the write command is in the cache. And searching data to be written by a write command accessing the first FTL table from the cache as read data of the read command. The speed of acquiring data from the cache is far faster than that of acquiring data from the nonvolatile memory chip, so that the cache data to be written is used as a response to a read command, and the processing time of the read command is further reduced.

Fig. 5A is a schematic diagram of a control component of a storage device accessing FTL tables according to yet another embodiment of the present application.

The control section 504 of the solid state disk includes a plurality of CPUs (CPU 510, CPU 512, CPU 514), each of which has access to FTL tables external to the control section 504. The CPU of the control unit also accesses NVM chip 505 through a flash interface. NVM chip 505 includes a plurality of memory cells, such as memory cell 550, memory cell 552, memory cell 560, and memory cell 562. By way of example, CPU 510 processes a write command from a garbage collection task, accesses FTL entry 524 at time t1 (indicated by Wg-t1 of FIG. 5A) according to the logical address indicated by the write command to allocate a physical address for the write command. To avoid multiple write commands writing to the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 5A, CPU 510 accesses lock 534 corresponding to FTL entry 524. In the example of fig. 5A, CPU 510 modifies lock 534 to indicate the locking of FTL entry 524.

Still referring to FIG. 5A, the CPU 514 processes a read command from the host, and accesses the FTL entry 524 (indicated by R-t2 in FIG. 5A) at time t2 according to the logical address of the read command. Although FTL table 524 is already locked, in an embodiment in accordance with the present application, CPU 514 ignores the lock of FTL table entry 524, still acquires FTL table entry 524, and acquires the physical address to be accessed according to FTL table entry 524 when processing the read command. The CPU 514 accesses the physical address of the NVM chip 505 through the flash interface according to the acquired physical address and obtains data to be read.

In the example of FIG. 5A, to process a write command from a garbage collection task, CPU 510 allocates a new physical address for the write command and updates FTL entry 524 with the new physical address, and at time t3, CPU 510 completes updating FTL entry 524 (indicated by Wg-t3 in FIG. 5A). And also writing data to the new physical address in response to the write command.

In some cases, the physical address accessed when the CPU 514 processes the read command is a physical block in the NVM chip 505 in an erased state. Physical blocks in the erased state do not have valid data in them and should not be read. FIG. 5B is a sequence diagram of processing IO requests, illustrating the cause of CPU 514 reading to an erase block in NVM chip 505, according to yet another embodiment of the present application. In fig. 5B, the time axis shows the elapsed direction of time. In response to a Garbage Collection (GC) write command 560, the cpu 510 accesses FTL entry 524 at time t1 (indicated by Wg-t1 of fig. 5A) according to the logical address indicated by the write command 560, FTL entry 524 is locked, and the physical address of FTL entry 524 indicates the memory location 550 of NVM chip 505. In processing the GC write command (560), the FTL entry 524 is next updated by the CPU 510, and the physical address of the FTL entry 524 updated indicates the storage unit 560.

After FTL entry 524 is locked, a user read command is received (570), CPU 514 processes the user read command (570) and retrieves FTL entry 524. The physical address retrieved from FTL entry 524 indicates the storage unit 550 because the lock 534 of FTL entry 524 is ignored by the CPU 514 when the FTL entry 524 is retrieved and the time to retrieve FTL entry 524 is before FTL entry 524 is updated by the CPU 510.

With continued reference to FIG. 5B, following the GC write command (560), a GC erase command (562), in response to the GC erase command (562), the affected old physical address (memory cell 550) of the GC write command (560) is erased. So that the memory cells 550 of the NVM chip are in an erased state. And CPU 514 obtains the old FTL entry 524 for processing the user read command 570 and issues the read command to memory unit 550 via the flash memory interface. The two operations, i.e., the CPU 514 issuing a read command to the memory unit 550 and the CPU 510 issuing an erase command to the memory unit 550, may occur in any order, such that when the CPU 514 issues a read command, the memory unit 550 may be in an erased state, and thus the read command may not be processed correctly.

In an embodiment according to the present application (see fig. 5A), to solve the above-described problem, the control section 504 also maintains a block status table 540. In the block state table 540, it is recorded whether each physical block of the NVM chip 550 is in an erased state or in an already written state. In one example, when a physical block is erased, block state table 540 is updated to identify that the physical block is in an erased state. And when a physical block is first written, the block status table 540 is updated to identify that the physical block is in a written state. Before the CPU 514 issues a read command to the NVM chip 505 via the flash interface, the physical block in which the physical address is located is obtained from the physical address obtained from the FTL entry 524, and the state of the physical block is queried in the block state table 540. If the physical block is in the written state, the CPU 514 issues a read command to the NVM chip 505 through the flash interface; if the physical block is in the erased state, the CPU 514 directs the read command to be replayed. By way of example, playback of a read command means that the control unit 504 treats the read command as a newly received read command and reprocesss it. Because of the time required for re-processing, when the FTL entry 524 is re-acquired, its contents are updated with a high probability, the newly acquired FTL entry 524 will provide an updated physical address, and valid data is stored in the updated physical address. In rare cases, as an example, when the FTL entry 524 is re-acquired, the updating of the FTL entry 524 is still incomplete, and the re-acquired FTL entry is still an old physical address in the erased state. In this case, in one example, the read command is replayed again to retrieve FTL entry 524; in yet another example, the CPU 514 further identifies a lock 534 corresponding to the FTL entry 524. If lock 534 indicates that FTL entry 524 is locked, CPU 514 waits for release of lock 534 to acquire updated FTL entry 524 and then accesses NVM chip 505 with the physical address provided by updated FTL entry 524; if lock 534 indicates FTL entry 524 is not locked, then NVM chip 505 is immediately accessed with the physical address provided by FTL entry 524.

FIG. 6 is a schematic diagram of organizing physical blocks of an NVM into a block stripe according to an embodiment of the application. In the solid-state storage device shown in FIG. 6, a stripe of blocks is constructed over every 16 logical units (LUN 0, LUN1, … … LUN 15), with physical blocks of the same physical address in each logical unit constituting a "stripe of blocks".

In FIG. 6, block B0 with address 0 in LUN0-LUN15 constitutes block stripe 0, where physical block B0 of LUN0 through LUN14 is used to store user data, and physical block B0 of LUN15 is used to store parity data calculated from user data within the block stripe. The physical block of the NVM includes a plurality of pages, the physical pages in the block stripe having the same address forming a page stripe, and the check data is calculated for each page stripe. For example, each physical page of physical block B0 of LUN15 stores the calculated check data for all user data of the page stripe in which the physical page resides.

Similarly, in FIG. 6, LUN0-LUN15 is physical block B2, stripe 2, with address 2. Alternatively, the physical block used to store the check data may be located in any LUN in the block stripe. In the example of fig. 6, with the check data in the block stripe, in the case where the data of 1 physical page of the block stripe is corrupt, the data of the corrupt page can be recovered from the other pages of the page stripe in which the physical page is located.

Those skilled in the art will appreciate that the block strips may be constructed in a variety of other data organization manners. A plurality of physical blocks are included in a block stripe and data protection is provided in the block stripe by redundancy or RAID techniques. So that in case one or several physical blocks in the block stripe are corrupted, data of a bad physical block can be reconstructed by other blocks of the block stripe. Erasure is performed in units of a block stripe. When performing an erase operation, all physical blocks belonging to a block stripe are erased together.

Fig. 7 is a schematic diagram of a control component of a memory device accessing FTL tables according to still another embodiment of the present application. In contrast to FIG. 5A, in the embodiment of FIG. 7, control unit 504 further includes CPU 516, and NVM705 includes block stripes 750, block stripes 752, block stripes 754, and block stripes 756, and a block stripe state table 740 that records the state of each block stripe. In block stripe state table 740, a plurality of entries (entry 760, entry 762, entry 764, and entry 766) are included, each entry recording whether the corresponding block stripe of NVM705 is in an erased state or in a state that has been written. In one example, when a block stripe is erased, block stripe state table 740 is updated to identify that the block stripe is in an erased state. And when a block stripe is first written, the block stripe state table 740 is updated to identify that the physical block is in a written state.

In the embodiment of fig. 7, for a processor read command, CPU 514 accesses FTL entry 524 and provides the physical provision provided by FTL entry 524 to CPU 516.CPU 516 issues a read command to NVM 705 over a flash interface. Before the CPU516 issues a read command to the NVM 705 via the flash interface, the physical address obtained from the FTL entry 524 is used to obtain the block stripe where the physical address is located, and the status of the block stripe is queried in the block stripe status table 740. If the block stripe is in the written state, CPU516 issues a read command to NVM 705 over the flash interface; if the physical block is in the erased state, the CPU516 directs the read command to be replayed. In rare cases, as an example, when the FTL entry 524 is re-acquired, the updating of the FTL entry 524 is still incomplete, and the re-acquired FTL entry provides a physical address that is still old and in an erased state. In this case, in one example, the read command is replayed again to retrieve FTL entry 524; in yet another example, the CPU516 further identifies a lock 534 corresponding to the FTL entry 524. If lock 534 indicates that FTL entry 524 is locked, CPU 614 waits for release of lock 534 to obtain updated FTL entry 524 and then provides the physical address provided by updated FTL entry 524 to CPU 516; if lock 534 indicates FTL entry 524 is not locked, the physical address provided by FTL entry 524 is immediately provided to CPU 516.

Fig. 8 is a flow chart of accessing FTL tables for processing IO commands according to yet another embodiment of the present application. In the embodiment according to fig. 8, in response to receiving a write command to access a logical address of a first FTL entry (802), it is checked whether the first FTL entry is locked (804). If the first FTL entry is locked, the subsequent processing of the first FTL entry is suspended, and the lock of the first FTL entry is waited for to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, the first FTL entry is locked (806) for processing the write command, such that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is allocated for the write command, a first FTL entry is updated with the first physical address, the updated FTL entry is written to the FTL table, and the first FTL entry is unlocked (808). The assignment of a new physical address for a write command may utilize a variety of ways known in the art. And writing data corresponding to the write command to the first physical address (809).

With continued reference to fig. 8, in response to receiving the read command, the logical address of the read command also corresponds to the first FTL entry (810). For a read command, it is not checked whether the first FTL entry is locked. Even though the first FTL entry has been locked due to processing the write command (see step 806 of fig. 8), the first physical address provided by the first FTL entry is obtained from the FTL table and used when the read command is processed (820). Next, the corresponding physical block or block stripe is obtained from the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5a, 540) or the block stripe state table (see fig. 7, 740). If the retrieved state indicates that the physical block or stripe of blocks where the first physical address is located is in an erased state (830), the read command is replayed, in other words, the read command is reprocessed through step 810. If the acquired state indicates that the physical block or stripe of blocks where the first physical address is located is in a written state (830), data is read from the first physical address in response to the read command (840).

Fig. 9A is a flow chart of accessing FTL tables for processing IO commands according to an embodiment of the present application. In the embodiment of fig. 9A, in response to receiving a read command, a logical address of the read command corresponds to a first FTL entry (910). For a read command, it is not checked whether the first FTL entry is locked. Even though the first FTL entry has been locked due to processing of the write command, the first physical address provided by the first FTL entry is retrieved from the FTL table and used when the read command is processed (920). Next, a read command is sent to the NVM in accordance with the first physical address to read data from the first physical address (925). The result of reading the data indicates whether the physical page corresponding to the first address is in an erased state (930). In one example, the NVM chip provides an indication in the result of reading the data to identify whether the physical page being read is in an erased state. In another example, the flash interface of the control unit determines from the data read from the NVM chip whether the read data is from a physical page in an erased state.

With continued reference to FIG. 9A, if the read data result indicates that the physical page corresponding to the first physical address is in an erased state, return to step 910 and replay the read command. If the read data result indicates that the physical page corresponding to the first physical address is not in an erased state, the read data is valid and the read data is used as a response to the read command, and the read command processing is completed (940).

In the embodiment of fig. 9A, after the first physical address is obtained, it is not first checked whether the physical block or block stripe in which the first physical address is located is in an erased state. Because the probability that the physical block or stripe of blocks where the first physical address is located is in the erased state is low, in most cases, checking whether it is in the erased state will introduce additional delay. In the embodiment of fig. 9A, after the first physical address is obtained, it is not first checked whether the physical block or block stripe where the first physical address is located is in an erased state, but the data is directly read from the first physical address, and it is determined whether the read physical page is in an erased state depending on an indication provided by the read data result. Thus, only when the read physical page is in an erased state, additional processing is performed, and the average processing delay of the read command is reduced.

Fig. 9B is a flow chart of accessing FTL tables for processing IO commands according to yet another embodiment of the present application. The embodiment of fig. 9B is similar to the embodiment of fig. 9A, except that when data is read from the first physical address, it is determined in the result of the reading of the data whether the physical page corresponding to the first address is in the erased state (980), if the result of the reading of the data indicates that the physical page corresponding to the first physical address is in the erased state, a corresponding physical block or stripe is obtained according to the first physical address, and the state of the corresponding physical block or stripe is obtained from the block state table (see fig. 5a, 540) or the block stripe state table (see fig. 7, 740) (990). If the physical block or stripe of blocks where the first physical address is located is in a written state (990), then the read data results from the first physical address indicate that the physical page is in an erased state independent of whether the first FTL entry is locked, but rather that the data stored by the first physical address is corrupted, indicating that the read command processing failed as a response to the read command (995). If the physical block or stripe of blocks where the first physical address is located is in the erased state 990, the process returns to step 950 to replay the read command. And when the data is read from the first physical address, judging whether the physical page corresponding to the first address is in an erased state or not in the result of the data reading (980), if the result of the data reading indicates that the physical page corresponding to the first physical address is not in the erased state, taking the read data as a response to a read command, and completing the read command processing (985).

Referring still to FIG. 9B, in another example, when the first time step 980 is passed, the data is read from the first physical address for the first time, and it is determined in the result of reading the data that the physical page corresponding to the first address is in the erased state (980), the read command is directly replayed as indicated by the dashed line in FIG. 9B. For the same read command, since it is replayed, when the second time passes through step 980, if it is determined again that the physical page corresponding to the first address is in the erased state (980) in the result of reading the data, step 990 is entered, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5a, 540) or the block stripe state table (see fig. 7, 740).

In the embodiment of FIG. 9B, different processing strategies are employed to achieve better error handling efficiency when the read physical page is encountered as being in an erased state.

Fig. 9C is a flow chart of accessing FTL tables for processing IO commands according to yet another embodiment of the present application. The embodiment of fig. 9B is similar to the embodiment of fig. 9C, except that when data is read from the first physical address and it is determined in the result of the reading of the data whether the physical page corresponding to the first address is in the erased state (980), it is queried whether the first FTL entry is locked (992). If the first FTL entry is not locked (992), then reading the data result from the first physical address indicates that the physical page is in an erased state independent of whether the first FTL entry is locked, but rather that the data stored by the first physical address is corrupted, indicating that the read command processing failed as a response to the read command (995). If the first FTL entry is locked (992), reading the data result from the first physical address indicates that the physical page is in an erased state in connection with the first FTL entry being locked, waiting for the lock of the first FTL entry to be released, retrieving the first FTL entry again and obtaining the updated second physical address provided by the first FTL (994). And issuing an access command to the NVM at the second physical address, reading data from the second physical address of the NVM (996) as a response to the read command.

Referring still to FIG. 9C, in another example, when the first time step 980 is passed, the data is read from the first physical address for the first time, and it is determined in the result of reading the data that the physical page corresponding to the first address is in the erased state (980), the read command is directly replayed, as indicated by the broken line in FIG. 9C, returning to step 950. For the same read command, if the physical page corresponding to the first address is again determined to be in the erased state (980) in the result of reading the data when the read command is replayed and passes through the step 980 for the second time, step 992 is entered to query whether the first FTL entry is locked, and the subsequent processing is performed.

In the embodiment of FIG. 9C, different processing strategies are employed to achieve better error handling efficiency when the read physical page is encountered as being in an erased state.

The embodiment of the present application also provides a program comprising program code which, when loaded into and executed in a CPU, causes the CPU to perform one of the methods according to the embodiments of the present application provided above.

The present application also provides a program comprising program code which, when loaded into and executed on a storage device, causes a processor of the storage device to perform one of the methods provided above in accordance with the embodiments of the present application.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

Although the present application has been described with reference to examples, which are intended for purposes of illustration only and not to be limiting of the application, variations, additions and/or deletions to the embodiments may be made without departing from the scope of the application.

Many modifications and other embodiments of the applications set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the applications are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method of processing an IO request, comprising:

in response to receiving a first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry;

reprocessing the first read request if a physical block or block stripe containing a first physical address is in an erased state;

wherein the first physical address recorded by the first FTL entry is obtained even if the first FTL entry is locked.

2. The method of claim 1, further comprising: and in response to receiving the read request, accessing a first FTL entry corresponding to the read request, and if a first physical block or block stripe containing a first physical address is in a written state, reading data from the first physical address to respond to the first read request.

3. The method of claim 1 or 2, wherein processing of the write request is aborted if the first FTL entry is locked while processing the write request until the lock of the first FTL entry is released.

4. The method of claim 3, wherein the first FTL entry is acquired and locked after the lock of the first FTL entry is released.

5. The method of claim 1 or 2, wherein processing of the write request ends if the first FTL entry is locked while processing the write request.

6. A method of processing an IO request, comprising: in response to receiving a write request, accessing a first FTL entry corresponding to the write request, and if the first FTL entry is not locked, locking the first FTL entry; responding to a received read request, accessing a first FTL table item corresponding to the read request, and reprocessing the first read request if a physical block containing a first physical address is in an erased state; and allocating a first physical address for the write request, updating the first FTL table entry with the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

7. The method of claim 6, further comprising: and in response to receiving the read request, accessing a first FTL entry corresponding to the read request, and if a first physical block containing a first physical address is in a written state, reading data from the first physical address to respond to the first read request.

8. The method of claim 6 or 7, wherein processing of the write request is aborted if the first FTL entry is locked while processing the write request until the lock of the first FTL entry is released.

9. The method of claim 6 or 7, wherein the first FTL entry is acquired and locked after the lock of the first FTL entry is released.

10. The method of claim 6 or 7, wherein processing of the write request ends if the first FTL entry is locked while processing the write request.

11. A method of processing an IO request, comprising:

reading data from a first physical address;

if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is in an erased state, reprocessing the first read request;

responding to the first read request again, and if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, indicating that the first read request operation fails; or in response to reprocessing the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, reprocessing the first read request if the physical block containing the first physical address is in an erased state.

12. The method of claim 11, further comprising: responding to the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, and if the first physical block containing the first physical address is in a written state, reading the data from the first physical address to respond to the first read request; or alternatively

And in response to reprocessing the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, reprocessing the first read request if the large block containing the first physical address is in the erased state.

13. The method of claim 12, further comprising: in response to reprocessing the first read request, if the result of reading the data from the first physical address indicates that the physical page where the first physical address is located is still in an erased state, if the large block containing the first physical address is in a written state, reading the data from the first physical address in response to the first read request.

14. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to one of claims 1-13.