CN111625199A

CN111625199A - Method and device for improving reliability of data path of solid state disk, computer equipment and storage medium

Info

Publication number: CN111625199A
Application number: CN202010467759.6A
Authority: CN
Inventors: 高湾湾; 臧鑫; 冯元元
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-09-04
Anticipated expiration: 2040-05-28
Also published as: CN111625199B

Abstract

The invention relates to a method, a device, computer equipment and a storage medium for improving the reliability of a data path of a solid state disk; the method comprises the following steps: NVMe receives a command sent by a host; judging whether a command sent by a host is a write command; if so, the NVMe takes the data to be written out of the host, adds check bits to the data to be written, stores the data to be written after the check bits are added into the DRAM, and transmits the write command to the FTL; updating a mapping table, and transmitting a write command to the NFC; the NFC takes out the data to be written from the DRAM and verifies the data to be written; judging whether the data to be written passes the verification; if the data passes the write-in process, writing the data to be written into the flash memory; if not, error processing is carried out. According to the invention, the check bit is added to the data written into the DRAM, when the data is read, the operation can be continued only after the check is passed, and the error processing is carried out after the check is failed, so that the reliability of a data path is effectively improved.

Description

Method and device for improving reliability of data path of solid state disk, computer equipment and storage medium

Technical Field

The invention relates to the technical field of data reliability of solid state disks, in particular to a method and a device for improving the reliability of a data path of a solid state disk, computer equipment and a storage medium.

Background

As a storage type Solid State Disk, the data security of an SSD (Solid State Disk) is very important, the SSD mainly consists of a main control module, a cache module, and a flash memory module, the flash memory module is nonvolatile when power down, and is mainly used as a medium for data storage, and the cache module is volatile when power down, and is mainly used for service and data access; the data security of the solid state disk mainly comprises flash memory data protection and data path protection.

The existing data from Host to Flash will pass through DRAM (Dynamic Random Access Memory), and the FTL (Flash transfer Layer) mapping table will occupy most of the space of DRAM, and compared with SRAM (Static Random-Access Memory), DRAM is more prone to error due to bit flipping; therefore, during the data transmission process, errors are likely to occur due to bit flipping of the DRAM, if the Host data is in error, the error data can be stored in Flash as correct data, if a mapping table is in error, the access of the data is deviated, and if the errors cannot be corrected, the data reliability and integrity of the solid state disk are affected.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a method, a device, computer equipment and a storage medium for improving the reliability of a data path of a solid state disk.

In order to achieve the purpose, the invention adopts the following technical scheme:

the method for improving the reliability of the data path of the solid state disk comprises the following steps:

NVMe receives a command sent by a host;

judging whether a command sent by a host is a write command;

if the command is a write command, the NVMe takes the data to be written out of the host, adds a check bit to the data to be written, stores the data to be written after the check bit is added into the DRAM, and simultaneously transmits the write command to the FTL;

the FTL updates the mapping table according to the write command and transmits the write command to the NFC;

the NFC takes out the data to be written from the DRAM and verifies the data to be written;

judging whether the data to be written passes the verification;

if yes, writing the data to be written into the flash memory;

if not, error processing is carried out.

The further technical scheme is as follows: in the step "judging whether the command sent by the host is a write command", if not, the NVMe transmits the command sent by the host to the FTL;

the FTL inquires corresponding items in the mapping table according to the command, updates the mapping result into the command, and transmits the updated command to the NFC;

the NFC reads the data to be read out from the flash memory, adds check bits to the data to be read out, stores the data to be read out after the check bits are added to the DRAM, and simultaneously transmits a command processing result to the NVMe through the FTL;

NVMe takes out data to be read from the DRAM and checks the data to be read;

judging whether the data to be read passes the verification;

if yes, moving the data to be read to a host cache;

if not, error processing is carried out.

The further technical scheme is as follows: and the NVMe takes out the data to be written from the host or moves the data to be read to the host cache through the PCIE interface.

The further technical scheme is as follows: the error handling comprises the steps of:

regenerating the command sent by the host computer and verifying the regenerated command;

judging whether the regenerated command check passes;

if yes, returning to the step of executing to judge whether the command sent by the host is a write command;

if not, the information is transmitted to the host, the equipment has an error prompt, and the host resets the equipment.

Promote device of solid state hard disk data path reliability, include: the device comprises a receiving unit, a first judging unit, a taking-out and adding storage transfer unit, an updating transfer unit, a first taking-out checking unit, a second judging unit, a writing-in unit and a processing unit;

the receiving unit is used for receiving a command sent by the host by the NVMe;

the first judging unit is used for judging whether the command sent by the host is a write command;

the taking-out and storage-adding transfer unit is used for taking out the data to be written from the host by the NVMe, adding a check bit to the data to be written, storing the data to be written after the check bit is added into the DRAM, and simultaneously transferring a write command to the FTL;

the update transfer unit is used for the FTL to update the mapping table according to the write command and transfer the write command to the NFC;

the first taking-out verification unit is used for taking out the data to be written from the DRAM by the NFC and verifying the data to be written;

the second judging unit is used for judging whether the data to be written passes the verification;

the writing unit is used for writing data to be written into the flash memory;

and the processing unit is used for carrying out error processing on the command sent by the host.

The further technical scheme is as follows: further comprising: the transfer unit is used for inquiring and updating the transfer unit, reading the added storage transfer unit, the second taking-out verification unit, the third judgment unit and the moving unit;

the transfer unit is used for the NVMe to transfer the command sent by the host to the FTL;

the query update transfer unit is used for the FTL to query the corresponding item in the mapping table according to the command, update the mapping result into the command, and transfer the updated command to the NFC;

the read-out and storage-adding transfer unit is used for reading data to be read out from the flash memory by NFC, adding check bits to the data to be read, storing the data to be read after the check bits are added into the DRAM, and simultaneously transferring a command processing result to NVMe through the FTL;

the second taking-out checking unit is used for taking out the data to be read from the DRAM by the NVMe and checking the data to be read;

the third judging unit is used for judging whether the data to be read passes the verification;

and the moving unit is used for moving the data to be read to the host cache.

The further technical scheme is as follows: the processing unit includes: the system comprises a generation checking module, a judgment module, a return module and a transmission resetting module;

the generation and verification module is used for regenerating the command sent by the host and verifying the regenerated command;

the judging module is used for judging whether the regenerated command check passes;

the return module is used for returning and executing whether the command sent by the judgment host is a write command;

and the transfer resetting module is used for transferring to the host, prompting that the equipment has an error, and resetting the equipment by the host.

A computer device, the computer device includes a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the method for improving the reliability of the data path of the solid state disk as described above.

A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the method of improving solid state disk data path reliability as described above.

Compared with the prior art, the invention has the beneficial effects that: by adding the check bit to the data written into the DRAM, when the data is read, the data is checked, the operation can be continued only after the check is passed, and error processing is performed after the check is failed, so that the purpose of effectively improving the reliability of a data path is achieved, and the requirement can be better met.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an application of a conventional SSD data path;

fig. 2 is a first flowchart illustrating a method for improving reliability of a data path of a solid state disk according to an embodiment of the present invention;

fig. 3 is a schematic flowchart illustrating a second method for improving reliability of a data path of a solid state disk according to an embodiment of the present invention;

fig. 4 is a schematic view of an application scenario of the method for improving reliability of a data path of a solid state disk according to the embodiment of the present invention;

fig. 5 is a schematic block diagram of an apparatus for improving reliability of a data path of a solid state disk according to an embodiment of the present invention;

FIG. 6 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to the specific embodiments shown in fig. 1 to fig. 6, please refer to the application schematic diagram of the existing SSD data path shown in fig. 1, wherein the SSD main controller mainly comprises NVMe (Non-Volatile Memory host controller interface specification module), FTL (Flash Translation Layer, Flash Memory Translation algorithm module), NFC (Flash Memory control module) and platform. PCIE (Peripheral component interconnect Express) is an interface module of the SSD, and DRAM (Dynamic Random Access Memory) is a cache of the SSD.

Data interaction between Host and SSD is mainly completed through a read-write command path.

The write path process is roughly as follows:

NVMe moves host data to DRAM through PCIE for caching, and transmits a command node to FTL;

the FTL updates the corresponding item in the mapping table according to the node and informs NFC;

the NFC then moves the host data from DRAM to Flash.

The read path is the reverse of the write path, i.e.:

NVMe transmits the command node to FTL;

the FTL inquires corresponding items in the mapping table according to the contents of the node, updates the mapping result into node information and informs NFC;

the NFC moves the Host data from the Flash to the DRAM for caching according to the relevant information of the node;

NVMe then moves the data from DRAM to Host's cache via PCIE.

Compared with an SRAM (Static Random-Access Memory), the DRAM is more prone to error caused by bit flipping, so that during data transmission, errors are likely to occur due to bit flipping of the DRAM, if the Host data is in error, the erroneous data can be stored in the Flash as correct data, if the mapping table is in error, the data Access is biased, and if the errors cannot be corrected, the data reliability and integrity of the solid state disk are affected.

Referring to fig. 2 to 4, the present invention discloses a method for improving reliability of a data path of a solid state disk, including the following steps:

s1, NVMe receives a command sent by the host;

s2, judging whether the command sent by the host is a write command;

s3, if the command is a write command, the NVMe takes out the data to be written from the host, adds a check bit to the data to be written, stores the data to be written after the check bit is added into the DRAM, and simultaneously transmits the write command to the FTL;

in the embodiment, the NVMe takes out the data to be written from the host through the PCIE interface, which has high bandwidth, supports high power, and has a fast transmission speed.

The NVMe calls a check module for each data from Host to DRAM, namely the data to be written, and adds check bits when the data is written into the DRAM, wherein the specific cost is determined by a check algorithm.

Further, in this embodiment, the check algorithm is one of a parity check algorithm, a hamming check algorithm, an MD5 check algorithm, an xor check algorithm, and a cyclic redundancy check algorithm, and is selected according to actual needs, and the check bits are check bits, and the bit size of the check bits is set according to actual needs.

S4, the FTL updates the mapping table according to the write command and transmits the write command to the NFC;

s5, the NFC takes out the data to be written from the DRAM and verifies the data to be written;

when the NFC takes out the data to be written from the DRAM, the check module is called to perform error detection, the same check algorithm is used for checking the data again, and the check algorithm is compared with the existing check bits in the DRAM.

S6, judging whether the data to be written pass the verification;

s7, if the data pass, writing the data to be written into the flash memory;

if not, S8 performs error processing.

Wherein, the step S2 "determines whether the command sent by the host is a write command";

s9, if the command is not a write command, the NVMe transmits the command sent by the host to the FTL;

s10, the FTL inquires corresponding items in the mapping table according to the command, updates the mapping result into the command, and transmits the updated command to the NFC;

s11, reading the data to be read from the flash memory by NFC, adding check bits to the data to be read, storing the data to be read after the check bits are added into a DRAM, and simultaneously transmitting a command processing result to NVMe through FTL;

s12, NVMe takes out the data to be read from the DRAM and checks the data to be read;

s13, judging whether the data to be read passes the verification; if not, the process proceeds to step S8 to perform error handling;

and S14, if the data to be read passes, moving the data to be read to the host cache.

The NVMe moves the data to be read to the host cache through the PCIE interface, and the transmission speed is high and stable.

In the reading and writing process, the FTL is required to search or update the corresponding mapping table for the data, so that the corresponding check bit is added to the FTL table by using the check module to perform data protection, and when an error occurs in the mapping table, the error can be timely processed.

As shown in fig. 3, the error processing of step S8 includes the following steps:

s81, regenerating the command sent by the host computer and verifying the regenerated command;

s82, judging whether the regenerated command check passes;

s83, if yes, returning to step S2 to determine whether the command sent by the host is a write command;

and S84, if the data fails, the data is transmitted to the host, the device generates an error prompt, and the host resets the device.

In step S84, the Host is informed by filling the associated register of aer (advanced Error report) of NVMe, and the device has a FATAL Error (false Error); when the Host detects a fatal error, the equipment is reset, for the NVME controller, the reset effect is the same as the power-on reset effect, the error processing at the level can affect the work of the Host, and the Host needs to reinitialize the NVME equipment to continue working.

Referring to fig. 4, in the application scenario of the present invention, a check module is added to add a check bit to data written in a DRAM, when the data is read, the operation can be continued only after the check is passed, and error processing is performed after the check fails.

The invention adds the check bit to the data written into the DRAM, when the data is read, the data is checked, the operation can be continued only after the check is passed, and the error processing is carried out after the check is failed, thereby achieving the purpose of effectively improving the reliability of the data path and better meeting the requirements.

Referring to fig. 5, the present invention also discloses a device for improving the reliability of the data path of the solid state disk, including: a receiving unit 10, a first judging unit 20, a fetch-and-add-store transferring unit 30, an update transferring unit 40, a first fetch checking unit 50, a second judging unit 60, a writing unit 70, and a processing unit 80;

the receiving unit 10 is configured to receive a command sent by a host by the NVMe;

the first judging unit 20 is configured to judge whether a command sent by the host is a write command;

the fetch-add-store transfer unit 30 is configured to fetch data to be written from the host by the NVMe, add a check bit to the data to be written, store the data to be written after the check bit is added to the DRAM, and transfer a write command to the FTL;

the update transferring unit 40 is configured to update the mapping table according to the write command and transfer the write command to the NFC;

the first taking-out verification unit 50 is configured to take out the data to be written from the DRAM by NFC and verify the data to be written;

the second judging unit 60 is configured to judge whether the data to be written passes the verification;

the writing unit 70 is configured to write data to be written into the flash memory;

the processing unit 80 is configured to perform error processing on a command issued by a host.

Wherein, the device still includes: a transferring unit 90, a query update transferring unit 100, a read-out add-storage transferring unit 110, a second fetch verifying unit 120, a third determining unit 130, and a moving unit 140;

the transfer unit 90 is used for the NVMe to transfer the command issued by the host to the FTL;

the query update transfer unit 100 is configured to query, by the FTL, a corresponding item in the mapping table according to the command, update the mapping result to the command, and transfer the updated command to the NFC;

the read-out add-storage transfer unit 110 is configured to read out data to be read from the flash memory by NFC, add a check bit to the data to be read, store the data to be read after the check bit is added to the DRAM, and transfer a command processing result to NVMe through the FTL;

the second fetch checking unit 120 is configured to fetch the data to be read from the DRAM by the NVMe and check the data to be read;

the third determining unit 130 is configured to determine whether the data to be read passes the verification;

the moving unit 140 is configured to move data to be read to the host cache.

And the NVMe takes out the data to be written from the host or moves the data to be read to the host cache through the PCIE interface.

Wherein the processing unit 80 comprises: a generation check module 81, a determination module 82, a return module 83, and a transfer reset module 84;

the generation and verification module 81 is configured to regenerate the command sent by the host and verify the regenerated command;

the judging module 82 is configured to judge whether the regenerated command check passes;

the return module 83 is configured to return to execute whether the command sent by the host is a write command;

the transfer reset module 84 is configured to transfer the notification to the host that the device has an error, and the host resets the device.

It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation process of the apparatus for improving the reliability of the data path of the solid state disk and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided herein.

The above-mentioned apparatus for improving the reliability of the data path of the solid state disk may be implemented in the form of a computer program, and the computer program may be run on a computer device as shown in fig. 6.

Referring to fig. 6, fig. 6 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 6, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a method for improving reliability of a data path of a solid state disk.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the computer program 5032 in the non-volatile storage medium 503 to run, and when the computer program 5032 is executed by the processor 502, the processor 502 may be enabled to perform a method for improving the reliability of the data path of the solid state disk.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 6 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

It should be understood that, in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions, which when executed by a processor, implement the above-mentioned method for improving reliability of data path of a solid state disk.

The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.

Claims

1. The method for improving the reliability of the data path of the solid state disk is characterized by comprising the following steps:

NVMe receives a command sent by a host;

judging whether a command sent by a host is a write command;

judging whether the data to be written passes the verification;

if yes, writing the data to be written into the flash memory;

if not, error processing is carried out.

2. The method for improving the reliability of the data path of the solid state disk according to claim 1, wherein in the step "judging whether the command sent by the host is a write command", if not, the NVMe transmits the command sent by the host to the FTL;

NVMe takes out data to be read from the DRAM and checks the data to be read;

judging whether the data to be read passes the verification;

if yes, moving the data to be read to a host cache;

if not, error processing is carried out.

3. The method according to claim 2, wherein the NVMe fetches data to be written from the host or moves data to be read to the host cache via the PCIE interface.

4. The method for improving reliability of data path of solid state disk according to claim 3, wherein the error handling comprises the following steps:

judging whether the regenerated command check passes;

5. Promote device of solid state hard drive data path reliability, its characterized in that includes: the device comprises a receiving unit, a first judging unit, a taking-out and adding storage transfer unit, an updating transfer unit, a first taking-out checking unit, a second judging unit, a writing-in unit and a processing unit;

the writing unit is used for writing data to be written into the flash memory;

6. The apparatus for improving reliability of data path of solid state disk according to claim 5, further comprising: the transfer unit is used for inquiring and updating the transfer unit, reading the added storage transfer unit, the second taking-out verification unit, the third judgment unit and the moving unit;

and the moving unit is used for moving the data to be read to the host cache.

7. The apparatus according to claim 6, wherein the NVMe fetches data to be written from the host or moves data to be read to the host cache via a PCIE interface.

8. The apparatus for improving reliability of data path of solid state disk according to claim 7, wherein the processing unit comprises: the system comprises a generation checking module, a judgment module, a return module and a transmission resetting module;

9. A computer device, characterized in that the computer device comprises a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the method for improving reliability of data path of solid state disk according to any one of claims 1 to 4.

10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the method for improving reliability of a data path of a solid state disk according to any one of claims 1 to 4.