CN111615790B - Analog-to-digital converter, image sensor and handheld device - Google Patents
Analog-to-digital converter, image sensor and handheld device Download PDFInfo
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- CN111615790B CN111615790B CN201880083516.3A CN201880083516A CN111615790B CN 111615790 B CN111615790 B CN 111615790B CN 201880083516 A CN201880083516 A CN 201880083516A CN 111615790 B CN111615790 B CN 111615790B
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Abstract
An analog-to-digital converter (100) for converting a plurality of pixel column sensing information from an analog signal to a plurality of digital signals, respectively, the analog-to-digital converter (100) comprising: a counter (104) for generating count information and reflecting a plurality of bits output at said counter (104); a ramp signal generator (102) for generating a ramp signal; and a plurality of analog-to-digital conversion units including: a comparator (106) for comparing the corresponding pixel column sensing information with the ramp signal; a plurality of sampling units, wherein each sampling unit determines whether to sample a corresponding counter (104) output bit and output a corresponding digital signal according to an enable input of the sampling unit; and an enable information generation unit (108) for generating enable information according to the digital signal output by the sampling unit corresponding to the least significant bit of the plurality of bits.
Description
Technical Field
The present disclosure relates to circuits, and more particularly to an analog-to-digital converter, and a related image sensor and a handheld device.
Background
An analog-to-digital converter in an image sensor is used to convert an analog signal sensed by a pixel circuit into a digital signal, the pixel circuit includes a plurality of pixel columns, and if the analog-to-digital conversion is performed for each pixel column, noise immunity can be effectively improved. One important dominant factor in integrated circuit design is the power consumption of the integrated circuit, so good circuit design requires that the power consumption of any circuit be minimized as much as possible. Therefore, further improvements and innovations are needed to meet this need.
Disclosure of Invention
One objective of the present application is to disclose an analog-to-digital converter, a related image sensor and a handheld device, so as to solve the above problems.
An embodiment of the present application discloses an analog-to-digital converter for converting a plurality of pixel column sensing information from analog signals to a plurality of digital signals, respectively, the analog-to-digital converter comprising: a counter for generating count information and reflecting a plurality of bits output at the counter; a ramp signal generator for generating a ramp signal; and a plurality of analog-to-digital conversion units corresponding to the plurality of pixel rows for sensing information, wherein each analog-to-digital conversion unit is coupled to the counter and the ramp signal generator, and comprises: the comparator is used for comparing the sensing information of the corresponding pixel row with the ramp signal and generating a comparison result according to the comparison result; a plurality of sampling units respectively coupled to a plurality of bits of the counter, wherein each sampling unit determines whether to sample a corresponding counter output bit and output a corresponding digital signal according to an enable input of the sampling unit, wherein the enable input of the sampling unit corresponding to the least significant bit of the plurality of bits is coupled to the comparison result; and an enable information generating unit for generating enable information according to the digital signal output by the sampling unit corresponding to the least significant bit of the plurality of bits, wherein enable inputs of the plurality of sampling units other than the least significant bit of the plurality of bits are coupled to the enable information.
An embodiment of the present application discloses an analog-to-digital converter for converting sensing information of a plurality of pixel columns from analog signals to a plurality of digital signals, respectively, the analog-to-digital converter comprising: a counter for generating count information and reflecting a plurality of bits output at the counter; a first ramp signal generator for generating a first ramp signal; a second ramp signal generator for generating a second ramp signal, wherein the second ramp signal leads the first ramp signal by a certain time; and a plurality of analog-to-digital conversion units corresponding to the plurality of pixel rows for sensing information, wherein each analog-to-digital conversion unit is coupled to the counter and the ramp signal generator, and comprises: a first comparator for comparing the corresponding pixel row sensing information with the first ramp signal and generating a first comparison result accordingly; the second comparator is used for comparing the corresponding pixel row sensing information with the second ramp signal and generating a second comparison result; and each sampling unit determines whether to sample the corresponding counter output bit and output the corresponding digital signal according to the first comparison result and the second comparison result.
An embodiment of the present application discloses an image sensor, including: a plurality of pixels including a plurality of pixel columns and generating a plurality of pixel sensing column information; and the analog-to-digital converter is used for converting the sensing information of the pixel columns into a plurality of digital signals from analog signals respectively.
An embodiment of the present application discloses a handheld device for sensing a fingerprint of a specific object, comprising: a display screen assembly; and the image sensor is used for obtaining the fingerprint information of the specific object
The analog-to-digital converter disclosed by the application has lower power consumption and does not influence the efficiency.
Drawings
Fig. 1 is a schematic diagram of an embodiment of an image sensor according to the present application.
Fig. 2 is a schematic diagram of a first embodiment of an analog-to-digital converter according to the present application.
Fig. 3 is a schematic diagram of an embodiment of an enable information generation unit.
Fig. 4 is a timing diagram of the analog-to-digital converter shown in fig. 2.
Fig. 5 is another timing diagram of the analog-to-digital converter shown in fig. 2.
Fig. 6 is a diagram of an analog-to-digital converter according to a second embodiment of the present invention.
Fig. 7 is a timing diagram of the analog-to-digital converter shown in fig. 6.
Fig. 8 is a schematic diagram of a third embodiment of the analog-to-digital converter of the present application.
Fig. 9 is a timing diagram of the analog-to-digital converter shown in fig. 8.
Fig. 10 is another timing diagram of the analog-to-digital converter shown in fig. 8.
FIG. 11 is a schematic view of an embodiment of a handheld device of the present application.
Wherein the reference numerals are as follows:
100. 200, 300 analog-to-digital converter
102. 202 ramp signal generator
104 counter
106. 206 comparator
Ln-1-L0 sampling unit
108 enable information generating unit
110. 112, 210, 212, 310, 312 analog-to-digital conversion unit
120 pixel(s)
122. 124 pixel column
108_2 exclusive OR circuit
108_4 delay unit
204 logic unit
400 hand-held device
402 display screen assembly
900 image sensor
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in various embodiments. Such reuse is for brevity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages herein used (e.g., to describe amounts of materials, length of time, temperature, operating conditions, ratio of amounts, and the like) are modified by "about" in addition to the experimental examples, or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits and the number resulting from applying ordinary rounding techniques. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
The analog-to-digital converter disclosed in the present application has low power consumption and does not affect performance, and the technical contents of the analog-to-digital converter and related image sensor and handheld device are described in detail below with reference to a plurality of embodiments and drawings.
Referring to fig. 1, fig. 1 is a schematic view of an embodiment of an image sensor according to the present disclosure. The image sensor 900 of fig. 1 includes a plurality of pixels 120 and an analog-to-digital converter 100/200/300, i.e., the analog-to-digital converter may be an analog-to-digital converter 100 shown in fig. 2, an analog-to-digital converter 200 shown in fig. 6, or an analog-to-digital converter 300 shown in fig. 8. The plurality of pixels 120 are arranged in a matrix form, include a plurality of (e.g., m + 1) pixel columns 122, 124, …, and generate a plurality of pixel column sensing information pixel _ col0, pixel _ col1, … pixel _ col, respectively. Image sensor 900 may be used in any suitable application, and in the embodiment of FIG. 11, image sensor 900 is used to implement optical underscreen fingerprint sensing for handheld device 400.
The pixels 120 are coupled to the adc 100/200/300, and specifically, in the embodiment, the pixel rows 122, 124, and … are respectively coupled to the adc units 110, 112, and … in the adc 100/200/300. In other words, the plurality of analog-to- digital conversion units 110, 112, … respectively correspond to the plurality of pixel column sensing information pixel _ col0, pixel _ col1, … pixel _ col, the plurality of pixel column sensing information pixel _ col0, pixel _ col1, … pixel _ col are analog signals, and the plurality of analog-to- digital conversion units 110, 112, … respectively convert the analog signals into a plurality of digital signals D _ col0[ n-1:0], D _ col1[ n-1:0], … D _ col [ n-1:0], wherein each digital signal has n bits, and n is an integer greater than 1.
Fig. 2 is a schematic diagram of a first embodiment of an analog-to-digital converter according to the present application. The analog-to-digital converter 100 of fig. 2 includes a counter 104, a ramp signal generator 102, and a plurality of analog-to- digital conversion units 110, 112, …. The counter 104 generates count information in response to a plurality of bits C [ n-1:0] output by the counter 104]For example, the counter 104 sequentially increments from 0 to generate binary outputs of 0, 1, 2, … in bits C [ n-1: 0%]Or from 2 n -1 starts to decrement sequentially to generate 2 n -1、2 n -2、2 n -binary output of 3, …. The counter 104 may be a general binary counter, or may be in other forms such as a gray code based counter.
The ramp signal generator 102 generates a linear up-ramp signal Vramp, for example, the ramp signal generator 102 generates a linear up-ramp signal Vramp from low level to high level, or generates a linear down-ramp signal Vramp from high level to low level.
As shown in FIG. 2, the bits C [ n-1:0] are coupled to the analog-to- digital conversion units 110, 112, …, so the counter 104 can be understood as a global counter. Each of the plurality of analog-to-digital converting units 110, 112, … includes a plurality of sampling units Ln-1 to L0, in this embodiment, the plurality of sampling units Ln-1 to L0 are latches, but the type of latch is not limited, and in some embodiments, the plurality of sampling units Ln-1 to L0 may be other types of sampling units as long as the function is capable of sampling the input signal. The inputs D of the sampling units Ln-1 through L0 are coupled to the bits C [ n-1:0] outputted by the counter 104, respectively, where C [0] is the least significant bit outputted by the counter 104, C [0] is coupled to the input D of the sampling unit L0, and so on, and C [ n-1] is coupled to the input D of the sampling unit Ln-1.
In addition, the plurality of sampling units Ln-1 to L0 respectively have an enable input E, and the plurality of sampling units Ln-1 to L0 determine whether to enable (i.e., activate) according to the enable input E, that is, the plurality of sampling units Ln-1 to L0 determine whether to sample the input D according to the enable input E, for example, when the enable input E is high (logic "1"), the sampling units sample the input D.
Each of the plurality of analog-to- digital conversion units 110, 112, … further includes a comparator 106 and an enable information generation unit 108. The comparator 106 is used for comparing the ramp signal Vramp and the pixel column sensing information pixel _ col0, pixel _ col1, …, and accordingly generating a comparison result LE from the output of the comparator 106, which is coupled to the enable input E of the least significant bit sampling unit L0.
FIG. 4 is a timing diagram of the ADC unit 110 of the present application 100, and it can be seen from FIG. 4 that when the ramp signal Vramp is not greater than the pixel column sensing information pixel _ col0, the comparison result LE of the comparator 106 is high (logic "1"), the sampling unit L0 continuously samples the input D, i.e., C [0], and generates the digital signal D _ col0[0] corresponding to the least significant bit C [0] of the counter 104 at the output Q. When the ramp signal Vramp is greater than the pixel column sensing information pixel _ col0, i.e., at time T1, the comparison result LE of the comparator 106 goes low (logic "0"), so the sampling unit L0 stops sampling the input D, i.e., C [0], and generates the digital signal D _ col0[0] at the output Q, which is kept at the level at which the comparison result LE transits, e.g., in fig. 4, the comparison result LE transits when C [ n-1:0] is 30 (decimal), and the output Q of the sampling unit L0 keeps the output digital signal D _ col0[0] at low (logic "0").
The present embodiment reduces the enable time of the sampling units Ln-1 to L1 other than the sampling unit L0 by using the enable information generation unit 108, thereby reducing power consumption. As shown in FIG. 2, the enable information generating unit 108 generates the enable information LEPS according to the digital signal D _ col0[0] output by the sampling unit L0, as shown in FIG. 4, the rising edge and the falling edge of the digital signal D _ col0[0] trigger the enable information generating unit 108 to generate the enable information LEPS to a high level (logic "1") and maintain the enable information LEPS for less than one output period of the counter 104, so that the total enable time of each of the sampling units Ln-1-L1 is respectively less than the total enable time of the sampling unit L0 as a whole, i.e., the time for maintaining the enable information LEPS to the high level (logic "1") is less than the time for maintaining the comparison result LE to the high level (logic "1"). It should be noted that the time for each time the enable information LEPS is asserted to the high level (logic "1") generated by the rising edge and the falling edge of the digital signal D _ col0[0] is enough for the sampling units Ln-1 to L1 to sample C [ n-1:1] to ensure that no error occurs.
FIG. 3 is a diagram of an embodiment of the enable information generating unit 108, wherein the enable information generating unit 108 includes a delay unit 108_4 and an XOR circuit 108_2, the delay unit 108_4 is used to delay the digital signal D _ col0[0] outputted by the sampling unit L0 and generate a delayed digital signal D _ col0_ D [0], and specifically, the delay unit 108_4 is used to control the time for which the enable information LEPS is maintained at a high level (logic "1") each time according to the rising edge and the falling edge of the digital signal D _ col0[0 ]. The XOR circuit 108_2 is used to generate the enable information LEPS according to the digital signal D _ col0[0] and the delayed digital signal D _ col0_ D [0 ]. It should be noted that the implementation manner of the enabling information generating unit 108 in the present application is not limited to fig. 3, and all embodiments are within the scope of the present application as long as similar functions can be achieved.
FIG. 5 is another timing diagram of the ADC 100 according to the present invention, taking the ADC unit 110 as an example, as shown in FIG. 5, only the falling edge of the digital signal D _ col0[0] triggers the enable information generating unit 108 to generate the enable information LEPS to a high level (logic "1") for less than one output cycle time of the counter 104, but enough for the sampling units Ln-1-L1 to sample C [ n-1:1] to ensure no error occurs. Therefore, in general, the total enable time of each of the sampling units Ln-1 to L1 is less than half of the total enable time of each of the sampling units Ln-1 to L1 of FIG. 4, i.e., the time for the enable information LEPS of FIG. 5 to remain at the high level (logic "1") is less than half of the time for the enable information LEPS of FIG. 4 to remain at the high level (logic "1"), further reducing power consumption.
Fig. 6 is a diagram of an analog-to-digital converter according to a second embodiment of the present invention. The most significant difference between the adc 200 of fig. 6 and the adc 100 of fig. 2 is that the adc 200 of fig. 6 further includes a second ramp signal generator 202, and the plurality of adc units 210, 212, … are different from the plurality of adc units 110, 112, … of fig. 2.
The second ramp signal generator 202 is used for generating a second ramp signal VrampPre, the second ramp signal VrampPre is substantially the same as the first ramp signal Vramp, and the difference is that the second ramp signal VrampPre leads the first ramp signal Vramp by a specific time, and the specific time is greater than the output period of the counter 104, fig. 7 is a timing diagram of the analog-to-digital converter 200 of the present application, for example, an analog-to-digital conversion unit 210, and as can be seen from fig. 7, the second ramp signal VrampPre leads the first ramp signal Vramp by about two output periods of the counter 104. Therefore, the plurality of sampling units Ln-1L 0 may be allowed to sample C [ n-1:0] about two output cycles of the counter 104, i.e., the time T0, before the time T1 at which the sampling is finished, to further reduce power consumption.
Compared to the adc units 110, 112, …, each of the adc units 210, 212, … includes the second comparator 206 and the logic unit 204 in addition to the first comparator 106, and the adc units 210, 212, … do not include the enable information generation unit 108. The comparator 106 is used for comparing the ramp signal Vramp with one of the plurality of pixel column sensing information pixel _ col0, pixel _ col1, …, and accordingly generating a comparison result LE from the output of the comparator 106, wherein the comparison result LE of the comparator 106 is at a high level (logic "1") when the ramp signal Vramp is not greater than the pixel column sensing information pixel _ col 0; the comparator 206 is used for comparing the second ramp signal VrampPre with one of the pixel column sensing information pixel _ col0, pixel _ col1 and …, for example, for comparing the second ramp signal VrampPre with the pixel column sensing information pixel _ col0, and generating a comparison result LEPre according to an output of the comparator 206, wherein the comparison result LEPre of the comparator 206 is at a high level (logic "1") when the second ramp signal VrampPre is greater than the pixel column sensing information pixel _ col 0.
That is, the comparison result LEPre of the comparator 206 serves as a signal for predicting the transition of the comparison result LE of the comparator 106, and the comparison result LEPre of the comparator 206 is reflected in advance about two cycles of the output of the counter 104 before the transition of the comparison result LE of the comparator 106. By combining the comparison result LE and the comparison result LEPre by the logic unit 204, each of the sampling units Ln-1 to L0 can be enabled only about two cycles of the output of the counter 104 before the comparison result LE of the comparator 106 transitions to further reduce power consumption.
In this embodiment, the logic unit 204 comprises an AND gate having two inputs respectively coupled to the comparison result LE and the comparison result LEPre, and outputting the enable information LEDS to the enable input E of each of the sampling units Ln-1L 0. As can be seen from FIG. 7, the enable information LEDS is high (logic "1") between the times T0 and T1, so that the sampling units Ln-1L 0 are not enabled before the time T0 and after the time T1, and only between the times T0 and T1 is C [ n-1:0] sampled.
Fig. 8 is a schematic diagram of a third embodiment of the analog-to-digital converter of the present application. The analog-to-digital converter 300 of fig. 8 combines the analog-to-digital converter 100 of fig. 2 and the analog-to-digital converter 200 of fig. 6. In detail, the analog-to-digital converter 300 of fig. 8 includes a first ramp signal generator 102 and a second ramp signal generator 202, the first ramp signal generator 102 is configured to generate a first ramp signal Vramp, the second ramp signal generator 202 is configured to generate a second ramp signal VrampPre, the second ramp signal VrampPre is substantially the same as the first ramp signal Vramp, and the difference is that the second ramp signal VrampPre leads the first ramp signal Vramp by a specific time, and the specific time is greater than the output period of the counter 104.
The analog-to-digital converter 300 of fig. 8 further includes a plurality of analog-to- digital conversion units 310, 312, …, each of which includes a second comparator 206, a logic unit 204, and an enable information generating unit 108 in addition to the first comparator 106, wherein the first comparator 106, the second comparator 206, and the logic unit 204 generate enable information LEDS to an enable input E of the sampling unit L0. The enable information generating unit 108 generates enable information LEPS to sampling units Ln-1 to L1 other than the sampling unit L0 based on the digital signal D _ col0[0] output from the sampling unit L0.
Fig. 9 is a timing diagram of the adc 300 according to the present invention, taking the adc unit 310 as an example, and it can be seen from fig. 9 that the total enabling time of the sampling units Ln-1 to L0 of the adc 300 of fig. 8 is shortest compared to fig. 4 and 7. FIG. 10 is a timing diagram of the ADC 300 according to the present invention, taking the ADC unit 310 as an example, different from the timing diagram shown in FIG. 9, in that only the falling edge of the digital signal D _ col0[0] triggers the enable information generating unit 108 to generate the enable information LEPS to a high level (logic "1") and maintains the enable information LEPS to be less than one output cycle time of the counter 104, compared to FIG. 9, the total enable time of the sampling units Ln-1L 0 of the ADC 300 of FIG. 10 is shorter.
FIG. 11 is a schematic view of an embodiment of a handheld device of the present application. The handheld device 400 includes a display screen assembly 402 and an image sensor 900. The handheld device 400 may be used for optical underscreen fingerprint sensing to sense a fingerprint of a particular object. The handheld device 400 can be any handheld electronic device such as a smart phone, a personal digital assistant, a handheld computer system, or a tablet computer. The display screen assembly 402 may include a display panel and a protective cover plate, the protective cover plate is disposed above the display panel, and the image sensor 900 is disposed below the display panel, in this embodiment, the display panel may be an organic electroluminescent display panel (OLED), but the present application is not limited thereto.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (14)
1. An analog-to-digital converter for converting sensing information of a plurality of pixel columns from analog signals to a plurality of digital signals, respectively, the analog-to-digital converter comprising:
a counter for generating count information and reflecting a plurality of bits (bits) output from the counter;
a ramp signal generator for generating a ramp signal; and
a plurality of analog-to-digital conversion units corresponding to the plurality of pixel rows for sensing information, wherein each analog-to-digital conversion unit is coupled to the counter and the ramp signal generator, and comprises:
the comparator is used for comparing the sensing information of the corresponding pixel row with the ramp signal and generating a comparison result according to the comparison result;
a plurality of sampling units respectively coupled to a plurality of bits of the counter, wherein each sampling unit determines whether to sample a corresponding counter output bit and output a corresponding digital signal according to an enable input of the sampling unit, wherein the enable input of the sampling unit corresponding to the least significant bit of the plurality of bits is coupled to the comparison result; and
and an enable information generating unit for generating enable information according to the digital signal output by the sampling unit corresponding to the least significant bit of the plurality of bits, wherein enable inputs of the sampling units other than the least significant bit of the plurality of bits are coupled to the enable information, wherein the sampling unit corresponding to the least significant bit of the plurality of bits determines whether to stop sampling the corresponding counter output bit according to the comparison result, and the total enable time of each of the sampling units other than the least significant bit of the plurality of bits is less than the total enable time of the sampling unit corresponding to the least significant bit of the plurality of bits.
2. The analog-to-digital converter according to claim 1, wherein the enable information generating unit generates the enable information according to rising and falling edges of the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits.
3. The analog-to-digital converter of claim 2, wherein the enable information generating unit comprises:
a delay unit for delaying the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits and generating a delayed signal; and
and the exclusive-OR circuit is used for generating the enabling information according to the delay signal and the digital signal output by the sampling unit corresponding to the least significant bit in the plurality of bits.
4. The analog-to-digital converter according to claim 1, wherein the enable information generating unit generates the enable information according to one of a rising edge and a falling edge of the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits.
5. An analog-to-digital converter for converting a plurality of pixel column sensing information from an analog signal to a plurality of digital signals, respectively, the analog-to-digital converter comprising:
a counter for generating count information and reflecting a plurality of bits output at the counter;
a first ramp signal generator for generating a first ramp signal;
a second ramp signal generator for generating a second ramp signal, wherein the second ramp signal leads the first ramp signal by a certain time; and
a plurality of analog-to-digital conversion units corresponding to a plurality of pixel rows for sensing information, wherein each analog-to-digital conversion unit is coupled to the counter, the first ramp signal generator and the second ramp signal generator, and comprises:
a first comparator for comparing the corresponding pixel row sensing information with the first ramp signal and generating a first comparison result accordingly;
the second comparator is used for comparing the corresponding pixel row sensing information with the second slope signal and generating a second comparison result according to the second slope signal;
and a plurality of sampling units respectively coupled to a plurality of bits of the counter, wherein each sampling unit determines whether to sample a corresponding counter output bit and output a corresponding digital signal according to the first comparison result and the second comparison result, wherein each sampling unit determines whether to start and stop sampling the corresponding counter output bit and output the corresponding digital signal according to the first comparison result and the second comparison result, and the specific time is longer than an output period of the counter.
6. The analog-to-digital converter of claim 5, wherein each analog-to-digital conversion unit further comprises:
the enable information generating unit is used for generating enable information according to the digital signal output by the sampling unit corresponding to the least significant bit of the plurality of bits, wherein the plurality of sampling units corresponding to the bits except the least significant bit of the plurality of bits determine whether to sample the corresponding counter output bit and output the corresponding digital signal according to the enable information.
7. The analog-to-digital converter of claim 6, wherein a total enable time for each of the plurality of sampling units other than the least significant bit of the plurality of bits is less than a total enable time for the sampling unit corresponding to the least significant bit of the plurality of bits.
8. The analog-to-digital converter of claim 6, wherein the enable information generating unit generates the enable information according to rising and falling edges of the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits.
9. The analog-to-digital converter of claim 8, wherein the enable information generating unit comprises:
a delay unit for delaying the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits and generating a delayed signal; and
and the exclusive-OR circuit is used for generating the enabling information according to the delay signal and the digital signal output by the sampling unit corresponding to the least significant bit in the plurality of bits.
10. The analog-to-digital converter according to claim 6, wherein the enable information generating unit generates the enable information according to one of a rising edge and a falling edge of the digital signal output from the sampling unit corresponding to the least significant bit among the plurality of bits.
11. An image sensor, comprising:
a plurality of pixels including a plurality of pixel columns and generating a plurality of pixel sensing column information; and the analog-to-digital converter of any one of claims 1 to 10, for converting the plurality of pixel column sensing information from analog signals to a plurality of digital signals, respectively.
12. A handheld device for sensing a fingerprint of a specific object, comprising:
a display screen assembly; and
the image sensor of claim 11, to obtain fingerprint information of the particular object.
13. The handheld device of claim 12 wherein the display screen assembly comprises a display panel and a protective cover.
14. The handheld device of claim 13, wherein the display panel has a first side and a second side opposite the first side, the protective cover is disposed on the second side of the display panel, and the image sensor is disposed on the first side of the display panel such that the display panel is between the image sensor and the protective cover.
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| PCT/CN2018/122524 WO2020124518A1 (en) | 2018-12-21 | 2018-12-21 | Analog-to-digital converter, image sensor and handheld apparatus |
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| KR102057575B1 (en) * | 2013-07-25 | 2019-12-20 | 삼성전자주식회사 | Image sensor and control method thereof |
| KR102431248B1 (en) * | 2016-01-29 | 2022-08-11 | 에스케이하이닉스 주식회사 | Analog-digital converting apparatus and method, and cmos image sensor thereof |
| CN107147859B (en) * | 2017-06-06 | 2019-10-18 | 长春长光辰芯光电技术有限公司 | A kind of high speed analog-to-digital conversion device applied in imaging sensor |
| WO2019113772A1 (en) * | 2017-12-12 | 2019-06-20 | 深圳市汇顶科技股份有限公司 | Method for analog-digital conversion and analog-digital converter |
| CN108551344B (en) * | 2018-03-29 | 2022-04-01 | 上海集成电路研发中心有限公司 | Double-sampling analog-to-digital conversion circuit |
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