CN111614235B - Wide bandgap MOSFET driving circuit - Google Patents
Wide bandgap MOSFET driving circuit Download PDFInfo
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- CN111614235B CN111614235B CN202010486521.8A CN202010486521A CN111614235B CN 111614235 B CN111614235 B CN 111614235B CN 202010486521 A CN202010486521 A CN 202010486521A CN 111614235 B CN111614235 B CN 111614235B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application relates to the field of MOS tube driving, in particular to a wide bandgap MOSFET tube driving circuit, which comprises: the signal generation module is used for reconstructing the edges of the input PWM signals by utilizing a plurality of groups of reconstruction pulse signals to generate PWM signals with step waveforms at the edges; the signal processing module is used for processing the generated PWM signal into a driving signal of the wide band gap MOSFET; the signal generating module is connected with the input end of the signal processing module. The switching performance of the wide band gap MOSFET can be improved, the phenomena of grid voltage oscillation, voltage spike overshoot, ringing and the like are effectively avoided, and the anti-interference capability is strong.
Description
Technical Field
The application relates to the field of MOS tube driving, in particular to a wide bandgap MOSFET tube driving circuit.
Background
Silicon carbide and gallium nitride materials are widely used because of the advantages of large forbidden bandwidth, high critical breakdown field strength, large thermal conductivity, high saturated electron drift velocity, low dielectric constant and the like. In recent years, commercial wide bandgap MOSFET transistors (SiC, gaN, etc.) have been proposed by CREE corporation in the united states and ROHM corporation in japan, etc., which have excellent properties such as low on-resistance, high thermal conductivity, high breakdown voltage, high saturation speed, etc., and which can improve the conversion efficiency of a power converter and reduce the power density thereof, save space, reduce weight, and reduce heat dissipation requirements. The wide-band-gap MOSFET has the characteristic of smaller positive threshold voltage and negative safety voltage, is easily influenced by the Miller effect in the high-frequency switching process, causes the voltage oscillation of the grid electrode to cause the false switching on or the breakdown of the grid electrode and the source electrode, and damages the switching tube when serious.
In addition, the wide band gap MOSFET is applied to high-frequency high-power occasions, and voltage spike overshoot, ringing and other phenomena are generated in the switching process of the wide band gap MOSFET, so that the system operation is seriously endangered. Unlike conventional silicon devices, the gate turn-on voltage of the wide bandgap MOSFET must reach 18-20V to be fully turned on, thereby exerting the advantage of low turn-on loss.
At present, research on the driver and switching characteristics of wide bandgap MOSFETs has become a hotspot. How to improve the switching performance of the wide bandgap MOSFET is very critical in designing a driver with the characteristics of strong anti-interference capability, small switching peak, high reliability and the like.
Disclosure of Invention
The wide-band-gap MOSFET driving circuit provided by the application can improve the switching performance of the wide-band-gap MOSFET, effectively avoid the phenomena of grid voltage oscillation, voltage spike overshoot, ringing and the like, and has strong anti-interference capability.
The application provides a wide bandgap MOSFET driving circuit, comprising:
the signal generation module is used for reconstructing the edges of the input PWM signals by utilizing a plurality of groups of reconstruction pulse signals to generate PWM signals with step waveforms at the edges;
the signal processing module is used for processing the generated PWM signal into a driving signal of the wide band gap MOSFET;
the signal generating module is connected with the input end of the signal processing module.
Further, the signal generating module includes:
the digital signal processor is used for tracking the input PWM signals and generating a plurality of groups of reconstruction pulse signals for reconstructing the input PWM signals;
the gain amplifier is used for carrying out voltage amplification on each group of reconstruction pulse signals;
the signal superposition processor is used for superposing the amplified reconstructed pulse signals to form PWM signals with step waveforms at the edges;
the digital signal processor, the gain amplifier and the signal superposition processor are connected in sequence.
Still further, the reconstructing pulse signal includes: rising and falling reconstruction pulses;
the digital signal processor is specifically configured to:
the rising edge and the falling edge of an input pulse PWM signal are tracked by adopting a hardware input synchronous locking mechanism and a micro-edge positioning technology;
the ascending reconstruction pulse and the descending reconstruction pulse are correspondingly constructed in sequence according to the time sequence.
Still further, the signal generating module further includes:
a buffer unit for generating a tracking signal tracking the rising and falling edges of the input PWM signal and transmitting to the digital signal processor;
the buffer unit is connected with the digital signal processor.
In the above technical solution, the signal processing module includes:
a PWM level conversion circuit for converting a PWM signal having a step waveform into a positive and negative level PWM signal;
the high-frequency signal amplifying circuit is used for amplifying the positive and negative level PWM signals to reach the amplitude value for driving the wide band gap MOSFET;
the high-speed signal isolation circuit is used for carrying out electric isolation transmission and output current enhancement on the amplified positive and negative level PWM signals to obtain isolated PWM signals;
the output push-pull circuit is used for further improving the output current capacity of the isolated PWM signal;
the PWM level conversion circuit, the high-frequency signal amplification circuit, the high-speed signal isolation circuit and the output push-pull circuit are sequentially connected.
Further, the signal processing module further includes:
the linear power supply conversion circuit is used for supplying power to the PWM level conversion circuit;
the linear power supply conversion circuit is connected with the PWM level conversion circuit;
the PWM level conversion circuit includes: a first resistor, a second resistor, a third resistor and a fourth resistor;
one end of the first resistor is connected with the output end of the signal generating module, and the other end of the first resistor is connected with one end of the third resistor;
the other end of the third resistor is connected with the input end of the high-frequency signal amplifying circuit;
one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is connected with the output end of the linear power supply conversion circuit;
one end of the fourth resistor is connected with the other end of the third resistor, and the other end of the fourth resistor is connected with the output end of the linear power supply conversion circuit.
Still further, the high-frequency signal amplifying circuit includes: a high-speed operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a third capacitor and a fourth capacitor;
one end of the fifth resistor is grounded, and the other end of the fifth resistor is connected with the pin 2 of the high-speed operational amplifier;
one end of the seventh resistor is connected with the output end of the PWM level conversion circuit, and the other end of the seventh resistor is connected with the pin 3 of the high-speed operational amplifier;
the pin 2 of the high-speed operational amplifier is connected with the sixth resistor and the first capacitor in sequence and then connected with the output end of the high-frequency signal amplifying circuit;
the pin 3 of the high-speed operational amplifier is connected with an eighth resistor and then grounded;
the pin 4 of the high-speed operational amplifier is respectively connected with a-8V power supply and grounded through a fourth capacitor;
the pin 6 of the high-speed operational amplifier is connected with the output end of the high-frequency signal amplifying circuit;
and a pin 7 of the high-speed operational amplifier is respectively connected with a +23V power supply and grounded through a third capacitor.
Still further, the high-speed signal isolation circuit includes: a photo coupler and a ninth resistor;
one end of the ninth resistor is connected with the output end of the high-frequency signal amplifying circuit, and the other end of the ninth resistor is connected with the pin 2 of the photoelectric coupler;
and a pin 1 of the photoelectric coupler is connected with a +23V power supply, a pin 4 of the photoelectric coupler is connected with a-8V power supply, and a pin 6 of the photoelectric coupler is connected with an output push-pull circuit.
Still further, the output push-pull circuit includes: the first transistor, the second transistor, the first transient diode, the second transient diode, the fifth capacitor, the sixth capacitor, the tenth resistor, the eleventh resistor, the twelfth resistor and the thirteenth resistor;
one end of the tenth resistor is connected with the pin 6 of the photoelectric coupler, and the other end of the tenth resistor is respectively connected with the base electrode of the first triode and the base electrode of the second triode;
the collector of the first triode is respectively connected with a +23V power supply and grounded through a fifth capacitor, and the emitter is connected with the grid of the wide band gap MOSFET through an eleventh resistor;
the emitter of the second triode is connected with the grid electrode of the wide band gap MOSFET through a twelfth resistor, and the collector of the second triode is respectively connected with a-8V power supply and grounded through a sixth capacitor;
one end of the thirteenth resistor is connected with one end of the eleventh resistor far away from the first triode, and the other end of the thirteenth resistor is connected with a-8V power supply;
the anodes of the first transient diode and the second transient diode are respectively connected;
the cathode of the first transient diode is connected with the grid electrode of the wide bandgap MOSFET;
and the cathode of the second transient diode is connected with the source electrode of the wide bandgap MOSFET.
Still further, the linear power conversion circuit includes: the second capacitor, the third triode, the fourteenth resistor and the third transient diode;
the input end of the linear power supply conversion circuit is respectively connected with a-8V power supply, the collector electrode of the third triode and one end of the fourteenth resistor;
the emitter of the third triode is connected with a-5V output power supply, and the base of the third triode is respectively connected with the other end of the fourteenth resistor and the anode of the third transient diode;
the cathode of the third transient diode is grounded;
one end of the second capacitor is connected with a-5V output power supply, and the other end of the second capacitor is grounded.
The signal generating module can be used for generating a PWM signal with a step waveform at the edge of a pulse switch, and then the signal processing module converts the PWM signal with the step waveform into a driving signal; thereby effectively reducing the peak voltage of the switch, the noise of the switch and the electromagnetic radiation.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of an embodiment of the present application;
FIG. 2 is a schematic waveform diagram of an input PWM signal and a falling reconstruction pulse according to an embodiment of the present application;
FIG. 3 is a schematic waveform diagram of an input PWM signal and amplified falling reconstruction pulse according to an embodiment of the present application;
FIG. 4 is a schematic waveform diagram of an input PWM signal and a rising reconstruction pulse according to an embodiment of the present application;
FIG. 5 is a schematic waveform diagram of an input PWM signal and amplified rising reconstruction pulse according to an embodiment of the present application;
FIG. 6 is a schematic diagram of waveforms of an input PWM signal and a PWM signal according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a signal processing module according to an embodiment of the present application;
fig. 8 is a schematic diagram of a linear power conversion circuit according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 1, the wide bandgap MOSFET driving circuit provided in this embodiment includes:
the signal generating module 1 is used for reconstructing the edges of the input PWM signals by utilizing a plurality of groups of reconstruction pulse signals to generate PWM signals with step waveforms at the edges;
the signal processing module 2 is used for processing the generated PWM signal into a driving signal of the wide bandgap MOSFET;
the signal generating module 1 is connected with the input end of the signal processing module 2.
In this embodiment, the signal generating module 1 is used to generate a PWM signal with a step waveform at the switching edge of the pulse, and then the signal processing module 2 converts the PWM signal with a step waveform at the edge into a driving signal; thereby effectively reducing the peak voltage of the switch, the noise of the switch and the electromagnetic radiation.
The signal generating module 1 includes:
a digital signal processor 11 for tracking the input PWM signal, generating a plurality of sets of reconstruction pulse signals for reconstructing the input PWM signal;
gain amplifier 12 for voltage amplifying each set of reconstructed pulse signals;
a signal superposition processor 13, configured to superimpose the amplified groups of reconstructed pulse signals to form a PWM signal with a step waveform at an edge;
the digital signal processor 11, the gain amplifier 12 and the signal superposition processor 13 are connected in sequence.
As shown in fig. 1, in the present embodiment, the model number of the digital signal processor 11 is TMS320F28335.
The reconstructed pulse signal includes: rising and falling reconstruction pulses;
as shown in fig. 1, 2 and 4, in this embodiment, the reconstructed pulse signal has six paths, which are respectively: HRPWM1 to HRPWM6; wherein, HRPWM1 to HRPWM3 are rising reconstruction pulses for reconstructing rising edges of the input PWM signal (PWM IN); HRPWM4 to HRPWM6 are falling reconstruction pulses for reconstructing falling edges of the input PWM signal. In this embodiment, HRPWM1, HRPWM2, HRPWM4 to HRPWM6 are five sets of narrow pulse signals, and HRPWM3 is also used to track the input PWM signal.
As shown in fig. 1 to 6, the digital signal processor 11 is specifically configured to:
the rising edge and the falling edge of an input pulse PWM signal are tracked by adopting a hardware input synchronous locking mechanism and a micro-edge positioning technology;
the ascending reconstruction pulse and the descending reconstruction pulse are correspondingly constructed in sequence according to the time sequence.
In the present embodiment, first, a reconstruction pulse signal for reconstructing an input PWM signal is sequentially generated in time sequence;
then, tracking is performed for the rising and falling edges of the input PWM signal:
when the rising edge of the input PWM signal is detected, rising reconstruction pulses which can be overlapped with the rising edge are obtained from the reconstruction pulse signals;
when a falling edge of an input PWM signal is detected, a falling reconstruction pulse which can coincide with the falling edge is acquired from each reconstruction pulse signal.
In the embodiment, a voltage source in a PSPICE program is adopted to simulate a multi-level reconstruction PWM signal rising edge or falling edge waveform, and a MOSFET and converter model is built to optimize a pulse edge; then, in order to meet the requirements of tracking and reconstructing pulse edges of various MOSFET driving signals such as silicon carbide, gallium nitride and the like, a digital signal processor TMS320F28335 is adopted, and a pulse width modulation wave HRPWM with 100ps precision is generated through an on-chip integrated enhanced pulse width modulator EPWM and a supporting hardware input synchronization interface EPWMSYNCI, so that PWM signal tracking with the frequency up to 1MHz is realized; and finally, sequentially generating six paths of high-precision reconstruction pulses for reconstructing PWM edges according to a time sequence, carrying out voltage amplification on each path of reconstruction pulses by adopting a wide dynamic range and high-speed digital control VGA interface, and then forming PWM signals with step waveforms at edges after signal superposition processing. The time sequence, the pulse width and the amplitude of the reconstruction pulse are preset according to PSPICE optimized data, and correction is carried out according to measured data.
The signal generating module 1 further includes:
a buffer unit 14 for generating a tracking signal tracking the rising and falling edges of the input PWM signal and transmitting to the digital signal processor 11;
the buffer unit 14 is connected to the digital signal processor 11.
As shown in fig. 1, the buffer unit 14 includes: in-phase Schmitt buffers SN74LVC1G17-Q1 and anti-phase Schmitt buffers SN74LVC1G14-Q1.
In order to realize the functions, the specific implementation scheme is as follows:
step 1, shaping an input PWM signal by adopting an in-phase Schmidt buffer SN74LVC1G17-Q1 and an anti-phase Schmidt buffer SN74LVC1G14-Q1 to form a pair of complementary PWM signals;
step 2, connecting a pair of formed complementary PWM signals into GPIO6 and GPIO32 pins of the digital signal processor 11;
step 3, configuring GPIO6 and GPIO32 pins as a hardware input synchronization interface EPWMSYNCI of an enhanced pulse width modulator module EPWM in the digital signal processor 11, so that a pair of formed complementary PWM signals are respectively used to track rising edges and falling edges of the input PWM signals;
step 4, setting the clock of the main timer of the digital signal processor 11 as the synchronous time base of the internal clock timer of each EPWM module; the timers corresponding to the six groups of reconstructed pulse signals adopt a continuous count-up mode;
step 5, setting a TBPRD period register value and a TBPHS comparison register value corresponding to the reconstructed pulse signal according to the pulse width, the time base and the pulse time sequence;
step 6, when the digital signal processor 11 detects the synchronous pulse signal at the rising edge time, the PHSDIR direction position 1 is used to obtain two groups of narrow pulse signals of HRPWM1 and HRPWM2 and HRPWM3 signals;
HRPWM3 is used to track the input PWM signal as shown in fig. 4;
step 7, when the dsp 11 detects the synchronization pulse signal at the falling edge time, generating a low level at the PHSDIR direction position 0 to obtain HRPWM signals of three groups of narrow pulses including HRPWM4, HRPWM5 and HRPWM6, as shown in fig. 2;
step 8, the gain amplifier 12 adopts a wide dynamic range, high-speed and digital control VGA interface to obtain pre-optimized parameters from a digital signal processor through a 6-bit parallel communication and latch interface, and performs voltage amplification on each path of reconstruction pulse signals, as shown in figures 3 and 5;
step 9, the signal superposition processor 13 superimposes the amplified reconstructed pulse signals to form a PWM signal having a step waveform at the edge, as shown in fig. 6.
As shown in fig. 7, the signal processing module 2 includes:
a PWM level conversion circuit 21 for converting a PWM signal having a step waveform into a positive and negative level PWM signal;
a high-frequency signal amplifying circuit 22 for amplifying the positive and negative level PWM signals to an amplitude value for driving the wide bandgap MOSFET;
the high-speed signal isolation circuit 23 is used for carrying out electric isolation transmission and output current enhancement on the amplified positive and negative level PWM signals to obtain isolated PWM signals;
an output push-pull circuit 24 for further improving the output current capability of the isolated PWM signal;
the PWM level conversion circuit 21, the high-frequency signal amplification circuit 22, the high-speed signal isolation circuit 23, and the output push-pull circuit 24 are connected in this order.
As shown in fig. 8, the signal processing module 2 further includes:
a linear power supply conversion circuit 25 for supplying power to the PWM level conversion circuit 21;
the linear power conversion circuit 25 is connected to the PWM level conversion circuit 21.
In this embodiment, firstly, the +15v input power supply generates +23v and-8v power supplies through the flyback converter, and then the-8v power supply generates a-5V accurate power supply through the linear power supply conversion circuit 25 to supply power to each circuit of the signal processing module 2. The digital signal processor 11, the gain amplifier 12 and the signal superposition processor 13 are adopted to generate a PWM signal with a step on the switch edge, and the PWM level conversion circuit 21, the high-frequency signal amplification circuit 22, the high-speed signal isolation circuit 23 and the output push-pull circuit 24 are designed to amplify the voltage, amplify the current and electrically isolate the PWM signal with the step on the switch edge generated by the front stage, and finally generate a driving signal of the wide band gap MOSFET.
The PWM level shift circuit 21 includes: a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4;
one end of the first resistor R1 is connected with the output end of the signal generation module 1, and the other end of the first resistor R1 is connected with one end of the third resistor R3;
the other end of the third resistor R3 is connected with the input end of the high-frequency signal amplifying circuit 22;
one end of the second resistor R2 is connected with the other end of the first resistor R1, and the other end of the second resistor R2 is connected with the output end of the linear power supply conversion circuit 25;
one end of the fourth resistor R4 is connected to the other end of the third resistor R3, and the other end is connected to the output end of the linear power conversion circuit 25.
The high-frequency signal amplifying circuit 22 includes: a high-speed operational amplifier U1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a third capacitor C3, and a fourth capacitor C4;
one end of the fifth resistor R5 is grounded, and the other end of the fifth resistor R5 is connected with the pin 2 of the high-speed operational amplifier U1;
one end of the seventh resistor R7 is connected with the output end of the PWM level conversion circuit 21, and the other end of the seventh resistor R7 is connected with the pin 3 of the high-speed operational amplifier U1;
the pin 2 of the high-speed operational amplifier U1 is connected with the sixth resistor R6 and the first capacitor C1 in sequence and then connected with the output end of the high-frequency signal amplifying circuit 22;
the pin 3 of the high-speed operational amplifier U1 is connected with an eighth resistor R8 and then grounded;
the pin 4 of the high-speed operational amplifier U1 is respectively connected with a-8V power supply and grounded through a fourth capacitor C4;
the pin 6 of the high-speed operational amplifier U1 is connected with the output end of the high-frequency signal amplifying circuit 22;
and a pin 7 of the high-speed operational amplifier U1 is respectively connected with a +23V power supply and grounded through a third capacitor C3.
The high-speed signal isolation circuit 23 includes: a photo coupler U2 and a ninth resistor R9;
one end of the ninth resistor R9 is connected with the output end of the high-frequency signal amplifying circuit 22, and the other end of the ninth resistor R9 is connected with the pin 2 of the photoelectric coupler U2;
pin 1 of the photocoupler U2 is connected with a +23V power supply, pin 4 is connected with a-8V power supply, and pin 6 is connected with an output push-pull circuit 24.
In the present embodiment, the model of the high-speed operational amplifier U1 is LM7121; the model of the photocoupler U2 is MOC3010.
The output push-pull circuit 24 includes: the first triode Q1, the second triode Q2, the first transient diode D1, the second transient diode D2, the fifth capacitor C5, the sixth capacitor C6, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13;
one end of the tenth resistor R10 is connected with the pin 6 of the photoelectric coupler U2, and the other end of the tenth resistor R is respectively connected with the base electrode of the first triode Q1 and the base electrode of the second triode Q2;
the collector of the first triode Q1 is respectively connected with a +23V power supply and grounded through a fifth capacitor C5, and the emitter is connected with the grid of the wide band gap MOSFET through an eleventh resistor R11;
the emitter of the second triode Q2 is connected with the grid electrode of the wide bandgap MOSFET through a twelfth resistor R12, and the collector of the second triode Q is respectively connected with a-8V power supply and grounded through a sixth capacitor C6;
one end of the thirteenth resistor R13 is connected with one end of the eleventh resistor R11 far away from the first triode Q1, and the other end of the thirteenth resistor R13 is connected with a-8V power supply;
anodes of the first transient diode D1 and the second transient diode D2 are respectively connected;
the cathode of the first transient diode D1 is connected with the grid electrode of the wide bandgap MOSFET;
and the cathode of the second transient diode D2 is connected with the source electrode of the wide-bandgap MOSFET.
In this embodiment, the PWM level conversion circuit 21 uses a pair of voltage dividing resistors to pull down the PWM signal having a step waveform at the edge of +5v/0V level to the-5V power supply, converts the PWM signal of positive level into the PWM signal of positive and negative level, and realizes accurate setting of the PWM signal output level by two-stage series adjustment. The high-frequency signal amplifying circuit 22 adopts a high-speed operational amplifier U1 to amplify the voltage of the PWM signal with positive and negative levels by a differential operational amplifier mode to reach +20V/-5V level suitable for driving the wide bandgap MOSFET. The high-speed signal isolation circuit 23 adopts a thyristor output photoelectric coupler U2 to carry out electric isolation transmission and output current enhancement on PWM signals with +20V/-5V level. The output push-pull circuit 24 employs a pair of transistors to increase the output current capability.
As shown in fig. 8, the linear power conversion circuit 25 includes: the second capacitor R2, the third triode Q3, the fourteenth resistor R14 and the third transient diode D3;
the input end of the linear power supply conversion circuit 25 is respectively connected with a-8V power supply, the collector electrode of the third triode Q3 and one end of a fourteenth resistor R14;
the emitter of the third triode Q3 is connected with a-5V output power supply, and the base of the third triode Q3 is respectively connected with the other end of the fourteenth resistor R14 and the anode of the third transient diode D3;
the cathode of the third transient diode D3 is grounded;
one end of the second capacitor R2 is connected with a-5V output power supply, and the other end of the second capacitor R2 is grounded.
In the present embodiment, the first transistor Q1 and the second transistor Q2 in the output push-pull circuit 24 are NPN transistors; the third transistor Q3 in the linear power conversion circuit 25 is a PNP transistor.
The present embodiment is realized as follows: firstly, a +15V input power supply generates a +23V power supply and a-8V power supply through a flyback converter, and then a-8V power supply generates a-5V accurate power supply through a linear power supply conversion circuit 25 to supply power to other circuits in the signal processing module 1.
The front stage captures an input PWM signal by using a digital signal processor 11 and generates a plurality of groups of reconstruction pulse signals for reconstructing the input pulse signals; then adopting a gain amplifier 12 to amplify the voltage of each group of reconstruction pulse signals; then, the reconstructed pulse signals of each group are superimposed by a signal superimposing processor (HC 4051) 13 to form a PWM signal with a step waveform at the switch edge.
The latter stage adopts PWM level conversion circuit 21 to convert the PWM signal with step waveform at the edge of +5V/0V level into positive and negative level PWM signal with same amplitude, and then converts into +20V/-5V level PWM signal by high frequency signal amplification circuit 22, and then makes signal isolation and output current amplification by high speed signal isolation circuit 23 and output push-pull circuit 24.
The miller effect of the MOSFET in the switching process can be effectively reduced by changing the gate series resistance in a combined way or adopting a method of forming a switch edge by multi-level superposition, and the like, but the flexibility of the methods is limited by carrying out parameter adjustment according to the MOSFET characteristics. In this embodiment, the driving circuit can reconfigure the pulse edge waveform of the PWM signal by software according to the MOSFET characteristics, so as to effectively reduce the switching spike voltage, and reduce the switching noise and electromagnetic radiation.
Compared with the prior art, the wide bandgap MOSFET driving circuit has the advantages that:
1. the switching spike voltage and the switching loss are effectively reduced;
2. the anti-interference capability is strong, safe and reliable;
3. the parameter adjustment is convenient, and the application range is wide.
It should be understood that the specific order or hierarchy of steps in the processes disclosed are examples of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, application lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate preferred embodiment of this application.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. As will be apparent to those skilled in the art; various modifications to these embodiments will be readily apparent, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, as used in the specification or claims, the term "comprising" is intended to be inclusive in a manner similar to the term "comprising," as interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean "non-exclusive or".
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.
Claims (8)
1. A wide bandgap MOSFET drive circuit comprising:
the signal generation module (1) is used for reconstructing the edges of the input PWM signals by utilizing a plurality of groups of reconstruction pulse signals to generate PWM signals with step waveforms at the edges;
the signal processing module (2) is used for processing the generated PWM signal into a driving signal of the wide bandgap MOSFET;
the signal generating module (1) is connected with the input end of the signal processing module (2);
the signal processing module (2) comprises:
a PWM level conversion circuit (21) for converting a PWM signal having a step waveform into a positive and negative level PWM signal;
the high-frequency signal amplifying circuit (22) is used for amplifying the positive and negative level PWM signals to reach the amplitude value for driving the wide band gap MOSFET;
the high-speed signal isolation circuit (23) is used for carrying out electric isolation transmission and output current enhancement on the amplified positive and negative level PWM signals to obtain isolated PWM signals;
an output push-pull circuit (24) for further improving the output current capability of the isolated PWM signal;
the PWM level conversion circuit (21), the high-frequency signal amplification circuit (22), the high-speed signal isolation circuit (23) and the output push-pull circuit (24) are sequentially connected;
the signal processing module (2) further comprises:
a linear power supply conversion circuit (25) for supplying power to the PWM level conversion circuit (21);
the linear power supply conversion circuit (25) is connected with the PWM level conversion circuit (21);
the PWM level conversion circuit (21) includes: a first resistor (R1), a second resistor (R2), a third resistor (R3) and a fourth resistor (R4);
one end of the first resistor (R1) is connected with the output end of the signal generation module (1), and the other end of the first resistor is connected with one end of the third resistor (R3);
the other end of the third resistor (R3) is connected with the input end of the high-frequency signal amplifying circuit (22);
one end of the second resistor (R2) is connected with the other end of the first resistor (R1), and the other end of the second resistor is connected with the output end of the linear power supply conversion circuit (25);
one end of the fourth resistor (R4) is connected with the other end of the third resistor (R3), and the other end of the fourth resistor is connected with the output end of the linear power supply conversion circuit (25).
2. The wide bandgap MOSFET drive circuit according to claim 1, wherein said signal generation module (1) comprises:
a digital signal processor (11) for tracking the input PWM signal, generating a plurality of sets of reconstructed pulse signals for reconstructing the input PWM signal;
a gain amplifier (12) for voltage-amplifying each set of reconstructed pulse signals;
a signal superposition processor (13) for superposing the amplified reconstructed pulse signals to form a PWM signal with a step waveform at the edge;
the digital signal processor (11), the gain amplifier (12) and the signal superposition processor (13) are sequentially connected.
3. The wide bandgap MOSFET drive circuit of claim 2, wherein said reconstructed pulse signal comprises: rising and falling reconstruction pulses;
the digital signal processor (11) is specifically configured to:
the rising edge and the falling edge of an input pulse PWM signal are tracked by adopting a hardware input synchronous locking mechanism and a micro-edge positioning technology;
the ascending reconstruction pulse and the descending reconstruction pulse are correspondingly constructed in sequence according to the time sequence.
4. The wide bandgap MOSFET tube driving circuit according to claim 2, wherein said signal generating module (1) further comprises:
a buffer unit (14) for generating a tracking signal that tracks the rising and falling edges of the input PWM signal and transmitting to the digital signal processor (11);
the buffer unit (14) is connected to the digital signal processor (11).
5. The wide bandgap MOSFET drive circuit of claim 1, wherein said high frequency signal amplifying circuit (22) comprises: a high-speed operational amplifier (U1), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a first capacitor (C1), a third capacitor (C3), and a fourth capacitor (C4);
one end of the fifth resistor (R5) is grounded, and the other end of the fifth resistor is connected with the pin 2 of the high-speed operational amplifier (U1);
one end of the seventh resistor (R7) is connected with the output end of the PWM level conversion circuit (21), and the other end of the seventh resistor is connected with the pin 3 of the high-speed operational amplifier (U1);
the pin 2 of the high-speed operational amplifier (U1) is connected with a sixth resistor (R6) and a first capacitor (C1) in sequence and then connected with the output end of the high-frequency signal amplifying circuit (22);
the pin 3 of the high-speed operational amplifier (U1) is connected with an eighth resistor (R8) and then grounded;
the pin 4 of the high-speed operational amplifier (U1) is respectively connected with a-8V power supply and grounded through a fourth capacitor (C4);
the pin 6 of the high-speed operational amplifier (U1) is connected with the output end of the high-frequency signal amplifying circuit (22);
pin 7 of the high-speed operational amplifier (U1) is respectively connected with a +23V power supply and grounded through a third capacitor (C3).
6. The wide bandgap MOSFET drive circuit of claim 1, wherein said high speed signal isolation circuit (23) comprises: a photo coupler (U2) and a ninth resistor (R9);
one end of the ninth resistor (R9) is connected with the output end of the high-frequency signal amplifying circuit (22), and the other end of the ninth resistor is connected with the pin 2 of the photoelectric coupler (U2);
pin 1 of the photoelectric coupler (U2) is connected with a +23V power supply, pin 4 is connected with a-8V power supply, and pin 6 is connected with an output push-pull circuit (24).
7. The wide bandgap MOSFET drive circuit of claim 6, wherein said output push-pull circuit (24) comprises: a first triode (Q1), a second triode (Q2), a first transient diode (D1), a second transient diode (D2), a fifth capacitance (C5), a sixth capacitance (C6), a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), and a thirteenth resistor (R13);
one end of the tenth resistor (R10) is connected with the pin 6 of the photoelectric coupler (U2), and the other end of the tenth resistor is respectively connected with the base electrode of the first triode (Q1) and the base electrode of the second triode (Q2);
the collector of the first triode (Q1) is respectively connected with a +23V power supply and grounded through a fifth capacitor (C5), and the emitter is connected with the grid of the wide band gap MOSFET through an eleventh resistor (R11);
the emitter of the second triode (Q2) is connected with the grid electrode of the wide band gap MOSFET through a twelfth resistor (R12), and the collector is respectively connected with a-8V power supply and grounded through a sixth capacitor (C6);
one end of the thirteenth resistor (R13) is connected with one end of the eleventh resistor (R11) far away from the first triode (Q1), and the other end of the thirteenth resistor is connected with a-8V power supply;
anodes of the first transient diode (D1) and the second transient diode (D2) are respectively connected;
the cathode of the first transient diode (D1) is connected with the grid electrode of the wide bandgap MOSFET;
and the cathode of the second transient diode (D2) is connected with the source electrode of the wide-bandgap MOSFET.
8. The wide bandgap MOSFET drive circuit of claim 1, wherein said linear power conversion circuit (25) comprises: a second capacitor (C2), a third triode (Q3), a fourteenth resistor (R14) and a third transient diode (D3);
the input end of the linear power supply conversion circuit (25) is respectively connected with a-8V power supply, the collector electrode of the third triode (Q3) and one end of the fourteenth resistor (R14);
the emitter of the third triode (Q3) is connected with a-5V output power supply, and the base is respectively connected with the other end of the fourteenth resistor (R14) and the anode of the third transient diode (D3);
-the third transient diode (D3) cathode is grounded;
one end of the second capacitor (C2) is connected with a-5V output power supply, and the other end of the second capacitor is grounded.
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| CN206283426U (en) * | 2016-12-22 | 2017-06-27 | 中国电子科技集团公司第二十一研究所 | Multichannel superposing type high-frequency and high-voltage power supply based on DSP2812 |
| CN110212754A (en) * | 2019-06-21 | 2019-09-06 | 南京工业大学 | Relay charging type switched capacitor high-bandwidth envelope tracking power supply circuit |
| CN110995225A (en) * | 2019-11-21 | 2020-04-10 | 全球能源互联网研究院有限公司 | Drive control circuit and method for optimizing switching characteristics of power semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN206283426U (en) * | 2016-12-22 | 2017-06-27 | 中国电子科技集团公司第二十一研究所 | Multichannel superposing type high-frequency and high-voltage power supply based on DSP2812 |
| CN110212754A (en) * | 2019-06-21 | 2019-09-06 | 南京工业大学 | Relay charging type switched capacitor high-bandwidth envelope tracking power supply circuit |
| CN110995225A (en) * | 2019-11-21 | 2020-04-10 | 全球能源互联网研究院有限公司 | Drive control circuit and method for optimizing switching characteristics of power semiconductor device |
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