CN111597076A - Method and device for operating data and method and device for managing persistent skip list - Google Patents
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Abstract
A method and apparatus for manipulating data and a method and apparatus for managing a persistent skip list are provided. The method of manipulating data includes: reading a first pointer sp having a particular format, wherein the particular format includes at least an address portion and a dirty bit; determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; and modifying the first pointer sp to point to the new address by a compare and swap CAS operation.
Description
Technical Field
The present application relates generally to the field of data manipulation of Persistent Memory devices (PMEM), and more particularly, to a method and apparatus for data manipulation of Persistent Memory devices and a method and apparatus for managing Persistent skip lists.
Background
Existing concurrent lock-free skip lists are implemented based on compare and Swap (CAS) operations, but PMEM differs from DRAM in the persistence feature, i.e., data is not lost when power is off. Under the existing computer software and hardware architecture, the program reads and writes the memory through the cache (the basic unit is called cache line) in the CPU, so for the write operation (including CAS) of the data in the PMEM, it cannot be guaranteed that the written new data will be written into the PMEM immediately. Only when the Cacheline in which the new data is located is written back to PMEM (i.e. cache line FLUSH (hereinafter referred to as FLUSH)) is the data really written into PMEM. The sequence of FLUSH is independent of the sequence in which the data is modified, as determined by the CPU, and the program can achieve its goal by executing an additional instruction (CLFLUSH/CLWB), but these instructions cannot be combined with the conventional CAS into an atomic operation. Thus, in some cases, using a conventional CAS can cause data inconsistency problems after a power outage has resumed. For example, as shown in FIG. 1, X is controlled by thread 1, the initial value is 1, and Y needs to always keep its value equal to X +1, controlled by thread 2. Since CAS + FLUSH is not an atomic operation, threads 1 and 2 may execute in the order of FIG. 1, therefore, if the system is powered off before FLUSH (X) of thread 1, the new value of X is not really written into PMEM after recovery, which results in the value of X still being 1 before modification, and the new value of Y4 has been written into PMEM, which results in Y ≠ X +1, and further causes the problem of data inconsistency. The existing CAS cannot be applied to PMEM-based persistent data structures.
Although the prior art can utilize a refresh-on-read (FLUSH-on-read) mechanism to solve the above problem in terms of correctness, i.e., FLUSH the read data once before the CAS, in the present system, there is no method for determining whether the read data needs FLUSH. In addition, there is a large use of CAS in the lock-less jump table implementation, which would generate a large number of unnecessary flashes if each CAS is preceded by a flash, which itself is a very time-consuming operation. In addition, the prior art can also utilize cachelineeffect instructions (CLFLUSH/CLWB) to solve the above problem, but the instructions are atomic operations only when the data size of flush is less than or equal to 64 bytes (64B), which means that if power is cut off during the flush operation performed on the data with the data size >64B, the data with the data size >64B may be inconsistent due to the fact that only part of the data is updated after the system is restarted and recovered.
Disclosure of Invention
Exemplary embodiments of the present application are to provide a method and apparatus for operating data and a method and apparatus for managing a persistent skip list, so as to solve at least the above-mentioned problems of the prior art.
According to an exemplary embodiment of the present application, there is provided a method of operating data, which may include: reading a first pointer sp having a particular format, wherein the particular format includes at least an address portion and a dirty bit; determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; the first pointer sp is modified to point to the new address by a compare and swap CAS operation.
Optionally, the step of determining whether to perform a flush operation on the first pointer sp according to the dirty bit of the first pointer sp may include: determining whether a dirty bit of a first pointer sp is a first value; and if the dirty bit of the first pointer sp is a first value, setting the dirty bit of the first pointer sp to be a second value and executing a flush operation on the first pointer sp, and if the dirty bit of the first pointer sp is the second value, not executing the flush operation on the first pointer sp.
Optionally, the dirty bit in the particular format may be at least one of the lowest 3 bits of the pointer.
Optionally, the step of modifying the first pointer sp to point to the new address by a compare-and-swap CAS operation may comprise: creating a second pointer sp _ old and a third pointer sp _ new having the specific format; pointing a second pointer sp _ old to an address part of a first pointer sp, and setting a dirty bit of the second pointer sp _ old to a second value; pointing a third pointer sp _ new to the new address, and setting a dirty bit of the third pointer sp _ new to a first value; the CAS operation is performed on the first pointer sp, the second pointer sp _ old, and the third pointer sp _ new.
According to an exemplary embodiment of the present application, there is provided an apparatus to manipulate data, the apparatus may include: a reading module configured to read a first pointer sp having a specific format, wherein the specific format comprises at least an address portion and a dirty bit; and a processing module configured to: determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; and modifies the first pointer sp to point to the new address by a compare and swap CAS operation.
Optionally, the processor may be configured to determine whether to perform a flush operation on the first pointer sp by: determining whether a dirty bit of a first pointer sp is a first value; and if the dirty bit of the first pointer sp is a first value, setting the dirty bit of the first pointer sp to be a second value and executing a flush operation on the first pointer sp, and if the dirty bit of the first pointer sp is the second value, not executing the flush operation on the first pointer sp.
Optionally, the dirty bit in the particular format may be at least one of the lowest 3 bits of the pointer.
Optionally, the processing module may be configured to modify the first pointer sp to point to the new address by: creating a second pointer sp _ old and a third pointer sp _ new having the specific format; pointing a second pointer sp _ old to an address part of a first pointer sp, and setting a dirty bit of the second pointer sp _ old to a second value; pointing a third pointer sp _ new to the new address, and setting a dirty bit of the third pointer sp _ new to a first value; the CAS operation is performed on the first pointer sp, the second pointer sp _ old, and the third pointer sp _ new.
According to an exemplary embodiment of the present application, there is provided a method of managing a persistent skip list, which may include: generating a persistent skip list based on the pointers having the first format and the pointers having the second format; and storing all pointers in the persistent skip list having a first format and key-value pairs and heights of all nodes in a persistent storage, wherein the first format includes at least an address portion and a dirty bit, the second format includes only the address portion, the dirty bit is used to determine whether to perform a flush operation on the pointers having the first format, wherein a next pointer of each node in a bottom linked list in the persistent skip list has the first format, and a next pointer of each node in a top linked list other than the bottom linked list in the persistent skip list has the second format.
Alternatively, the dirty bit in the first format may be at least one of the lowest 3 bits of the pointer.
Optionally, when any one node in the bottom linked list is modified, the following operations may be performed: reading a next pointer sp of the any one node; determining whether a dirty bit of a next pointer sp of any one of the nodes is a first value; if the dirty bit of the next pointer sp of any one node is a first value, setting the dirty bit of the next pointer sp of any one node as a second value and executing flush operation on the next pointer sp of any one node, and if the dirty bit of the next pointer sp of any one node is the second value, not executing flush operation on the next pointer sp of any one node; the next pointer sp of any one of the nodes is modified to point to the new address by the compare and swap CAS operation.
Optionally, the step of modifying the first pointer sp to point to the new address by a compare-and-swap CAS operation may comprise: creating a pointer sp _ old and a pointer sp _ new having a first format; pointing the pointer sp _ old to the address part of a next pointer sp of any one node, and setting a dirty bit of the pointer sp _ old to be a second value; pointing a pointer sp _ new to the new address, and setting a dirty bit of the pointer sp _ new to a first value; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node.
Optionally, when any node in the upper linked list except the bottom linked list in the persistent skip list is modified, the following operations may be performed: reading a next pointer sp of the any one node; creating a pointer sp _ old and a pointer sp _ new having a second format; pointing a pointer sp _ old to a next pointer sp of the arbitrary node; pointing the pointer sp _ new to the new address; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node.
Optionally, when a device using the method powers up, the persistent skip list may be restored by rebuilding a next pointer in the persistent skip list having a second format based on the underlying linked list stored in the persistent storage.
Optionally, the step of restoring the persistent skip list may include: obtaining a head node of the bottom linked list, and assigning the head node to a current node; starting from the head node: and if the next pointer of the current node in the bottom linked list does not point to the tail node, modifying the next pointer of the corresponding layer linked list of the previous node of each upper linked list to point to the current node according to the height of the current node in the bottom linked list, and if the next pointer of the current node in the bottom linked list points to the tail node, modifying the next pointer of the last node of each upper linked list to point to the tail node.
Optionally, according to an exemplary embodiment of the present application, there is provided an apparatus for managing a persistent skip list, which may include: a processing unit configured to generate a persistent skip list based on the pointers having the first format and the pointers having the second format; and a storage unit configured to store all pointers having a first format in the persistent skip list and key-value pairs and heights of all nodes in a persistent storage, wherein the first format includes at least an address portion and a dirty bit, the second format includes only the address portion, and the dirty bit is used to determine whether to perform a flush operation on the pointers having the first format, wherein a next pointer of each node in an underlying linked list in the persistent skip list has the first format, and a next pointer of each node in an upper linked list other than the underlying linked list in the persistent skip list has the second format.
Alternatively, the dirty bit in the first format may be at least one of the lowest 3 bits of the pointer.
Optionally, when modifying any one node in the underlying linked list, the processing unit may be configured to: reading a next pointer sp of the any one node; determining whether a dirty bit of a next pointer sp of any one of the nodes is a first value; if the dirty bit of the next pointer sp of any one node is a first value, setting the dirty bit of the next pointer sp of any one node as a second value and executing flush operation on the next pointer sp of any one node, and if the dirty bit of the next pointer sp of any one node is the second value, not executing flush operation on the next pointer sp of any one node; the next pointer sp of any one of the nodes is modified to point to the new address by the compare and swap CAS operation.
Optionally, the processing unit may be configured to modify the first pointer sp to point to the new address by: creating a pointer sp _ old and a pointer sp _ new having a first format; pointing the pointer sp _ old to the address part of a next pointer sp of any one node, and setting a dirty bit of the pointer sp _ old to be a second value; pointing a pointer sp _ new to the new address, and setting a dirty bit of the pointer sp _ new to a first value; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node.
Optionally, when modifying any node in the upper linked list except the bottom linked list in the persistent skip list, the processing unit may be configured to: reading a next pointer sp of the any one node; creating a pointer sp _ old and a pointer sp _ new having a second format; pointing a pointer sp _ old to a next pointer sp of the arbitrary node; pointing the pointer sp _ new to the new address; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node.
Optionally, when the apparatus is powered on, the processor may be configured to restore the persistent skip list by reconstructing, by the storage unit, a next pointer in the persistent skip list having a second format on the basis of the underlying linked list stored in the persistent storage.
Optionally, the step of the processing unit being configurable to restore the persistent skip list by: obtaining a head node of the bottom linked list, and assigning the head node to a current node; starting from the head node: and if the next pointer of the current node in the bottom linked list does not point to the tail node, modifying the next pointer of the corresponding layer linked list of the previous node of each upper linked list to point to the current node according to the height of the current node in the bottom linked list, and if the next pointer of the current node in the bottom linked list points to the tail node, modifying the next pointer of the last node of each upper linked list to point to the tail node.
According to another exemplary embodiment of the present application, a computer-readable storage medium storing instructions is provided, wherein the instructions, when executed by at least one computing device, cause the at least one computing device to perform a method of operating data as described above or a method of managing a persistent skip list as described above.
According to another exemplary embodiment of the present application, a system is provided comprising at least one computing device and at least one storage device storing instructions, wherein the instructions, when executed by the at least one computing device, cause the at least one computing device to perform a method of operating data as described above or a method of managing a persistent skip list as described above.
The method and apparatus for manipulating data according to the exemplary embodiments of the present application avoid unnecessary flush using a new intelligent pointer, implement an efficient PMEM-based CAS, and simultaneously can solve the problem of data inconsistency caused by the CAS in PMEM. In addition, the method and the device for managing the persistent skip list replace the traditional memory address pointer by the intelligent pointer, so that the persistent concurrent lock-free skip list is realized.
Additional aspects and/or advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
Drawings
These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram illustrating an example of a DRAM-based CAS operation in the prior art;
FIG. 2 is a diagram illustrating a general pointer in the prior art and a smart pointer according to an exemplary embodiment of the present application;
FIG. 3 is a general flowchart illustrating a method of operating data according to an exemplary embodiment of the present application;
FIG. 4 is a detailed flowchart illustrating a method of operating data according to an exemplary embodiment of the present application;
FIG. 5 is a block diagram illustrating an apparatus to manipulate data according to an exemplary embodiment of the present application;
FIG. 6 is a flowchart illustrating a method of managing a persistent skip list according to an exemplary embodiment of the present application;
FIG. 7 is a diagram illustrating an example of a conventional DRAM-based skip list and a PEME-based persistent skip list according to an exemplary embodiment of the present application;
FIG. 8 is a flowchart illustrating a process of modifying an underlying linked list of PMEM-based persistent skip lists according to an exemplary embodiment of the present application;
FIG. 9 is a flowchart illustrating a process of restoring a PMEM-based persistent hop-table according to an exemplary embodiment of the present application;
FIG. 10 is a diagram of pseudo code illustrating a process of restoring a PMEM-based persistent skip list according to an exemplary embodiment of the present application;
fig. 11 is a block diagram illustrating an apparatus for managing a persistent skip list according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments are described below in order to explain the present invention by referring to the figures.
Fig. 2 is a diagram illustrating a general pointer in the related art and an intelligent pointer according to an exemplary embodiment of the present application.
As shown in fig. 2, the memory address used in computer programming based on X8664-bit CUP is 64 bits, the normal pointer 101 in the prior art uses a 64-bit unsigned integer variable to store the pointed memory address, and the 8-byte CAS atomic operation supported in the X8664-bit CPU must guarantee 8-byte alignment, which means that the lowest 3 bits of the address supporting the 8-byte CAS atomic operation are always 0 since the basic unit of the memory access is 1 byte.
The smart pointer 102 according to an exemplary embodiment of the present application has a specific format including at least an address part addr and a dirty bit dirty _ flag. As shown in fig. 2, the dirty bit dirty _ flag according to the exemplary embodiment of the present application is at least one bit of the lowest 3 bits of the intelligent pointer 102 (i.e., at least one bit of the last reserved portion of the intelligent pointer 102 in fig. 2), and the address portion addr is a portion of the intelligent pointer 102 other than the lowest 3 bits, and the address portion addr is used for storing a memory address. The dirty bit dirty _ flag may be used to indicate whether a flush operation is required when the smart pointer 102 is accessed next time. If the dirty bit dirty _ flag is a first value (e.g., 1), it indicates that a flush operation needs to be performed on the smart pointer 102 when the smart pointer 102 is accessed next time, and if the dirty bit dirty _ flag is a second value (e.g., 0), it indicates that a flush operation does not need to be performed on the smart pointer 102 when the smart pointer 102 is accessed next time.
A method of operating data based on the intelligent pointer of fig. 2 according to an exemplary embodiment of the present application will be described in detail below.
Fig. 3 is a general flowchart illustrating a method of operating data according to an exemplary embodiment of the present application.
As shown in fig. 3, in step S301, a first pointer sp having the specific format including at least the address portion addr and the dirty bit dirtyflag is read, in other words, the first pointer sp is an intelligent pointer having the structure of the intelligent pointer 102 shown in fig. 2.
In step S302, it is determined whether to perform a flush operation on the first pointer sp according to the dirty bit dirtyflag of the first pointer sp.
At step S303, the first pointer sp is modified to point to the new address by the Compare-and-Swap CAS operation. This is described in detail below with reference to fig. 4.
Fig. 4 is a detailed flowchart illustrating a method of operating data according to an exemplary embodiment of the present application.
As shown in fig. 4, in step S401 (i.e., S301), the first pointer sp having the specific format is read to obtain the address part addr and the dirty bit dirtyflag of the first pointer sp.
In step S402, it is determined whether the dirty bit dirtyflag of the first pointer sp is a first value (e.g., 1);
if the dirty bit dirtyflag of the first pointer sp is a first value (e.g., 1), the dirty bit dirtyflag of the first pointer sp is set to a second value (e.g., 0) in step S403, a flush operation is performed on the first pointer sp, and it proceeds to step S404. Herein, the first value and the second value are different and may be any two values different from each other. If the dirty bit dirtyflag of the first pointer sp is a second value (e.g., 0), the flush operation is not performed on the first pointer sp, but directly proceeds to step S404. That is, step S302 includes step S402 and step S403.
In step S404, a second pointer sp _ old and a third pointer sp _ new having the specific format are created.
In step S405, the second pointer sp _ old is pointed to the address portion addr of the first pointer sp, and the dirty bit dirtyflag of the second pointer sp _ old is set to a second value (e.g., 0).
In step S406, the third pointer sp _ new is pointed to the new address, and the dirty bit dirty _ flag of the third pointer sp _ new is set to a first value (e.g., 1). The order between step S405 and step S406 may be interchanged.
In step S407, a CAS operation, i.e., CAS (sp, sp _ old, sp _ new) is performed on the first pointer sp, the second pointer sp _ old, and the third pointer sp _ new. Specifically, it is first determined whether sp and sp _ old are equal, and if sp and sp _ old are equal, sp is modified to sp _ new and ended. If sp and sp _ old are not equal, return to step S401. That is, step S303 includes steps S404 to S407. As can be seen from the above description, after the CAS operation based on the smart pointer is successful, the dirty bit dirtyflag of the smart pointer is set to 1.
Fig. 5 shows a block diagram of an apparatus 100 for manipulating data according to an exemplary embodiment of the present application.
As shown in fig. 5, the apparatus 100 may include a reading module 110 and a processing module 120.
The reading module 110 may be configured to read a first pointer sp having a specific format, wherein the specific format includes at least an address portion addr and a dirty bit dirtyflag, wherein the dirty bit dirtyflag may be at least one bit of the lowest 3 bits of the smart pointer 102 as shown in fig. 2. The processing module 120 may be configured to determine whether to perform a flush operation on the first pointer sp based on a dirty bit dirtyflag of the first pointer sp, and modify the first pointer sp to point to a new address by comparing and swapping CAS operations.
Specifically, the processing module 120 may determine whether to perform a flush operation on the first pointer sp by: first, it is determined whether a dirty bit dirtyflag of a first pointer sp is a first value (e.g., 1); if the dirty bit dirtyflag of the first pointer sp is a first value (e.g., 1), the dirty bit dirtyflag of the first pointer sp is set to a second value (e.g., 0) and a flush operation is performed on the first pointer sp, and if the dirty bit dirtyflag of the first pointer sp is the second value (e.g., 0), the flush operation is not performed on the first pointer sp.
After the processing module 120 determines whether to perform a flush operation on the first pointer sp by the above operations, the processing module 120 may modify the first pointer sp to point to the new address by: firstly, creating a second pointer sp _ old and a third pointer sp _ new with the specific format; then, pointing the second pointer sp _ old to the address portion addr of the first pointer sp, and setting the dirty bit dirtyflag of the second pointer sp _ old to a second value (e.g., 0); thereafter, pointing the third pointer sp _ new to the new address, and setting a dirty bit dirtyflag of the third pointer sp _ new to a first value (e.g., 1); finally, a CAS operation, i.e., CAS (sp, sp _ old, sp _ new), is performed on the first pointer sp, the second pointer sp _ old, and the third pointer sp _ new.
According to the method and the device for operating data based on the intelligent pointer, unnecessary flush operation can be avoided, the high-efficiency CAS based on PMEM is realized, and meanwhile the problem of data inconsistency caused by the CAS in PMEM can be solved.
A method and apparatus for managing a persistent skip list implemented using the intelligent pointers described with reference to fig. 2 through 5 will now be described.
Fig. 6 is a flowchart illustrating a method of managing a persistent skip list according to an exemplary embodiment of the present application.
As shown in fig. 6, in step S601, a persistent skip list is generated according to a pointer having a first format and a pointer having a second format, wherein the persistent skip list is a persistent lock-free skip list. The first format includes at least an address portion addr and a dirty bit dirtyflag, the dirty bit dirtyflag is used to determine whether to perform a flush operation on the pointer having the first format, and the dirty bit dirtyflag in the first format is at least one of the lowest 3 bits of the pointer, in other words, the first format is the format of the smart pointer 102 shown in fig. 2. The second format comprises only the address part, in other words the second format is the format of the ordinary pointer 101 shown in fig. 2.
In particular, a persistent skip list may be generated according to an existing method of generating a normal skip list, wherein a next pointer of each node in an underlying linked list in the persistent skip list has a first format, and a next pointer of each node in an upper linked list other than the underlying linked list in the persistent skip list has a second format. In addition, a dirty bit dirtyflag in the next pointer of each node in the underlying linked list in the persistent skip list is initialized to 1. Since a process of generating a skip list according to an existing method of generating a general skip list is well known to those skilled in the art, it is not described in detail herein.
In step S602, all pointers in the persistent skip list having the first format and key-value pairs and heights of all nodes are stored in a persistent storage. This will be described in detail with reference to fig. 7. Fig. 7 is a diagram illustrating an example of a conventional DRAM-based skip list and a PMEM-based persistent skip list according to an exemplary embodiment of the present application.
As shown in fig. 7, the next pointers of the nodes in each layer of linked list of the conventional DRAM-based skip list are pointers in the second format (i.e., the normal pointers 101 in fig. 2), however, the next pointers of the nodes in the bottom linked list of the PMEM-based persistent skip list according to the exemplary embodiment of the present application are pointers in the first format (i.e., the intelligent pointers 102 in fig. 2), and the next pointers of the nodes in the other layer of linked lists except for the bottom linked list of the PMEM-based persistent skip list are pointers in the second format, that is, the nodes in the bottom linked list of the PMEM-based persistent skip list include key value pairs (i.e., the key value k and the value v), the next pointers in the first format (i.e., the intelligent pointers 102 in fig. 2), and a height (height), and the nodes in the other layer of the persistent skip list except for the bottom linked list include key value pairs (i.e., the key value k and the value v) and the next pointers in the second format (i.e., the normal pointers 101 in fig. 2) ). In the present application, in order to make the whole skip list persistent, only the persistence of the bottom linked list needs to be ensured, so the next pointer of the node in the bottom linked list needs to be set as the intelligent pointer 102 in fig. 2, and the next pointers of the nodes in the other layer linked lists except the bottom linked list can be reconstructed on the basis of the bottom linked list in the recovery process of the persistent skip list, so the next pointers of the nodes in the other layer linked lists except the bottom linked list are set as the common pointers 101 in fig. 2.
An operation procedure when a PMEM-based persistent skip list according to an exemplary embodiment of the present application is modified will be described with reference to fig. 8.
FIG. 8 is a flowchart illustrating a process of modifying an underlying linked list of PMEM-based persistent hop-tables according to an exemplary embodiment of the present application.
As shown in fig. 8, when any one node in the bottom linked list is modified, step S801 is performed to read a next pointer sp of the any one node, where the next pointer sp of the any one node in the bottom linked list is a pointer having the structure of the intelligent pointer 102 in fig. 2, and therefore, the address portion addr and the dirty bit dirtyflag of the next pointer sp can be obtained in the reading process.
Thereafter, in step S802, it is determined whether the dirty bit dirtyflag of the next pointer sp of the arbitrary one node is a first value.
If the dirty bit dirtyflag of the next pointer sp of any one of the nodes is a first value (e.g., 1), the process proceeds to step S803, the dirty bit dirtyflag of the next pointer sp of any one of the nodes is set to a second value (e.g., 0), a flush operation is performed on the next pointer sp of any one of the nodes, and the process proceeds to step S804. If the dirty bit dirtyflag of the next pointer sp of the arbitrary one node is a second value (for example, 0), the flush operation is not performed on the next pointer sp of the arbitrary one node, but the process directly proceeds to step S804.
In step S804, the next pointer sp of the arbitrary one node is modified to point to the new address by the compare-and-swap CAS operation.
Specifically, the step of modifying the next pointer sp of the arbitrary one node to point to the new address by comparing and swapping CAS operations may include: creating a pointer sp _ old and a pointer sp _ new having a first format; pointing the pointer sp _ old to the address part of a next pointer sp of any one node, and setting a dirty bit of the pointer sp _ old to be a second value; pointing a pointer sp _ new to the new address, and setting a dirty bit of the pointer sp _ new to a first value; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node. After the above process, the dirty bit dirtyflag of the next pointer sp of any one of the nodes is set to 1. Since the process is similar to steps S404 to S407 of fig. 4, a description thereof will not be repeated.
When any one node in the upper linked list except the bottom linked list in the persistent skip list is modified, the process can be realized by using a CAS operation based on a common pointer 101, namely, reading a next pointer sp of the any one node in the upper linked list except the bottom linked list, creating a pointer sp _ old and a pointer sp _ new with a second format, pointing the pointer sp _ old to a next pointer sp of the any one node in the upper linked list except the bottom linked list, pointing the pointer sp _ new to a new address, and performing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of the any one node in the upper linked list except the bottom linked list.
Further, when a device using the method of managing a persistent skip list is powered on, the persistent skip list is restored by rebuilding a next pointer in the persistent skip list having a second format on the basis of an underlying linked list stored in a persistent storage device. This will be described in detail below with reference to fig. 9 and 10.
Fig. 9 is a flowchart illustrating a process of restoring a PMEM-based persistent hop-table according to an exemplary embodiment of the present application. Fig. 10 is a diagram of pseudo code illustrating a process of restoring a PMEM-based persistent skip list according to an exemplary embodiment of the present application.
As shown in fig. 9, in step S901, a head node head of the underlying linked list in the persistent skip list is obtained, and is assigned to the current node, where a key-value pair (i.e., a key value k and a data v) of the head node, a next pointer with a first format, and a height are obtained in the process of obtaining the head node head.
In this step, a temporary pointer array cur [1.. max _ height-1] needs to be set and initialized, as shown in fig. 10, in the pseudo code portion 1010, max _ height-1 represents the maximum value among the heights of all nodes of the PMEM-based persistent skip list stored in the PMEM. Pseudo code portion 1010 represents the initialization of the cur [1.. max _ height-1] pointer array as the head node head of the PMEM-based persisted list stored in PMEM, which is assigned as head. Further, in the pseudo code section 1020, a node represents a current node (in other words, a variable for representing the current node) and a head represents a head node, that is, the pseudo code section 1020 represents that the head node head is assigned to the current node, in other words, the current node is determined as the head node.
After step S901, from the head node head, the subsequent steps S902 to S904 are performed.
Specifically, first, in step S902, it is determined whether the next pointer of the current node in the underlying linked list points to the tail node tail. Referring to fig. 10, in the pseudo code portion 1030, tail denotes a tail node, and node _ addr is used to temporarily store an address portion addr of a next pointer of a current node, which belongs to the smart pointer 102 shown in fig. 2. The judge statement in the while statement in the pseudo-code portion 1030 indicates a judgment as to whether the next pointer of the current node points to the tail node tail.
If the next pointer of the current node in the bottom linked list does not point to the tail node tail, in step S903, the next pointer of the corresponding layer linked list of the previous node of each upper linked list is modified to point to the current node according to the height of the current node in the bottom linked list, as shown by pseudo code 1031 in fig. 10. Thereafter, in step S904, the next node in the bottom linked list is assigned to the current node, and as shown in fig. 10, the node ═ node- > next [0] statement in the pseudo code 1030 indicates that the next node- > next [0] is assigned to the current node.
If the next pointer of the current node in the bottom linked list points to the tail node tail, in step S905, the next pointer of the last node of each top linked list is modified to point to the tail node tail, as shown by the pseudo code 1040 in fig. 10.
The persistent concurrency no-hop table is implemented by fig. 6 to 10 described above.
Fig. 11 is a block diagram illustrating an apparatus for managing a persistent skip list according to an exemplary embodiment of the present application.
As shown in fig. 11, the apparatus 20 includes a processing unit 210 and a storage unit 220.
The processing unit 210 may be configured to generate a persistent skip list based on the pointer having the first format and the pointer having the second format, wherein the persistent skip list is a persistent lock-free skip list. The first format includes at least an address portion addr and a dirty bit dirtyflag, the dirty bit dirtyflag is used to determine whether to perform a flush operation on the pointer having the first format, and the dirty bit dirtyflag in the first format is at least one of the lowest 3 bits of the pointer, in other words, the first format is the format of the smart pointer 102 shown in fig. 2. The second format comprises only the address part, in other words the second format is the format of the ordinary pointer 101 shown in fig. 2.
In particular, processing unit 210 may generate a persistent skip list according to existing methods of generating a normal skip list, where a next pointer of each node in a bottom linked list in the persistent skip list has a first format, and a next pointer of each node in an upper linked list other than the bottom linked list in the persistent skip list has a second format. In addition, a dirty bit dirtyflag in the next pointer of each node in the underlying linked list in the persistent skip list is initialized to 1. Since a process of generating a skip list according to an existing method of generating a general skip list is well known to those skilled in the art, it is not described in detail herein.
The storage unit 220 may be configured to store all pointers in the persistent skip list having the first format and key-value pairs and heights of all nodes in a persistent storage. Since the case of the conventional DRAM-based skip list and the PMEM-based persistent skip list according to the exemplary embodiment of the present application has been described in detail above with reference to fig. 7, a repeated description will not be made herein.
How processing unit 210 operates when modifying any one of the nodes in the underlying linked list will be described below.
When any one node in the bottom linked list is modified, the processing unit 210 may be configured to read a next pointer sp of the any one node, where the next pointer sp of the any one node in the bottom linked list is a pointer having the structure of the intelligent pointer 102 in fig. 2, and therefore, during the reading process, the processing unit 210 may obtain an address part addr and a dirty bit dirtyflag of the next pointer sp.
Thereafter, the processing unit 210 may determine whether a dirty bit of the next pointer sp of the arbitrary one node is a first value. If the dirty bit dirtyflag of the next pointer sp of any one of the nodes is a first value (e.g., 1), the processing unit 210 may set the dirty bit dirtyflag of the next pointer sp of any one of the nodes to a second value (e.g., 0), perform a flush operation on the next pointer sp of any one of the nodes, and modify the next pointer sp of any one of the nodes to point to a new address by a compare-and-swap CAS operation. If the dirty bit dirtyflag of the next pointer sp of the arbitrary node is a second value (e.g., 0), the processing unit 210 may not perform flush operation on the next pointer sp of the arbitrary node, and modify the next pointer sp of the arbitrary node to point to a new address by comparing and swapping the CAS operation.
In particular, the processing unit 210 may be configured to modify the first pointer sp to point to the new address by: creating a pointer sp _ old and a pointer sp _ new having a first format; pointing the pointer sp _ old to the address part of a next pointer sp of any one node, and setting a dirty bit of the pointer sp _ old to be a second value; pointing a pointer sp _ new to the new address, and setting a dirty bit of the pointer sp _ new to a first value; and executing the CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of any one node. After the above process, the dirty bit dirtyflag of the next pointer sp of any one of the nodes is set to 1. Since the process is similar to steps S404 to S407 of fig. 4, a description thereof will not be repeated.
Further, when modifying any one node in the upper linked list other than the lower linked list in the persistent skip list, processing unit 210 may implement this process using a CAS operation based on normal pointer 101, that is, processor 210 may read a next pointer sp of the any one node in the upper linked list other than the lower linked list, create a pointer sp _ old and a pointer sp _ new having a second format, point the pointer sp _ old to a next pointer sp of the any one node in the upper linked list other than the lower linked list, point the pointer sp _ new to a new address, and perform a CAS operation on the next pointer sp, the pointer sp _ old and the pointer sp _ new of the any one node in the upper linked list other than the lower linked list.
Further, when the apparatus managing the persistent skip list is powered on, the processing unit may be configured to restore the persistent skip list by reconstructing, by the storage unit 220, a next pointer in the persistent skip list having the second format on the basis of an underlying linked list stored in the persistent storage.
In particular, the step of processing unit 210 being configurable to restore the persistent skip list by: obtaining a head node of the bottom linked list, and assigning the head node to a current node; and from the head node, if the next pointer of the current node in the bottom linked list does not point to the tail node, modifying the next pointer of the corresponding layer linked list of the previous node of each upper linked list to point to the current node according to the height of the current node in the bottom linked list, and if the next pointer of the current node in the bottom linked list points to the tail node, modifying the next pointer of the last node of each upper linked list to point to the tail node. Since this has been described in detail above with reference to fig. 9 and 10, a repeated description thereof will not be made.
A method and apparatus for operating data and a method and apparatus for managing a persistent skip list according to exemplary embodiments of the present application have been described above with reference to fig. 2 to 11. However, it should be understood that: the means shown in the figures may each be configured as software, hardware, firmware, or any combination of the preceding to perform a particular function. For example, the apparatus may correspond to an application specific integrated circuit, to pure software code, or to a module combining software and hardware. Further, one or more functions implemented by the apparatus may also be performed collectively by components in a physical entity device (e.g., a processor, a client, or a server, etc.).
It should be appreciated that the method of manipulating data according to exemplary embodiments of the present application may be implemented by instructions recorded on a computer-readable storage medium, for example, according to exemplary embodiments of the present application, there may be provided a computer-readable storage medium storing instructions that, when executed by at least one computing device, cause the at least one computing device to perform the steps of: reading a first pointer sp having a particular format, wherein the particular format includes at least an address portion and a dirty bit; determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; the first pointer sp is modified to point to the new address by a compare and swap CAS operation.
For another example, according to another exemplary embodiment of the present application, a computer-readable storage medium storing instructions that, when executed by at least one computing device, cause the at least one computing device to perform the steps of: generating a persistent skip list based on the pointers having the first format and the pointers having the second format; and storing all pointers in the persistent skip list having a first format and key-value pairs and heights of all nodes in a persistent storage, wherein the first format includes at least an address portion and a dirty bit, the second format includes only the address portion, the dirty bit is used to determine whether to perform a flush operation on the pointers having the first format, wherein a next pointer of each node in a bottom linked list in the persistent skip list has the first format, and a next pointer of each node in a top linked list other than the bottom linked list in the persistent skip list has the second format.
The instructions stored in the computer-readable storage medium can be executed in an environment deployed in a computer device such as a client, a host, a proxy device, a server, etc., and it should be noted that the instructions can also perform more specific processing when the above steps are performed, and the content of the further processing is mentioned in the description referring to fig. 2 to 4 and fig. 6 to 10, so that the further processing will not be repeated here to avoid repetition.
It should be noted that the devices on-line in the model according to the exemplary embodiment of the present invention may completely depend on the execution of the computer program to realize the corresponding functions, that is, each device corresponds to each step in the functional architecture of the computer program, so that the whole system is called by a special software package (e.g., lib library) to realize the corresponding functions.
On the other hand, the apparatus for manipulating data according to an exemplary embodiment of the present invention may also be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the corresponding operations may be stored in a computer-readable medium such as a storage medium, so that a processor may perform the corresponding operations by reading and executing the corresponding program code or code segments.
For example, according to an exemplary embodiment of the present application, a system may be provided comprising at least one computing device and at least one storage device storing instructions, wherein the instructions, when executed by the at least one computing device, cause the at least one computing device to perform the steps of: reading a first pointer sp having a particular format, wherein the particular format includes at least an address portion and a dirty bit; determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; the first pointer sp is modified to point to the new address by a compare and swap CAS operation.
For another example, according to another exemplary embodiment of the present application, there may be provided a system comprising at least one computing device and at least one storage device storing instructions, wherein the instructions, when executed by the at least one computing device, cause the at least one computing device to perform the steps of: generating a persistent skip list based on the pointers having the first format and the pointers having the second format; and storing all pointers in the persistent skip list having a first format and key-value pairs and heights of all nodes in a persistent storage, wherein the first format includes at least an address portion and a dirty bit, the second format includes only the address portion, the dirty bit is used to determine whether to perform a flush operation on the pointers having the first format, wherein a next pointer of each node in a bottom linked list in the persistent skip list has the first format, and a next pointer of each node in a top linked list other than the bottom linked list in the persistent skip list has the second format.
It should be noted that the instructions stored in the at least one storage device may also perform more specific processing when the above steps are performed, and the content of these further processing is already mentioned in the description with reference to fig. 2 to 4 and 6 to 10, so that the description will not be repeated here to avoid repetition.
In particular, the above-described system may be deployed in a server or client or on a node in a distributed network environment. Further, the system may be a PC computer, tablet device, personal digital assistant, smart phone, web application, or other device capable of executing the set of instructions. In addition, the system may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). In addition, all components of the system may be connected to each other via a bus and/or a network.
The system here need not be a single system, but can be any collection of devices or circuits capable of executing the above instructions (or sets of instructions) either individually or in combination. The system may also be part of an integrated control system or system manager, or may be configured as a portable electronic device that interfaces with local or remote (e.g., via wireless transmission).
In the system, the at least one computing device may comprise a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example, and not limitation, the at least one computing device may also include analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, and the like. The computing device may execute instructions or code stored in one of the storage devices, which may also store data. Instructions and data may also be transmitted and received over a network via a network interface device, which may employ any known transmission protocol.
The memory device may be integrated with the computing device, for example, by having RAM or flash memory disposed within an integrated circuit microprocessor or the like. Further, the storage device may comprise a stand-alone device, such as an external disk drive, storage array, or any other storage device usable by a database system. The storage device and the computing device may be operatively coupled or may communicate with each other, such as through I/O ports, network connections, etc., so that the computing device can read instructions stored in the storage device.
While exemplary embodiments of the invention have been described above, it should be understood that the above description is illustrative only and not exhaustive, and that the invention is not limited to the exemplary embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Therefore, the protection scope of the present invention should be subject to the scope of the claims.
Claims (10)
1. A method of manipulating data, the method comprising:
reading a first pointer sp having a particular format, wherein the particular format includes at least an address portion and a dirty bit;
determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp;
the first pointer sp is modified to point to the new address by a compare and swap CAS operation.
2. The method of claim 1, wherein determining whether to perform a flush operation on the first pointer sp according to the dirty bit of the first pointer sp comprises:
determining whether a dirty bit of a first pointer sp is a first value;
and if the dirty bit of the first pointer sp is a first value, setting the dirty bit of the first pointer sp to be a second value and executing a flush operation on the first pointer sp, and if the dirty bit of the first pointer sp is the second value, not executing the flush operation on the first pointer sp.
3. The method of claim 1, wherein the dirty bit in the particular format is at least one of the lowest 3 bits of a pointer.
4. The method of claim 2, wherein the step of modifying the first pointer sp to point to the new address by a compare-and-swap CAS operation comprises:
creating a second pointer sp _ old and a third pointer sp _ new having the specific format;
pointing a second pointer sp _ old to an address part of a first pointer sp, and setting a dirty bit of the second pointer sp _ old to a second value;
pointing a third pointer sp _ new to the new address, and setting a dirty bit of the third pointer sp _ new to a first value;
the CAS operation is performed on the first pointer sp, the second pointer sp _ old, and the third pointer sp _ new.
5. An apparatus to manipulate data, the apparatus comprising:
a reading module configured to read a first pointer sp having a specific format, wherein the specific format comprises at least an address portion and a dirty bit; and
a processing module configured to:
determining whether to execute a flush operation on a first pointer sp according to a dirty bit of the first pointer sp; and is
The first pointer sp is modified to point to the new address by a compare and swap CAS operation.
6. A method of managing a persistent skip list, the method comprising:
generating a persistent skip list based on the pointers having the first format and the pointers having the second format; and is
Storing all pointers in the persistent skip list having the first format and key-value pairs and heights of all nodes in a persistent storage,
wherein the first format comprises at least an address portion and a dirty bit, the second format comprises only the address portion, the dirty bit is used to determine whether to perform a flush operation on a pointer having the first format,
wherein a next pointer of each node in a bottom linked list in the persistent skip list has a first format, and a next pointer of each node in an upper linked list in the persistent skip list other than the bottom linked list has a second format.
7. The method of claim 6, wherein the dirty bit in the first format is at least one of the lowest 3 bits of the pointer.
8. An apparatus to manage persistent skip lists, the apparatus comprising:
a processing unit configured to generate a persistent skip list based on the pointers having the first format and the pointers having the second format; and is
A storage unit configured to store all pointers having a first format and key-value pairs and heights of all nodes in the persistent skip list in a persistent storage,
wherein the first format comprises at least an address portion and a dirty bit, the second format comprises only the address portion, the dirty bit is used to determine whether to perform a flush operation on a pointer having the first format,
wherein a next pointer of each node in a bottom linked list in the persistent skip list has a first format, and a next pointer of each node in an upper linked list in the persistent skip list other than the bottom linked list has a second format.
9. A computer-readable storage medium storing instructions that, when executed by at least one computing device, cause the at least one computing device to perform the method of any of claims 1-4 and 6-7.
10. A system comprising at least one computing device and at least one storage device storing instructions that, when executed by the at least one computing device, cause the at least one computing device to perform the method of any of claims 1-4 and 6-7.
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