CN111584593B - Display panel, display device and manufacturing method of display panel - Google Patents
Display panel, display device and manufacturing method of display panel Download PDFInfo
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- CN111584593B CN111584593B CN202010448063.9A CN202010448063A CN111584593B CN 111584593 B CN111584593 B CN 111584593B CN 202010448063 A CN202010448063 A CN 202010448063A CN 111584593 B CN111584593 B CN 111584593B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 127
- 239000002184 metal Substances 0.000 claims abstract description 127
- 239000003990 capacitor Substances 0.000 claims abstract description 105
- 238000004146 energy storage Methods 0.000 claims abstract description 16
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010409 thin film Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 12
- 239000004020 conductor Substances 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical class [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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Abstract
The application discloses a display panel, a display device and a manufacturing method of the display panel. The sub-pixel region of the display panel comprises a driving region and a display region, wherein the driving region comprises a transistor region and a functional region, the functional region comprises a shading layer, a buffer layer, a living jump layer, a gate insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and a first electrode layer which are sequentially laminated, and orthographic projections of the shading layer, the living jump layer, the first metal layer, the second metal layer and the first electrode layer on a substrate respectively have a public overlapping region. According to the technical scheme provided by the embodiment of the application, the plurality of capacitor electrodes are arranged in the driving area of the display panel, so that the problem that the energy storage capacitor with small occupied area and large capacitance value is obtained by arranging the plurality of capacitors can be solved.
Description
Technical Field
The present disclosure relates generally to the field of display technology, and more particularly, to a display panel, a display device, and a method of manufacturing the display panel.
Background
Organic Light Emitting Diode (OLED) display devices have good image quality, self-luminescence, no viewing angle obstruction, large operating temperature range, and the like, and have been considered as a new generation of flat panel display devices having market value following liquid crystal display and plasma display devices. In order to obtain an OLED device with good display performance, the design structure of the TFT circuit is also important. In the design process of TFT circuits, it is desirable to obtain a large enough capacitance to enhance the charging effect during driving, and at the same time, for bottom-emitting OLED devices, it is also desirable to increase the aperture ratio, and the increase of the area of the capacitor electrode will decrease the aperture ratio, so how to solve the above-mentioned problems is a need.
Disclosure of Invention
In view of the above-described drawbacks or shortcomings in the related art, it is desirable to provide a display panel, a display device, and a method of manufacturing a display panel having a large capacitance and an improved aperture ratio.
In a first aspect, a display panel is provided, where a sub-pixel area of the display panel includes a driving area and a display area, the driving area includes a transistor area and a functional area, the functional area includes a substrate, a light shielding layer, a buffer layer, a transition layer, a gate insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and an electrode layer, which are sequentially stacked, where orthographic projections of the light shielding layer, the transition layer, the first metal layer, the second metal layer, and the first electrode layer on the substrate respectively have a common overlapping area.
In some embodiments of the present invention, in some embodiments,
the shading layer, the active jump layer, the first metal layer, the second metal layer and the first electrode layer are respectively used as electrodes of the energy storage capacitor.
In some embodiments of the present invention, in some embodiments,
the shading layer and the active layer are respectively used as a first electrode and a second electrode of the first capacitor;
the first metal layer and the active layer are used as a first electrode and a second electrode of the second capacitor;
the first metal layer and the second metal layer are respectively used as a first electrode and a second electrode of the third capacitor;
the first electrode layer and the second metal layer are respectively used as a first electrode and a second electrode of the fourth capacitor.
In some embodiments, the second metal layer and the active layer are connected by a first via.
In some embodiments, the light shielding layer and the first metal layer are connected by a second via
The method comprises the steps of carrying out a first treatment on the surface of the The first metal layer and the first electrode layer are connected through a third via hole.
In some embodiments, the second metal layer and the first electrode layer are each for external electrical connection.
In some embodiments, the drive region includes a thin film transistor including a metal shielding layer, an active layer, a gate electrode, a source drain electrode, and a second electrode layer stacked in this order,
the shading layer and the metal shielding layer are arranged on the same layer;
the active layer and the active layer are arranged on the same layer;
the first metal layer and the grid are arranged on the same layer;
the second metal layer and the source drain electrode are arranged on the same layer;
the first electrode layer and the second electrode layer are arranged on the same layer.
A second aspect provides a display device including a display panel according to embodiments of the present application.
In a third aspect, there is provided a method of manufacturing a display panel, a sub-pixel region of the display panel including a driving region and a display region, the driving region including a functional region and a transistor region, the method comprising the steps of:
forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
forming a buffer layer;
forming an active layer and an active layer in the functional region and the transistor region, respectively;
forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
coating photoresist, forming a photoresist pattern on the active layer which does not need to be conductive, and conducting the active layer and part of the active layer which needs to be conductive;
removing the photoresist pattern, and forming a first metal layer and a grid electrode in the functional area and the transistor area respectively;
forming a dielectric layer;
forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
a passivation layer and an electrode layer are formed.
In a fourth aspect, there is provided a method of manufacturing a display panel, in which a sub-pixel region of the display panel includes a driving region and a display region, the driving region includes a functional region and a transistor region, the method comprising the steps of:
forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
forming a buffer layer;
forming an active layer and an active layer in the functional region and the transistor region, respectively;
forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
forming a grid electrode in the transistor area;
a conductive activation layer and a part of an active layer requiring conductive activation;
forming a first metal layer in the functional area;
forming a dielectric layer;
forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
a passivation layer and an electrode layer are formed.
According to the technical scheme provided by the embodiment of the application, the plurality of capacitor electrodes are arranged in the driving area of the display panel, so that the problem that the energy storage capacitor with small occupied area and large capacitance value is obtained by arranging the plurality of capacitors can be solved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
fig. 1 shows an exemplary structural block diagram of a display panel according to an embodiment of the present application;
FIG. 2 illustrates an exemplary cross-sectional view of an AA' according to an embodiment of the present application;
fig. 3 shows an exemplary flowchart of a method of manufacturing a display panel according to an embodiment of the present application;
fig. 4 illustrates an exemplary flowchart of a method of manufacturing a display panel according to another embodiment of the present application;
fig. 5 to 12 are specific exemplary diagrams illustrating a manufacturing method of the display panel according to fig. 3;
fig. 13 to 15 show specific exemplary schematic diagrams according to the display panel manufacturing method in fig. 4.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1 and 2, the sub-pixel region of the display panel includes a driving region 20 and a display region 10, the driving region 20 includes a transistor region D1 and a functional region D2, the functional region D2 includes a substrate (not shown), a light shielding layer 101, a buffer layer 102, an active layer 103, a gate insulating layer 104, a first metal layer 105, a dielectric layer 106, a second metal layer 107, a passivation layer 108 and a first electrode layer 109, which are sequentially stacked, wherein orthographic projections of the light shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107 and the first electrode layer 109 on the substrate respectively have a common overlapping region.
The common overlap region here refers to the common overlap region of the light shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109, and is not limited to any two or three of them. The arrangement of the functional region of the multi-layered structure in the non-transistor region of the drive region provides the possibility of arranging more components in a limited area.
In some embodiments, the light shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109 are respectively used as electrodes of the storage capacitor.
The driving circuit of the sub-pixel comprises an energy storage capacitor, the size of the energy storage capacitor directly influences the driving effect of the electroluminescent device, and the larger the capacitance of the energy storage capacitor is, the stronger the driving capability of the energy storage capacitor is. The larger the areas of the two electrodes oppositely arranged in the energy storage capacitor are, the larger the capacitance value is, and the increase of the area of the capacitor electrode increases the duty ratio of the driving area in the whole sub-pixel area, so that the duty ratio of the display area 10 is reduced, and the aperture ratio of the sub-pixel is reduced. The application adopts a mode that a plurality of capacitors are connected in parallel, so that the area of the capacitor electrode is reduced. Therefore, how to set the level of the electrodes in the functional region will be key to solving the above-described problem.
The functional area is provided with a plurality of layers which can be used as capacitance electrodes, including a shading layer 101, an active layer 103, a first metal layer 105, a second metal layer 107 and a first electrode layer 109. The capacitor electrode may be set according to the requirements of the application scenario, which is not limited herein. The remaining layers, buffer layer 102, gate insulating layer 104, dielectric layer 106, and passivation layer 108, can be used as insulating layers between the capacitor electrodes, and can form a thin film capacitor or parasitic capacitor with the electrodes on both sides thereof.
For example, 2 capacitors may be provided in the functional area of the present application: the light shielding layer 101 and the active layer 103 are respectively arranged as a first electrode and a second electrode of a first capacitor, and the first metal layer 105 and the second metal layer 107 are respectively arranged as a first electrode and a second electrode of a second capacitor; alternatively, the active layer 103 and the first metal layer 105 are respectively provided as a first electrode and a second electrode of the first capacitor, and the second metal layer 107 and the first electrode layer 109 are respectively provided as a first electrode and a second electrode of the second capacitor. In addition, there may be other arrangements for setting 2 capacitors, which will not be described here. The first electrode of the first capacitor and the first electrode of the second capacitor are connected through the via hole, and the second electrode of the first capacitor and the second electrode of the second capacitor are connected in parallel.
For another example, 3 capacitors may be provided in the functional area: the light shielding layer 101 and the active layer 103 are respectively used as a first electrode and a second electrode of a first capacitor, the first metal layer 105 and the second metal layer 107 are respectively used as a first electrode and a second electrode of a second capacitor, and the first electrode layer 109 and the second metal layer 107 are respectively used as a first electrode and a second electrode of a third capacitor. The second electrode of the second capacitor and the second electrode of the third capacitor are common electrodes. The first electrode of the first capacitor, the first electrode of the second capacitor and the first electrode of the third capacitor are connected through the through hole, and the second electrode of the first capacitor and the second electrode of the second capacitor are connected in parallel. Alternatively, the light shielding layer 101 and the active layer 103 serve as a first electrode and a second electrode of the first capacitor, the first metal layer 105 and the active layer 103 serve as a first electrode and a second electrode of the second capacitor, and the second metal layer 107 and the first electrode layer 109 serve as a first electrode and a second electrode of the third capacitor, respectively. The second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes. The first electrode of the first capacitor, the first electrode of the second capacitor and the first electrode of the third capacitor are connected through the through hole, and the second electrode of the first capacitor and the second electrode of the third capacitor are connected in parallel. In addition, there may be other parallel connection modes of setting 3 capacitors, which will not be described herein.
It should be noted that, the display area 10 is used for disposing an electroluminescent device; the driving region 20 is used to provide a pixel driving circuit for driving the electroluminescent device of the display region 10. The pixel driving circuit comprises an energy storage capacitor and a plurality of thin film transistors, and specifically can comprise structures such as 6T1C (6 thin film transistors plus 1 energy storage capacitor), 7T1C (7 thin film transistors plus 1 energy storage capacitor) and the like. Accordingly, the driving region 20 may be divided into a transistor region D1 for setting a thin film transistor and a functional region D2 for setting a storage capacitor, as shown in fig. 2. In addition, other transistors in the transistor region, such as the transistor 31, the transistor 32, and the transistor 33, are shown in fig. 1. For ease of illustration, fig. 2 shows only one transistor, and in practice the transistor region may comprise a plurality of transistors.
In some embodiments, the storage capacitor includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor,
the light shielding layer 101 and the active layer 103 serve as a first electrode and a second electrode of the first capacitor, respectively;
the first metal layer 105 and the active layer 103 serve as a first electrode and a second electrode of the second capacitor;
the first metal layer 105 and the second metal layer 107 serve as a first electrode and a second electrode of the third capacitor, respectively;
the first electrode layer 109 and the second metal layer 107 function as a first electrode and a second electrode of the fourth capacitor, respectively.
In the arrangement mode of the capacitor electrodes, the second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes, the first electrode of the second capacitor and the first capacitor of the third capacitor are common electrodes, and the second electrode of the third capacitor and the second electrode of the fourth capacitor are common capacitors. By providing a plurality of common electrodes, 4 capacitances are provided in the functional area with 5 electrodes. The arrangement of the electrodes of the 4 capacitors is given in the application above. Under the condition that the capacitance is the same, the area of the capacitance electrode can be further reduced in comparison with the mode that 2 capacitors are connected in parallel or 3 capacitors are connected in parallel, so that the aperture opening ratio of the pixel is further improved.
In some embodiments, the second metal layer 107 and the active layer 103 are connected by a first via 201. Through the first via 201, a connection between the second electrodes of the 4 capacitances is achieved.
In some embodiments, the light shielding layer 101 and the first metal layer 105 are connected by a second via 202. A connection between the first electrode of the first capacitor and the first electrode of the second capacitor is achieved.
In some embodiments, the first metal layer 105 and the first electrode layer 109 are connected by a third via 203. A connection between the first electrode of the third capacitor and the first electrode of the fourth capacitor is achieved. The parallel connection of 4 capacitors is realized by the first via 201, the second via 202 and the third via 203.
In some embodiments, the second metal layer 107 and the first electrode layer 109 are each configured to receive an external electrical signal. The energy storage capacitor connected with the 4 capacitors in parallel needs to be connected with the peripheral transistors to drive the electroluminescent device, so that the electrodes of the energy storage capacitor are connected with the transistors or are externally connected with the electroluminescent device.
Referring to fig. 2, in some embodiments, the driving region D1 includes a thin film transistor including a metal shielding layer 302, an active layer 301, a gate electrode 303, a source drain electrode 304 and a second electrode layer 305 sequentially stacked,
the light shielding layer 101 is arranged on the same layer as the metal shielding layer 302 of the thin film transistor;
the active layer 103 is arranged on the same layer as the active layer 301 of the thin film transistor;
the first metal layer 105 is arranged in the same layer as the gate electrode 303 of the thin film transistor;
the second metal layer 107 and the source/drain electrode 304 of the thin film transistor are arranged in the same layer;
the first electrode layer 109 is provided in the same layer as the second electrode layer 305 of the thin film transistor.
As shown in fig. 1, the arrangement of the plurality of capacitors should not affect the structure and process of the transistor as much as possible, and therefore, a structure in which the capacitors are arranged at the same layer as a part of the layer of the transistor is adopted. The light shielding layer 101 of the functional area and the metal shielding layer 302 of the thin film transistor may be connected or disconnected, which is not limited herein, and may be set according to an application scenario. Similarly, the first electrode layer 109 of the functional region and the second electrode layer 305 of the thin film transistor may be connected or disconnected, and may be set according to the application scenario without limitation.
The application also provides a display device which comprises the display panel provided by the embodiments of the application.
Referring to fig. 3, the present application further discloses a manufacturing method of a display panel, wherein a sub-pixel area of the display panel includes a driving area 20 and a display area 10, the driving area 20 includes a functional area D2 and a transistor area D1, and the manufacturing method includes the following steps:
step S101: forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
step S102: forming a buffer layer;
step S103: forming an active layer and an active layer in the functional region and the transistor region, respectively;
step S104: forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
step S105: coating photoresist, forming a photoresist pattern on the active layer which does not need to be conductive, and conducting the active layer and part of the active layer which needs to be conductive;
step S106: removing the photoresist pattern, and forming a first metal layer and a grid electrode in the functional area and the transistor area respectively;
step S107: forming a dielectric layer;
step S108: forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
step S109: a passivation layer and an electrode layer are formed.
The steps are described below with reference to fig. 5 to 12 and fig. 2.
In step S101, as shown in fig. 5, the light shielding layer 101 and the metal shielding layer 302 are formed in the functional region D2 and the transistor D1, respectively. In this embodiment, the light shielding layer 302 of the functional area is connected to the metal shielding layer 101 of the transistor area, and a disconnected structure may be used in the application. The light shielding layer 302 of the functional region and the metal shielding layer 101 of the transistor region may be made of the same material or may be made of different materials, and are not limited thereto.
In step S102, as shown in fig. 6, a buffer layer 102 is formed. The buffer layer 102 covers the entire drive region.
In step S103, as shown in fig. 7, the active layer 103 and the active layer 301 are formed in the functional region D2 and the transistor region D1, respectively, wherein the active layer 301 and the active layer 103 may be made of IGZO (indium gallium zinc oxide ) material, the IGZO having a high electron mobility, and being a channel material in the thin film transistor, thereby improving the resolution of the display panel. The active layer 103 and the active layer 301 are not conductive.
In step S104, as shown in fig. 8, the gate insulating layer 104 is formed and the gate insulating layer of the transistor region D1 is patterned so that the pattern of the gate insulating layer is formed in the region of the active layer 301 where the conductor is not required and the region of the active layer 301 where the conductor is required is exposed.
In step S105, as shown in fig. 9, a photoresist pattern is formed on the active layer 301-1 that does not require conductive. Since the first metal layer 105 is required to be provided in the functional region D2, and if the first metal layer is formed first, the active layer 104 cannot be made conductive, and the active layer has a portion of the active layer 301-1 which does not require conductive, a photoresist is provided in the active layer 301-1 which does not require conductive before the conductive, and the conductive is performed before the first metal layer is formed. The photoresist pattern may be formed by a general etching method, and the photoresist pattern may be remained only in the active layer 301-1 where no conductor is required, or may be exposed by a Half Tone Mask (Half Tone Mask) process, and the photoresist pattern may be remained thicker in the active layer 301-1 where no conductor is required, and thinner in the remaining regions, so that adverse effects of the conductor on other regions may be reduced. During the process of performing the photoresist exposure, a via 202 connecting the first metal layer 105 and the shielding layer 101 may also be formed. Thereafter, the conductive active layer 103 and a part of the active layer 301 to be conductive are obtained, and the conductive active layer 301-2 and the non-conductive active layer 301-1 shown in fig. 9, and the conductive active layer 103 are obtained. The indium gallium zinc oxide may be electrically conductive by using a gas such as H2, he, or NH 3.
In step S106, as shown in fig. 10, the photoresist pattern in step S105 is removed, and the first metal layer 105 and the gate electrode 303 are formed in the functional region and the transistor region, respectively. The first metal layer 105 and the gate electrode 303 are made of the same material, and may be a metal layer with excellent conductivity and good light shielding property, such as a Mo, cu, al film layer or a metal layer. In fabrication, PVD (Physical Vapor Deposition ) may be used to deposit the gate and first metal layer and etch to form the desired pattern.
In step S107, as shown in fig. 11, a dielectric layer 106 is formed. At this time, a via 201 connecting the second metal layer and the first metal layer may be formed.
In step S108, as shown in fig. 12, a second metal layer 107 and a source drain 304 are formed in the functional region and the transistor region, respectively. The second metal layer 107 and the source drain electrode 304 may use the same metal material. The second metal layer 107 and the source drain electrode 304 may be connected or disconnected according to the application scenario, which is not limited herein.
In step S109, as shown in fig. 2, a passivation layer 108 and an electrode layer 109 are formed. After forming the passivation layer 108, a via 203 connecting the electrode layer 109 and the first metal layer 105 may be formed. The electrode layer includes a first electrode layer of the functional region and a second electrode layer of the transistor region, and the first electrode layer and the second electrode layer may be connected to each other or disconnected, not limited herein. The material of the electrode layer may be ITO (indium Tin oxides, indium tin oxide).
Through the above process, a hierarchical structure of the functional region having 5 layers of the capacitor electrode is obtained.
Referring to fig. 4, the present application further discloses a manufacturing method of a display panel, wherein a sub-pixel area of the display panel includes a driving area and a display area, the driving area includes a functional area and a transistor area, and the manufacturing method includes the following steps:
step S101: forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
step S102: forming a buffer layer;
step S103: forming an active layer and an active layer in the functional region and the transistor region, respectively;
step S104: forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
step S105: forming a grid electrode in the transistor area;
step S106: conductive active layer and part of active layer requiring conductive
Step S107: forming a first metal layer in the functional area;
step S108: forming a dielectric layer;
step S109: forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
step S110: a passivation layer and an electrode layer are formed.
The steps are described below in conjunction with fig. 5 to 8, 13 to 15, 10 to 12, and 2.
In step S101, as shown in fig. 5, a light shielding layer 101 and a metal shielding layer 302 are formed in the functional region D2 and the transistor region D1, respectively. In this embodiment, the light shielding layer 302 of the functional region and the metal shielding layer 101 of the transistor region are connected, and may be disconnected in application, which is not limited herein. The light shielding layer 302 of the functional region and the metal shielding layer 101 of the transistor region may be made of the same material or may be made of different materials, and are not limited thereto.
In step S102, as shown in fig. 6, a buffer layer 102 is formed. The buffer layer 102 covers the entire drive region.
In step S103, as shown in fig. 7, the active layer 103 and the active layer 301 are formed in the functional region D2 and the transistor region D1, respectively, wherein the active layer 301 and the active layer 103 may be made of IGZO (indium gallium zinc oxide ) material, the IGZO having a high electron mobility, and being a channel material in the thin film transistor, thereby improving the resolution of the display panel. The active layer 301 and the active layer 103 at this time are not conductive.
In step S104, as shown in fig. 8, the gate insulating layer 104 is formed and the gate insulating layer of the transistor region D1 is patterned so that the pattern of the gate insulating layer is formed in the region of the active layer 301 where the conductor is not required and the region of the active layer 301 where the conductor is required is exposed. .
In step S105, as shown in fig. 13, a gate electrode 302 is formed on the gate insulating layer 104 in the transistor region, and the gate electrode 302 in the transistor region D1 is patterned so that the region of the active layer 301 not requiring conductor formation forms a gate pattern, and the region of the active layer 301 requiring conductor formation is exposed.
In step S106, as shown in fig. 14, the conductive active layer 103 and a part of the active layer 301-2 to be conductive are obtained, and the conductive active layer 301-2 and the non-conductive active layer 301-1 shown in fig. 14 and the conductive active layer 103 are obtained. The indium gallium zinc oxide may be electrically conductive by using a gas such as H2, he, or NH 3. After the conductive treatment, a via 202 connecting the first metal layer 105 and the shielding layer 101 may be formed.
In step S107, as shown in fig. 15, the first metal layer 105 is formed in the functional region. The first metal layer 105 and the gate electrode 303 are made of the same material, and may be a metal layer with excellent conductivity and good light shielding property, such as a Mo, cu, al film layer or a metal layer. In fabrication, PVD (Physical Vapor Deposition ) may be used to deposit a first metal layer and etch to form the desired pattern.
In step S108, as shown in fig. 11, a dielectric layer 106 is formed. At this time, a via 201 connecting the second metal layer and the first metal layer may be formed.
In step S109, as shown in fig. 12, a second metal layer 107 and a source drain 304 are formed in the functional region and the transistor region, respectively. The second metal layer 107 and the source drain electrode 304 may use the same metal material. The second metal layer 107 and the source drain electrode 304 may be connected or disconnected according to the application scenario, which is not limited herein.
In step S110, as shown in fig. 2, the passivation layer 108 and the electrode layer 109 are formed, and after the passivation layer 108 is formed, the via hole 203 connecting the first electrode layer 109 and the first metal layer 105 may be formed. The electrode layers include a first electrode layer 109 of a functional region and a second electrode layer 305 of a transistor region, and the first electrode layer and the second electrode layer may be connected to each other or disconnected, which is not limited herein. The material of the electrode layer may be ITO (indium Tin oxides, indium tin oxide).
Through the above process, a hierarchical structure of the functional region having 5 layers of the capacitor electrode is obtained.
The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Claims (5)
1. A display panel is characterized in that a sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a transistor area and a functional area, the functional area comprises a substrate, a shading layer, a buffer layer, a living jump layer, a gate insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and a first electrode layer which are sequentially stacked, wherein orthographic projections of the shading layer, the living jump layer, the first metal layer, the second metal layer and the first electrode layer on the substrate respectively have a common overlapping area,
the light shielding layer, the active jump layer, the first metal layer, the second metal layer and the first electrode layer are respectively used as electrodes of the energy storage capacitor, the light shielding layer, the active jump layer, the first metal layer, the second metal layer and the first electrode layer form a plurality of electrode layers so as to selectively set the number of the energy storage capacitors according to different layers, the second metal layer and the first electrode layer are respectively used for external electric connection, the second metal layer is connected with the active layer through a first via hole, the light shielding layer is connected with the first metal layer through a second via hole, and the first metal layer is connected with the first electrode layer through a third via hole;
the driving region comprises a thin film transistor, the thin film transistor comprises a metal shielding layer, an active layer, a grid electrode, a source electrode, a drain electrode and a second electrode layer which are sequentially stacked,
the shading layer and the metal shielding layer are arranged on the same layer;
the active layer and the active layer are arranged on the same layer;
the first metal layer and the grid electrode are arranged on the same layer;
the second metal layer and the source drain electrode are arranged on the same layer;
the first electrode layer and the second electrode layer are arranged on the same layer.
2. The display panel of claim 1, wherein the display panel comprises,
the energy storage capacitor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
the shading layer and the active layer are respectively used as a first electrode and a second electrode of the first capacitor;
the first metal layer and the active layer serve as a first electrode and a second electrode of the second capacitor;
the first metal layer and the second metal layer are respectively used as a first electrode and a second electrode of the third capacitor;
the first electrode layer and the second metal layer serve as a first electrode and a second electrode of the fourth capacitor, respectively.
3. A display device comprising the display panel of any one of claims 1-2.
4. A method of manufacturing a display panel, wherein a sub-pixel region of the display panel includes a driving region and a display region, the driving region including a functional region and a transistor region, the method comprising the steps of:
forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
forming a buffer layer;
forming an active layer and an active layer in the functional region and the transistor region, respectively;
forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
coating photoresist, forming a photoresist pattern on the active layer which does not need to be conductive, and conducting the active layer and part of the active layer which needs to be conductive;
removing the photoresist pattern, and forming a first metal layer and a grid electrode in the functional area and the transistor area respectively;
forming a dielectric layer;
forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
and forming a passivation layer and an electrode layer, wherein the second metal layer and the electrode layer are respectively used for external electric connection.
5. A method of manufacturing a display panel, wherein a sub-pixel region of the display panel includes a driving region and a display region, the driving region including a functional region and a transistor region, the method comprising the steps of:
forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;
forming a buffer layer;
forming an active layer and an active layer in the functional region and the transistor region, respectively;
forming a gate insulating layer and patterning the gate insulating layer in the transistor region;
forming a grid electrode in the transistor area;
conducting the active layer and a portion of the active layer requiring conduction;
forming a first metal layer in the functional area;
forming a dielectric layer;
forming a second metal layer and a source drain electrode respectively in the functional region and the transistor region;
and forming a passivation layer and an electrode layer, wherein the second metal layer and the electrode layer are respectively used for external electric connection.
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| CN202010448063.9A CN111584593B (en) | 2020-05-25 | 2020-05-25 | Display panel, display device and manufacturing method of display panel |
| PCT/CN2021/090201 WO2021238549A1 (en) | 2020-05-25 | 2021-04-27 | Display panel, display device, and method for manufacturing display panel |
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| CN111584593B (en) * | 2020-05-25 | 2024-02-23 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN112117311A (en) * | 2020-09-03 | 2020-12-22 | 深圳市华星光电半导体显示技术有限公司 | OLED panel manufacturing method and OLED panel |
| CN113097225B (en) * | 2021-03-19 | 2022-12-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
| CN113594212B (en) * | 2021-07-28 | 2023-09-22 | 合肥鑫晟光电科技有限公司 | Display panel, preparation method thereof and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257677A (en) * | 2015-06-19 | 2016-12-28 | 乐金显示有限公司 | Thin film transistor base plate and the display device of this thin film transistor base plate of use |
| CN107799556A (en) * | 2016-08-31 | 2018-03-13 | 乐金显示有限公司 | Display device |
| CN109585520A (en) * | 2018-12-28 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display module, electronic device |
| CN110729313A (en) * | 2019-11-29 | 2020-01-24 | 京东方科技集团股份有限公司 | Display panel, display panel preparation method and display device |
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| CN107680993B (en) * | 2017-10-23 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | OLED panel and manufacturing method thereof |
| CN111584593B (en) * | 2020-05-25 | 2024-02-23 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257677A (en) * | 2015-06-19 | 2016-12-28 | 乐金显示有限公司 | Thin film transistor base plate and the display device of this thin film transistor base plate of use |
| CN107799556A (en) * | 2016-08-31 | 2018-03-13 | 乐金显示有限公司 | Display device |
| CN109585520A (en) * | 2018-12-28 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display module, electronic device |
| CN110729313A (en) * | 2019-11-29 | 2020-01-24 | 京东方科技集团股份有限公司 | Display panel, display panel preparation method and display device |
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