CN111584575A - OLED display panel and preparation method thereof - Google Patents

OLED display panel and preparation method thereof Download PDF

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CN111584575A
CN111584575A CN202010405353.5A CN202010405353A CN111584575A CN 111584575 A CN111584575 A CN 111584575A CN 202010405353 A CN202010405353 A CN 202010405353A CN 111584575 A CN111584575 A CN 111584575A
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layer
buffer layer
display panel
oled display
buffer
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陈远鹏
徐源竣
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

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Abstract

The application discloses an OLED display panel and a preparation method, wherein the OLED display panel is divided into a driving circuit area and a capacitance area, and the part of the OLED display panel, which is positioned in the driving circuit area, comprises a glass substrate, a shading layer, a buffer layer, a driving circuit layer, a passivation layer and a planarization layer, wherein the shading layer is manufactured on the glass substrate, the buffer layer is deposited on the glass substrate and covers the shading layer, the driving circuit layer is arranged on the buffer layer, the passivation layer is arranged on the driving circuit layer, and the planarization layer is arranged on the passivation layer; the part of the OLED display panel, which is positioned in the capacitance area, comprises the glass substrate and a storage capacitor arranged on the glass substrate, wherein the storage capacitor is provided with a lower electrode plate and an upper electrode plate which are arranged at intervals and oppositely; the driving circuit layer is provided with a source electrode, a drain electrode and a grid electrode which are arranged on the same layer, the lower electrode plate and the light shielding layer are arranged on the same layer, and the upper electrode plate and any one of the source electrode, the drain electrode and the grid electrode are arranged on the same layer.

Description

OLED display panel and preparation method thereof
Technical Field
The application relates to the technical field of display, in particular to an OLED display panel and a preparation method thereof.
Background
An Organic Light Emitting Diode (OLED) display device has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of approximately 180 °, a wide temperature range, and capability of realizing flexible display and large-area full-color display, and is considered as a display device with the most potential development in the industry. A pixel driving circuit of a conventional OLED display panel generally includes a switching thin film transistor (Switch TFT), a driving thin film transistor (Driver TFT), and a storage capacitor (Cst); the switching TFT is controlled by a scan signal for controlling the input of a data signal, the driving TFT for controlling a current through the OLED, and the storage capacitor (Cst) for storing a gray scale voltage to determine a driving current of the driving TFT.
In order to improve the mass production characteristics of the OLED display device, the key point of the technical development is to reduce the manufacturing cost of the array substrate, and the effective means of reducing the cost is to reduce the number of yellow light manufacturing processes. Compared with the traditional top Gate process, the GSD process (Source-Drain Gate integrated preparation process) can effectively reduce the process cost because the Gate (Gate), the Source (Source) and the Drain (Drain) are wired by a metal layer. In addition, as a novel OLED device preparation process, the ink jet printing technology (IJP) has excellent mass production characteristics, particularly has excellent characteristics in the preparation of high-resolution large-size OLED display devices, and for the top-emission OLED display technology, a light-emitting area does not occupy a separate array substrate area independently of a driving circuit, so that the higher aperture ratio can be realized and the display performance of an OLED panel can be improved.
However, since the inkjet printing technology has a high requirement on the flatness of the pixel electrode, and the capacitance region structure of the conventional GSD process is an LS/IGZO/ITO three-layer interlayer capacitance structure, the pixel electrode in the pixel opening region is inevitably deposited directly on the inorganic protective layer without the organic flat layer, so that the requirement on high flatness cannot be guaranteed, and thus the yield of the process is reduced, and the display effect of the OLED display panel is affected.
Therefore, it is important to develop a new capacitor structure to ensure that the capacitance of the storage capacitor meets the requirement of driving the OLED display panel.
Disclosure of Invention
The embodiment of the application provides an OLED display panel and a preparation method, which can ensure that the capacitance value of a storage capacitor can meet the driving requirement of the OLED display panel, and solve the technical problems that when the OLED display panel in the prior art is prepared by adopting an ink-jet printing process, the high flatness requirement cannot be ensured because a pixel electrode in a pixel opening area is directly deposited above an inorganic protective layer without an organic flat layer, the process yield is reduced, and the display effect of the OLED display panel is influenced.
The embodiment of the application provides an OLED display panel, which is divided into a driving circuit area and a capacitance area, wherein the part of the OLED display panel, which is positioned in the driving circuit area, comprises a glass substrate, a shading layer, a buffer layer, a driving circuit layer, a passivation layer and a planarization layer, wherein the shading layer is manufactured on the glass substrate, the buffer layer is deposited on the glass substrate and covers the shading layer, the driving circuit layer is arranged on the buffer layer, the passivation layer is arranged on the driving circuit layer, and the planarization layer is arranged on the passivation layer; the part of the OLED display panel, which is positioned in the capacitance area, comprises the glass substrate and a storage capacitor arranged on the glass substrate, wherein the storage capacitor is provided with a lower electrode plate and an upper electrode plate which are arranged at intervals and oppositely;
the driving circuit layer is provided with a source electrode, a drain electrode and a grid electrode which are arranged on the same layer, the lower electrode plate and the light shielding layer are arranged on the same layer, and the upper electrode plate and any one of the source electrode, the drain electrode and the grid electrode are arranged on the same layer.
In some embodiments, the buffer layer and the gate insulating layer are sequentially disposed between the lower electrode plate and the upper electrode plate from bottom to top.
In some embodiments, the buffer layer includes a first buffer layer and a second buffer layer stacked from bottom to top, the first buffer layer is made of a non-oxide dielectric layer material with a high dielectric constant, and the second buffer layer is made of a dielectric layer material with a low H content; the thickness range of the buffer layer is
Figure BDA0002491041650000021
The first buffer layer has a thickness that is at least 3 times a thickness of the second buffer layer.
In some embodiments, the materials of the source, the drain, the gate, the lower electrode sheet, the upper electrode sheet, and the light shielding layer are all prepared by a first metal layer.
In some embodiments, the first metal layer includes a contact enhancement layer and a main metal routing layer which are stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the thickness of the contact enhancement layer ranges from bottom to top
Figure BDA0002491041650000022
The main metal wiring layer is made of Cu or Cu-containing alloy, and the thickness range of the main metal wiring layer is
Figure BDA0002491041650000023
In some embodiments, the driving circuit layer includes a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed on the semiconductor layer, and the source, the drain, and the gate disposed on the gate insulating layer in the same layer, the source and the drain are respectively connected to two ends of the semiconductor layer, and the source is connected to the light shielding layer through a first via.
In some embodiments, the OLED display panel further includes a pixel electrode disposed on the planarization layer, a pixel defining layer disposed on the pixel electrode, and an organic light emitting layer disposed in a pixel region of the pixel defining layer, the pixel electrode contacting the source electrode through a second via hole.
The embodiment of the application also provides a preparation method of the OLED display panel, which comprises the following steps:
s10, depositing a first metal layer on a glass substrate, wherein the first metal layer forms a light shielding layer and a lower electrode plate which are arranged at intervals through a first yellow manufacturing process;
s20, sequentially depositing a buffer layer and an amorphous oxide semiconductor layer on the glass substrate, wherein the buffer layer covers the shading layer and the lower electrode plate, and the amorphous oxide semiconductor layer forms a patterned semiconductor layer through a second yellow light process;
s30, depositing a gate insulating layer on the buffer layer, and opening a hole in the gate insulating layer by using a third yellow light process;
s40, depositing the first metal layer on the gate insulation layer, performing graphical processing on the first metal layer by using a fourth yellow light process, and etching the first metal layer to form a drain electrode, a gate electrode, a source electrode and an upper electrode plate;
s50, performing self-aligned etching on part of the gate insulating layer through the drain electrode, the gate electrode and the source electrode to form a self-aligned channel region;
s60, depositing a passivation layer and a planarization layer on the buffer layer in sequence, and opening holes in the planarization layer in a patterning mode;
and S70, sequentially preparing a pixel electrode, a pixel definition layer and an organic light emitting layer arranged in a pixel region of the pixel definition layer on the planarization layer.
In some embodiments, in S10, the first metal layer includes a contact enhancement layer and a main metal routing layer stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the thickness of the contact enhancement layer ranges from bottom to top
Figure BDA0002491041650000031
The main metal wiring layer is made of Cu or Cu-containing alloy, and the thickness range of the main metal wiring layer is
Figure BDA0002491041650000032
In some embodiments, in S20, the buffer layer includes a first buffer layer and a second buffer layer stacked from bottom to top, where the material of the first buffer layer is a non-oxide dielectric layer material with a high dielectric constant, and the material of the second buffer layer is a dielectric layer material with a low H content; the thickness range of the buffer layer is
Figure BDA0002491041650000041
The first buffer layer has a thickness that is at least 3 times a thickness of the second buffer layer.
According to the OLED display panel and the preparation method, the storage capacitor is prepared through the specially designed single-layer capacitor structure, the overall dielectric constant of the storage capacitor is improved on the premise that the total thickness of the buffer layer is unchanged, the GSD process technology is used for reducing the number of yellow light processes, the preparation cost is reduced, the storage capacitor value is improved, and the driving requirement of the OLED display panel prepared through the ink-jet printing technology is further met.
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The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional structure diagram of an OLED display panel provided in an embodiment of the present application.
Fig. 2 is a flowchart of a method for manufacturing an OLED display panel according to an embodiment of the present disclosure.
Fig. 3A to 3G are schematic structural diagrams of a method for manufacturing an oled display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
When the OLED display panel in the prior art is prepared by adopting the ink-jet printing process, the high flatness requirement cannot be ensured because the pixel electrode in the pixel opening area is directly deposited above the inorganic protective layer without the organic flat layer, so that the process yield is reduced, and the technical problem of the display effect of the OLED display panel is further influenced.
Fig. 1 is a schematic cross-sectional structure diagram of an OLED display panel according to an embodiment of the present disclosure. The components of the embodiments of the present application and the relative position relationship between the components can be seen from the figure, and the OLED display panel is divided into a driving circuit area and a capacitor area.
Specifically, the portion of the OLED display panel in the driving circuit region includes a glass substrate 101, a light-shielding layer 102 fabricated on the glass substrate 101, a buffer layer 104 deposited on the glass substrate 101 and covering the light-shielding layer 102, a driving circuit layer 105 disposed on the buffer layer 104, a passivation layer 107 disposed on the driving circuit layer 105, and a planarization layer 108 disposed on the passivation layer 107; wherein the driving circuit layer 105 includes a semiconductor layer 1051 disposed on the buffer layer 104, the gate insulating layer 1052 disposed on the semiconductor layer 1051, and a source electrode 1055, a drain electrode 1053, and a gate electrode 1054 disposed on the gate insulating layer 1052 in the same layer, and the source electrode 1055 and the drain electrode 1053 are connected to both ends of the semiconductor layer 1051, respectively.
In one embodiment, the source 1055 is connected to the light shielding layer 102 through a first via 1041. The light shielding layer 102 and the source 1055 are both located in the driving circuit region and are both made of metal, and if the source 1055 is not connected to the light shielding layer 102, when the TFT device operates, a voltage is generated at the source 1055 end, and a capacitance is formed between the source 1055 end and the light shielding layer 102, which affects the device performance. The source 1055 and the light-shielding layer 102 are connected, and zero potential is always maintained between the source 1055 and the light-shielding layer 102, and the influence on the device is small.
Specifically, the part of the OLED display panel located in the capacitor region includes the glass substrate 101 and a storage capacitor (Cst) disposed on the glass substrate 101, the storage capacitor (Cst) having a lower electrode plate 103 and an upper electrode plate 106 which are spaced and disposed oppositely; the lower electrode plate 103 and the light shielding layer 102 are disposed in the same layer, the upper electrode plate 106 and any one of the source 1055, the drain 1053 and the gate 1054 are disposed in the same layer, the buffer layer 104 and the gate insulating layer 1052 are sequentially disposed between the lower electrode plate 103 and the upper electrode plate 106 from bottom to top, and the buffer layer 104 and the gate insulating layer 1052 form a capacitor dielectric layer of the storage capacitor (Cst).
The buffer layer 104 may protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaked from the glass substrate 101; further, the buffer layer 104 includes a first buffer layer and a second buffer layer stacked from bottom to top, the first buffer layer is made of a non-oxide dielectric layer material with a high dielectric constant, such as SiNx(dielectric constant 7.5), and the material of the second buffer layer is a dielectric layer material with low H content, such as SiOx(═ 3.9); further, the thickness of the buffer layer 104 is in the range of
Figure BDA0002491041650000061
(angstrom), the thickness of the first buffer layer is at least 3 times of the thickness of the second buffer layer, so that the overall dielectric constant of the storage capacitor can be improved on the premise that the total thickness of the buffer layer 104 is not changed.
In one embodiment, the materials of the source 1055, the drain 1053, the gate 1054, the lower electrode plate 103, the upper electrode plate 106, and the light shielding layer 102 are all prepared by a first metal layer, which can effectively reduce the manufacturing cost; the first metal layer comprises a contact enhancement layer and a main metal routing layer which are stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the main metal routing layer is made of Cu or Cu-containing alloy; the thickness of the contact enhancing layer is in the range of
Figure BDA0002491041650000071
The thickness range of the main metal wiring layer is
Figure BDA0002491041650000072
In one embodiment, the material of the semiconductor layer 1051 is any one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), and Indium Gallium Zinc Tin Oxide (IGZTO), and the thickness of the semiconductor layer 1051 ranges from
Figure BDA0002491041650000073
The passivation layer 107 is made of SiO2The thickness range of the passivation layer 107 is
Figure BDA0002491041650000074
For protecting the underlying TFT device; the material of the planarization layer 108 is an organic photoresist.
In some embodiments, the material of the gate insulating layer 1052 is SiOx; wherein the oxygen content can be controlled by PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and the thickness of the gate insulating layer 1052 is in the range of
Figure BDA0002491041650000075
The gate electrode 1054, the source electrode 1055, and the drain electrode 1053 form three terminals of a thin film transistor.
In one embodiment, the OLED display panel further includes a pixel electrode 109 disposed on the planarization layer 108, a pixel defining layer 110 disposed on the pixel electrode 109, and an organic light emitting layer 111 disposed in a pixel region of the pixel defining layer 110, wherein the pixel electrode 109 is in contact with the source electrode 1055 through a second via 1081, and a control voltage signal is transmitted to the pixel electrode 109 by controlling whether the source electrode 1055 and the drain electrode 1053 are turned on or not. Preferably, the pixel electrode 109 is formed by laminating a lower ITO (indium tin oxide) film, an intermediate Ag metal film, and an upper ITO (indium tin oxide) film.
In one embodiment, the organic light emitting layer 111 may include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, an electron injection layer, and the like.
In the OLED display panel provided in the embodiment of the present application, the storage capacitor is prepared by using a specially designed capacitor dielectric layer material and a specially designed capacitor dielectric layer thickness, and the storage capacitor is sequentially arranged from bottom to top as the lower electrode plate 103, the buffer layer 104, the gate insulating layer 1052, and the upper electrode plate 106; the buffer layer 104 comprises a first buffer layer and a second buffer layer which are stacked from bottom to top, the first buffer layer is made of a non-oxide dielectric layer material with a high dielectric constant, the second buffer layer is made of a dielectric layer material with a low H content, and the thickness of the high dielectric layer material is limited to be larger than the thickness of a low dielectric material by 3 times or more, so that the overall dielectric constant of the capacitor is improved on the premise that the total thickness of the buffer layer 104 is not changed, the GSD process technology is used for reducing the number of yellow light processes, the preparation cost is reduced, meanwhile, the storage capacitance value is improved, and the driving requirement of the ink-jet printing technology for preparing the OLED display panel is met.
The embodiment of the application also provides a preparation method of the OLED display panel. As shown in fig. 2, a flowchart of a method for manufacturing an OLED display panel is provided in the embodiments of the present application. Wherein the method comprises the following steps:
s10, depositing a first metal layer on a glass substrate 201, wherein the first metal layer is formed by a first yellow process to form a light-shielding layer 202 and a lower electrode sheet 203 disposed at an interval.
Specifically, the S10 further includes:
firstly, providing a glass substrate 201, wherein the glass substrate is divided into a driving circuit area and a capacitance area; then, cleaning the glass substrate 201, and depositing a first metal layer; then, patterning the first metal layer by using a first yellow light process and Wet etching (Wet), forming a light shielding layer 202 with wiring and light shielding functions in the driving circuit area and forming a lower electrode plate 203 of a storage capacitor in the capacitor area; preferably, the first metal layer comprises a contact enhancement layer and a main metal routing layer which are stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the main metal routing layer is made of Cu or a Cu-containing alloy; the thickness of the contact enhancing layer is in the range of
Figure BDA0002491041650000081
Figure BDA0002491041650000082
The thickness range of the main metal wiring layer is
Figure BDA0002491041650000083
As shown in fig. 3A.
S20, sequentially depositing a buffer layer 204 and an amorphous oxide semiconductor layer on the glass substrate 201, wherein the buffer layer 204 covers the light-shielding layer 202 and the lower electrode sheet 203, and the amorphous oxide semiconductor layer forms a patterned semiconductor layer 205 through a second photolithography process.
Specifically, the S20 further includes:
firstly, depositing a buffer layer 204 on the glass substrate 201 by adopting a PECVD process, wherein the buffer layer 204 covers the light shielding layer 202 and the lower electrode plate 203; then, an Amorphous Oxide Semiconductor layer (Amorphous Oxide Semiconductor) is deposited by a pvd (physical Vapor deposition) process on the portion of the buffer layer 204 in the driving circuit region; then, the amorphous oxide semiconductor layer is patterned using a second photolithography process to form a patterned semiconductor layer 205. Preferably, the buffer layer 104 includes a first buffer layer and a second buffer layer stacked from bottom to top. The first buffer layer is made of non-oxide dielectric layer material with high dielectric constant, such as SiNx(7.5), on one hand, the oxidation atmosphere in the PECVD deposition process can be reduced to avoid metal oxidation, and on the other hand, the coverage characteristics of the buffer layer 204 to the light-shielding layer 202 and the lower electrode sheet 203 can be improved; the second buffer layer is made of dielectric material with low H content, such as SiOx(═ 3.9), the influence of a high hydrogen content in the first buffer layer on the semiconductor layer 205 can be avoided. Further, the thickness range of the buffer layer is
Figure BDA0002491041650000091
The first buffer layer has a thickness that is at least 3 times a thickness of the second buffer layer. Preferably, the material of the semiconductor layer 205 is any one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) and Indium Gallium Zinc Tin Oxide (IGZTO), and the thickness of the semiconductor layer 205 ranges from
Figure BDA0002491041650000092
As shown in fig. 3B.
S30, a gate insulating layer 206 is deposited on the buffer layer 204, and a third photolithography process is used to open the gate insulating layer 206.
Specifically, the S30 further includes:
firstly, a gate insulating layer 206 is deposited on the buffer layer 204 by adopting a PECVD (plasma enhanced chemical vapor deposition) process; then, a third yellow light process is used to open a hole in a portion of the gate insulating layer 206 in the driving circuit region, so as to form a source/drain region metal contact hole 2061 and a first via hole 2062; then, a conductor processing is performed on a portion of the semiconductor layer 205 located in the source/drain region metal contact hole 2061, so as to degrade the resistance value of the semiconductor layer 205 in the source/drain region. Preferably, the material of the gate insulating layer 206 is SiOx; wherein the oxygen content can be controlled by PECVD process, and the thickness of the gate insulation layer 1052 is within the range of
Figure BDA0002491041650000093
The portion of the gate insulating layer 206 located in the capacitor region may be used as a portion of a capacitor dielectric layer, as shown in fig. 3C.
S40, depositing the first metal layer on the gate insulating layer 206, patterning the first metal layer by a fourth photolithography process, and etching the first metal layer to form a drain 2071, a gate 2072, a source 2073 and an upper electrode plate 2074.
Specifically, the S40 further includes:
first, the first metal layer is deposited on the gate insulating layer 206 using a PVD process; then, a fourth photolithography process is performed to pattern the first metal layer, and the first metal layer is etched through the photoresist 30 by using a wet etching process, so as to define a drain 2071, a gate 2072, a source 2073 located in the driving circuit region, and an upper electrode 2074 located in the capacitance region. The source 2073 is connected to the light shielding layer 202 through the first via 2062. If the source 2073 is not connected to the light-shielding layer 202, when the TFT device operates, a voltage is generated at the source 2073 end, which may form a capacitor with the light-shielding layer 202, thereby affecting the device performance. The source 2073 and the light-shielding layer 202 are connected, and zero potential is always maintained between the source 2073 and the light-shielding layer 202, which has little influence on the device, as shown in fig. 3D.
S50, a self-aligned channel region 2063 is formed by self-aligned etching of a portion of the gate insulating layer 206 through the drain 2071, the gate 2072 and the source 2073.
Specifically, the S50 further includes:
a self-aligned etching is performed on a portion of the gate insulating layer 206 by using the drain 2071, the gate 2072 and the source 2073 as a dry etching pattern of the gate insulating layer 206, so as to form a self-aligned channel region 2063, as shown in fig. 3E.
S60, depositing a passivation layer 208 and a planarization layer 209 on the buffer layer 204, and opening the planarization layer 209 by patterning.
Specifically, the S60 further includes:
firstly, a passivation layer 208 is deposited on the buffer layer 204 by a PECVD process, the passivation layer 208 completely covers the drain 2071, the gate 2072, the source 2073 and the upper electrode 2074, the passivation layer 208 is made of SiO2The thickness of the passivation layer 208 is in the range of
Figure BDA0002491041650000101
For protecting the underlying TFT device; then, a planarization layer 209 is deposited on the passivation layer 208, the planarization layer 209 is patterned by using a fifth photolithography process, the planarization layer 209 is used to etch the opening of the passivation layer 208, so as to form a second via hole 2091, and the material of the planarization layer 209 is an organic photoresist, as shown in fig. 3F.
S70, a pixel electrode 210, a pixel defining layer 211, and an organic light emitting layer 212 disposed in a pixel region 2111 of the pixel defining layer 211 are sequentially formed on the planarization layer 209.
Specifically, the S70 further includes:
firstly, a metal electrode layer is deposited on the planarization layer 209, and the metal electrode layer is patterned by using a sixth yellow light process to form a pixel electrode 210, the pixel electrode 210 is connected with the source 2073 through the second via hole 2091, and the pixel electrode 109 is formed by laminating a lower ITO (indium tin oxide) film, a middle Ag metal film and an upper ITO (indium tin oxide) film; then, an organic photoresist layer is covered on the pixel electrode 210, and a yellow light process is used to define the pixel region 2111 of the OLED display panel, so as to form a pixel defining layer 211; finally, an organic light emitting layer 212 is prepared in the pixel region 2111 by using an inkjet printing technique, and the organic light emitting layer 212 may include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, an electron injection layer, and the like, as shown in fig. 3G.
In summary, according to the OLED display panel and the manufacturing method provided by the embodiment of the application, the storage capacitor is manufactured by adopting the specially designed single-layer capacitor structure, so that the overall dielectric constant of the storage capacitor is improved on the premise that the total thickness of the buffer layer is not changed, the number of yellow light processes is reduced by using the GSD process technology, the manufacturing cost is reduced, the storage capacitance value is improved, and the driving requirement of the OLED display panel manufactured by the inkjet printing technology is further met.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The OLED display panel and the manufacturing method provided in the embodiments of the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation manner of the present application, and the description of the embodiments above is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. The OLED display panel is characterized in that the OLED display panel is divided into a driving circuit area and a capacitance area, and the part of the OLED display panel, which is located in the driving circuit area, comprises a glass substrate, a shading layer, a buffer layer, a driving circuit layer, a passivation layer and a planarization layer, wherein the shading layer is manufactured on the glass substrate, the buffer layer is deposited on the glass substrate and covers the shading layer, the driving circuit layer is arranged on the buffer layer, the passivation layer is arranged on the driving circuit layer, and the planarization layer is arranged on the passivation layer; the part of the OLED display panel, which is positioned in the capacitance area, comprises the glass substrate and a storage capacitor arranged on the glass substrate, wherein the storage capacitor is provided with a lower electrode plate and an upper electrode plate which are arranged at intervals and oppositely;
the driving circuit layer is provided with a source electrode, a drain electrode and a grid electrode which are arranged on the same layer, the lower electrode plate and the light shielding layer are arranged on the same layer, and the upper electrode plate and any one of the source electrode, the drain electrode and the grid electrode are arranged on the same layer.
2. The OLED display panel of claim 1, wherein the buffer layer and the gate insulating layer are sequentially disposed from bottom to top between the lower electrode sheet and the upper electrode sheet.
3. The OLED display panel according to claim 2, wherein the buffer layer comprises a first buffer layer and a second buffer layer which are stacked from bottom to top, the material of the first buffer layer is a non-oxide dielectric layer material with a high dielectric constant, and the material of the second buffer layer is a dielectric layer material with a low H content; the thickness range of the buffer layer is
Figure FDA0002491041640000011
The first buffer layer has a thickness that is at least 3 times a thickness of the second buffer layer.
4. The OLED display panel of claim 1, wherein the materials of the source, drain, gate, lower electrode sheet, upper electrode sheet, and light shield layer are all prepared from a first metal layer.
5. The OLED display panel of claim 4, wherein the first metal layer comprises a contact enhancement layer and a main metal routing layer which are stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the thickness of the contact enhancement layer is in the range of
Figure FDA0002491041640000012
The main metal wiring layer is made of Cu or Cu-containing alloy, and the thickness range of the main metal wiring layer is
Figure FDA0002491041640000013
6. The OLED display panel of claim 2, wherein the driving circuit layer comprises a semiconductor layer disposed on the buffer layer, the gate insulating layer disposed on the semiconductor layer, and the source, the drain and the gate disposed on the gate insulating layer in the same layer, wherein the source and the drain are respectively connected to two ends of the semiconductor layer, and the source is connected to the light shielding layer through a first via.
7. The OLED display panel of claim 1, further comprising a pixel electrode disposed on the planarization layer, a pixel defining layer disposed on the pixel electrode, and an organic light emitting layer disposed in a pixel region of the pixel defining layer, wherein the pixel electrode contacts the source electrode through a second via.
8. A method of manufacturing an OLED display panel as claimed in claims 1-7, wherein the method comprises:
s10, depositing a first metal layer on a glass substrate, wherein the first metal layer forms a light shielding layer and a lower electrode plate which are arranged at intervals through a first yellow manufacturing process;
s20, sequentially depositing a buffer layer and an amorphous oxide semiconductor layer on the glass substrate, wherein the buffer layer covers the shading layer and the lower electrode plate, and the amorphous oxide semiconductor layer forms a patterned semiconductor layer through a second yellow light process;
s30, depositing a gate insulating layer on the buffer layer, and opening a hole in the gate insulating layer by using a third yellow light process;
s40, depositing the first metal layer on the gate insulation layer, performing graphical processing on the first metal layer by using a fourth yellow light process, and etching the first metal layer to form a drain electrode, a gate electrode, a source electrode and an upper electrode plate;
s50, performing self-aligned etching on part of the gate insulating layer through the drain electrode, the gate electrode and the source electrode to form a self-aligned channel region;
s60, depositing a passivation layer and a planarization layer on the buffer layer in sequence, and opening holes in the planarization layer in a patterning mode;
and S70, sequentially preparing a pixel electrode, a pixel definition layer and an organic light emitting layer arranged in a pixel region of the pixel definition layer on the planarization layer.
9. The method according to claim 8, wherein in the step S10, the first metal layer comprises a contact enhancement layer and a main metal routing layer which are stacked from bottom to top, the contact enhancement layer is made of at least one of Mo, Ti and Ni, and the thickness of the contact enhancement layer is in a range of Mo, Ti and Ni
Figure FDA0002491041640000021
The main metal wiring layer is made of Cu or Cu-containing alloy, and the thickness range of the main metal wiring layer is
Figure FDA0002491041640000031
10. The method according to claim 8, wherein in S20, the buffer layer includes a first buffer layer and a second buffer layer stacked from bottom to top, the first buffer layer is made of a non-oxide dielectric layer material with a high dielectric constant, and the second buffer layer is made of a dielectric layer material with a low H content; the thickness range of the buffer layer is
Figure FDA0002491041640000032
The first buffer layer has a thickness that is at least 3 times a thickness of the second buffer layer.
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